FULL ADDER USING 4X1 MUX

Aim:
To design a full adder program using multiplexer by Verilog HDL program under Altera
Quartus II 9.0 web Editor tool.
Tools required:
Altera Quartus II 9.0
Design:

A

B
Sum Cout
Sum

Cout
Cin=0 Cin=1 Cin=0 Cin=1
0 0 0 1 0 0 Cin 0
0 1 1 0 0 1

Cin
1 0 1 0 0 1

Cin
1 1 0 1 1 1 Cin 1

Logic Diagram:

Source Code:
module fa_mux(sum,cout,a,b,cin);
output cout,sum;
input a,b,cin;
wire cinb;
mux m1(.z(sum),.d0(cin),.d1(cinb),.d2(cinb),.d3(cin),.s0(a),.s1(b));
mux m2(.z(cout),.d0(0),.d1(cin),.d2(cin),.d3(1),.s0(a),.s1(b));
assign cinb=~cin;
endmodule

module mux(z,d0,d1,d2,d3,s0,s1);
input d0,d1,d2,d3,s0,s1;
output z;
reg z;
always @(d0 or d1 or d2 or d3 or s0 or s1)
begin
case({s0,s1})
2'b00: z<=d0;
2'b01: z<=d1;
2'b10: z<=d2;
2'b11: z<=d3;
endcase
end
endmodule

OUTPUT WAVEFORM:







RESULT:
Thus we have designed a full adder using multiplexer by Verilog HDL program under
Altera Quartus II 9.0 web Editor tool.