Digital Electronics - MCQs

Digital Electronics KEE-401
UNIT 1
1. Convert the following decimal number to 8-bit binary.
187
a) (10111011)2
b) (11011101)2
c) (10111101)2
d) (10111100)2
e) None of the above
Answer :a
2. The following hexadecimal number (1E.43)16 is equivalent to
a) (36.506)8
b) (36.206)8
c) (35.506)8
d) (35.206)8
Answer :b
3. If the decimal number is a fraction then its binary equivalent is obtained by the
number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Answer :b
4. The representation of octal number (532.2)8 in decimal is
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
e)None of the above
Answer :a
5. Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160

b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
e)None of the above
Answer :a
6. 1’s complement can be easily obtained by using
a) Comparator
b) Inverter
c) Adder
d) Sub-tractor
e)None of the above
Answer :b
7. The minimum decimal equivalent to 11C.0 is
a) 183
b) 194
c) 268
d) 296
Answer :b
8. The BCD code for a decimal(874)10 is
a) 100001110100
b) 010001111000
c) 100001000111
d) 011110000100
Answer :a
9. The Boolean function A+BC is a reduced form of

a) AB+BC
b) A’B+AB’C
c) (A+B).(A+C)
d) AC+A’B
Answer :c
10. A three variable truth table has high output for input 010,011 and 110. The Boolean
expression for SOP can be written as
a) A’B+BC’
b) AB’+B’C
c) (AB)’+BC
d) AB+(BC)’
Answer :a
11. The expression Y=(A+B)(B+C)(C+A) shows the operation.
a) AND
b) POS
c) SOP
d) NAND
Answer:b
12. Convert the hexadecimal number (1E2)16 to decimal.
a) 480
b) 483
c) 482
d) 484
e)None
Answer:c
13. What is addition of (-64)10 and (80)16?
a) (-16)10
b) (16)10
c) (11000000)2
d) (01000000)2
Answer:d
14. (28)8 is expressed in gray code as which of the following
a) 11000
b) 10100
c) 11110
d) 11111
e) 10101
Answer:c
15. If (135)x +(144)x=(323)x then the value of X
a) 5
b) 3
c) 12
d) 6
Answer:d
16. What is the gray code for binary 101011
a) 101011
b) 110101
c) 011111
d) 111110
Answer:d
17. The Boolean function Y=AB+CD is to be realized using 2 input NAND gates.The
minimum number of gates required is
a) 2
b) 3
c) 4
d) 5
e) 6
Answer:b
18. In the sum of product function f(XYZ)=∑m(2,3,4,5,), the prime implicants are
a) X’Y,XY’
b) X’Y,XY’Z’,XY’Z
c) X’YZ’,X’YZ,XY’
d) X’YZ’,X’YZ,XY’Z
Answer: a
19. Which of the following is complement of essential prime implicant

F(w,x,y,z)= wy+ xy + w’xyz + w’x’y + xz + x’y’z’
a) w,y,xz,x’z’
b) w,y,xz
c) y, x’y’z’
d) y, xz,x’z’
e) none of the above
Answer: d
20. The minterms expansion of f(P,Q,R)=PQ+QR’+PR’ is
a) ∑m(2,3,6,7)
b) ∑m(0,1,3,5)
c) ∑m(0,1,6,7)
d) ∑m(2,3,4,5)
Answer:a
21. On subtracting +28 and +29 using 2’s complement,we get
a) 111111001
b) 000000101
c) 111111010
d) 010101011
Answer:b
22. Excess -3 code for 597 is given by
a) 100011001010
b) 010110010111
c) 010110101101
d) 100010100111
Answer:b
23. Product of sum expression can be implemented using:
a) Both 2 –level OR-AND and NOR logic circuits

b) 2-level XOR logic circuits
c) 2-level OR –AND logic circuits
d) 2-level NOR logic circuits
Answer : a
24. Which of the following is/are non-weighted code.

A. 8-4-2-1 code
B. BCD
C. Excess-3
D. Gray code
a) Only A
b) C is correct
c) D is correct
d) Both C and D is correct
e) Only B is correct
Answer : d
25. The four variable function f in terms of min-terms as f(A,B,C,D)=
∑m(2,3,8,10,11,12,14,15).Using the K-map minimize the function in terms of SOP form
.also give the total number of two input NAND gate required to implement the function
a) F=AD’+AC+B’C and No. of two input NAND gate required=4

b) F=AD’+AC+B’C and No. of two input NAND gate required=6
c) F=A’D’+AC+AB’C and No. of two input NAND gate required=4
d) F=A’D’+AC+AB’C and No. of two input NAND gate required=6
Answer: b
26. Minimize following 3 variable functions.

f(A,B,C,)= ∑m(0,1,6,7)
a) A’B’+AB
b) A+B
c) AB+C’
d) A’+BC’
Answer: a
27. Minimize f = ∑m(1,5,6,12,13,14) + d(4) in SOP minimal form:
a) f = BC' + BC’D' + A'C'D

b) f = BC' + BD' + A'C'D
c) f= BC' D+ ABD' + A'C'D
d) f= BC' + BCD' + A'C'D
Answer: b
28. Simplify the following:

F= ((A+BC')'+D(E+F')')'
a) F=(A+B’C’)(D’+E+F)
b) F=(A+BC’)(D’+E’+F)
c) F=(A+BC’)(D’+E+F)’
d) F=(A+BC’)(D’+E+F)
Answer: d
29. Convert (100001011001)BCD to Excess-3 code
a) (1011 1010 1100)Excess-3

b) (1111 1001 1100) Excess-3
c) (1011 1000 1100) Excess-3
d) (1000 1000 1100) Excess-3
Answer :c
30. Why do we require hamming codes?

a) Error correction
b) Encryption only
c) Decryption
d) Bit stuffing
e)none of the above
Answer :b
UNIT 2
1. Which of the following logic expressions represents the logic diagram shown?
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
e)none of the above
Answer:d
2. The device shown here is most likely a
a) Comparator
b) Multiplexer
c) Adder
d) Demultiplexer
e)none of the above
Answer:d
3. In a multiplexer the output depends on its

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
e)none of the above
Answer: b
4. can be used as parallel to series converter.

a) Decoder
b) Multiplexer
c) Adder
d) Demultiplexer
Answer :b
5. The number of 4x16 decoder required to implement 8 x 256 decoder

a) 16
b) 17
c) 32
d) 48
Answer :e
6. A digital multiplexer can be used for

1) Parallel to serial conversion
2) Many to one switch
3) Generating memory chip select
4) Code conversion
a) 1,2 and 3
b) Only 1
c) 1 and 2 only
d) 1 and 3 only
e) 2 and 3 only
Answer :d
7. How many inputs are required for a 1-of-10 BCD decoder?

a) 4
b) 8
c) 10
d) 2
e)none of the above
Answer :a
8. Which of the following statements is not correct

a) A full adder can be constructed using two half adder and an OR gate
b) Two four bit parallel adder can be cascaded to construct 8-bit parallel adder.
c) Ripple carry adder has addition time independent to the number of bits
d) Carry look ahead adder is used to speed up the parallel addition.
Answer :c
9. Why is parallel data transmission preferred over serial data transmission for most
applications?
a) It is much slower
b) It is cheaper
c) More people use it
d) It is much faster
e)All of the above
Answer :d
10. What distinguishes the look-ahead-carry adder?

a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the final answer
e)None of the above
Answer: c
11. What is one disadvantage of the ripple-carry adder?

a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
d) All of the Mentioned
e)None of the aove
Answer: c
12. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be

a) Y0
b) Y1
c) Y2
d) Y3
e)Invalid output
Answer: d
13. Consider a 4-to-1 multiplexer with two select lines S1 and S0, given belowThe minimal
sum-of-products form of the Boolean expression for the output F of the multiplexer is:
a) P'Q+QR'+PQ'R
b) P'Q + P'QR' +PQR'+ PQ’R
c) P’QR+P’QR’+PQ’R
d) PQR’
Answer: a
14. Consider the circuit above. Which one of the following options correctly represents
f (x, y, z)?
a) xz’+xy+y’z
b) xz’+xy+(yz)’
c) xz+xy+(xy)’
d) xz+xy’+y’z
e) none othe above
Answer: a
15. Which of the following logic operations is performed by the following given
combinational circuit?
a) XOR
b) X-NOR
c) NAND
d) NOR
Answer: a
16. The logic operations of two combinational circuits in Figure-I and Figure-II are
a) Entirely different
b) Identical
c) Complementary
d) Dual
Answer: a
17. Minimum number of multiplexers required to realize the following function,f = A'B'C +
A'B'C' Assume that inputs are available only in true form and Boolean constant 1 and 0
are available.
a) 1
b) 2
c) 3
d) 4
Answer: b
18. The BCD adder to add two decimal digits needs minimum of
a) 6 Full adder and 2 half adder
b) 5 Full adder and 2 half adder
c) 4 Full adder and 3 half adder
d) 3 Full adder and 2 half adder
Answer: c
19. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
e)none of the above
Answer: b
20. A binary full-subtractor

a) Consists of two cascaded half- subtractor
b) Contains two half -subtractor and one OR gate.
c) Can subtract any binary number
d) Can be implement out of full adder
Answer: b
21. Which of te following circuit comes under the class of combinational circuits? Select the
correct answer
1) Full subtractor
2) Full adder
3) Half adder
4) JK flip flop
5) Counter
a) Only 1
b) 4 and 5
c) 1,2,and3
d) 3 and 4
Answer: c
22. What is the number of select line required in single input n-output de-multiplexer?
a) 2
b) n
c) 2n
d) Log 2 n
Answer: d
23. Two 16-input MUX drive 2-input MUX,what will be the total input lines?
a) 2-input MUX
b) 4-input MUX
c) 16-input MUX
d) 32-input MUX
Answer: d
24. In a combinational circuit, the output at any time depends only on the at that
time.
a) Voltage
b) Intermediate values
c) Input values
d) Clock pulses
e)none of the above
Answer :c
25. Procedure for the design of combinational circuits are:
A. From the word description of the problem, identify the inputs and outputs and
draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the
circuit for different combination of circuit
C. Simplify the switching expression(s) for the output(s).

D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
Answer: c
26. A digital system consists of types of circuits.

a) 2
b) 3
c) 4
d) 5
e)none of the above
Answer: a
27. Using four –input multiplexer, if BC is taken as Select line while implementing ,what
will be inputs,if the function f(A,B,C)= )=∑m(0,2,3,5,7)
a) I0,I1,I2,I3=A’,A,A’,1
b) I0,I1,I2,I3=A’,1,A’,1
c) I0,I1,I2,I3=A’,A’,0’,1
d) I0,I1,I2,I3=A’,0,0,1
Answer: a
28. If A and B are the inputs of a half adder, the sum is given by
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
e)none of the above
Answer: c
29. If A and B are the inputs of a half adder, the carry is given by
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
e)none of the above
Answer: a
30. Half-adders have a major limitation in that they cannot

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
e)No limitations
Answer: c
UNIT 3
1. How would you describe the counter shown in the figure?
a) 3-bit binary synchronous up counter

b) 3-bit binary ripple up counter
c) 3-bit binary synchronous down counter
d) 3-bit binary ripple down counter
Answer: d
2. For the counter of Q-1, the initial count is Q2 Q1 Q0= 000 . What is the count after 13
clock pulses?(in above question)
a) Q2 Q1 Q0= 000
b) Q2 Q1 Q0= 011
c) Q2 Q1 Q0= 010
d) Q2 Q1 Q0= 111
Answer: b
3. When both inputs of SR latches are low, the latch

a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Answer: c
4. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
e) not defined
Answer: c
5. What is meant by the parallel load of a shift register?
a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Answer: a
6. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first)
a) 1100
b) 0011
c) 0000
d) 1111
e)none of the above
Answer: c
7. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output
shift register with an initial state 01110. After three clock pulses, the register contains
a) 01110
b) 00001
c) 00101
d) 00110
e)none of the above
Answer: c
8. The difference between a combinational circuit and a flip-flop is that

a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states
e) none of the these
Answer: c
9. A register is defined as _
a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
e) none of these
Answer: d
10. A shift register is defined as
a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
e) none of these
Answer: b
11. Which flip flop is used to over come the race around condition?
a)S R flip flop
b) J K flip flop
c) Master Slave flip flop
d) D flip flop
e) none of these
Answer: c
12. Master Slave Flip flop consist of :

a)2 Flip flop
b) 3 Flip flop
c) 4 Flip flop
d) 5 Flip flop
Answer: a
13. The difference between a combinational circuit and a flip-flop is that

a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states
e) none of these
Answer: c
14. The minimum number of flip-flops that can be used to construct a modulus-5 counter is
a) 3
b) 8
c) 5
d) 10
e) none
Answer :a
15. MOD-16 counter requires no. of states.
a) 8
b) 4
c) 16
d) 32
e)64
Answer :c
16. High speed counter is

a) Ring counter
b) Ripple counter
c) Synchronous counter
d) Asynchronous counter
Answer: c
17. Which of the following statements are true?

a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
Answer :a
18. In a 3-bit asynchronous down counter, the initial content is

a) 000
b) 111
c) 010
d) 101
e)100
Answer :a
19. Consider the following statements:

1) Race around condition occurs in a JK flip flop when both the inputs are one.
2) A flip flop is used to store one bit of information.
3) A transparent latch consists of D flip flop
4) Master –slave configuration in flip flop to store two bit of information
20. Which of these statements are correct:
a) 1,2,and 3
b) 1,3 and 4
c) 1,2 and 4
d) 2,3 and 4
e) None of these
Answer :a
21. Assertion (A):An unclocked flip flop is called latch.

Reason( R):A latch is constructed using two cross coupled NAND gates or NOR gates
a) Both A and R are true,and R is the correct explaination of A
b) Both A and R are true,and R is not the correct explaination of A
c) A is true but R is false
d) A is false but R is true
e) None of these
Answer :b
22. The digital circuit as shown in figure below represents to which one of the following?
a) J-K flip-flop
b) S-R flip-flop
c) T flip-flop
d) Master-slave flip-flop
e) None of these
Answer :b
23. If tp is pulse width ,td is propagation delay,T is the period of pulse train then which of the
following condition can avoid the race around condition?
a) 2tp > td>T
b) tp = td=T
c) 2tp < td<T
d) 2tp < td>T
Answer :d
24. Characteristic equation of T flip flop is given by:
a) Qn+1= TQn’ + T’ Qn
b) Qn+1= T + T’ Qn
c) Qn+1= (TQn)’ + T’ Qn
d) Qn+1= (TQn)’
e) None of the above.
Answer :a
25. In a J-K flip_ flop we have J=Q’ and K= 1(as shown in figure ).Assuming flip flop was
initially cleared and then clocks for 6 –pulses, the sequence at the Q output will be:
a) 010000
b) 110010
c) 010101
d) 101010
Answer :d
26. When the flip flop is reset then the output will be:
a) Q= 1 and Q’ = 0
b) Q= 0 and Q’ = 0
c) Q= 1 and Q’ = 1
d) Q= 0 and Q’ = 1
Answer :d
27. Assertion (A):The indeterminate condition of J-K flip flop is permitted in S-R flip flop.
Reason( R):A J K flip flop has a characteristic similar to that of an S-R flip flop.
a) Both A and R are true, and R is the correct explanation of A
b) Both A and R are true, and R is not the correct explanation of A
e) None of these
Answer :d
28. Assertion (A):A flip flop is bistable multi vibrator

Reason( R):A flip flop remains in one stable state indefinitely until it is directed by an
input signal to switch over the other stable state
a) Both A and R are true, and R is the correct explanation of A
b) Both A and R are true, and R is not the correct explanation of A
e) None of these
Answer :a
29. A 4-bit ripple counter consists of flip flops that each have propagation delay of 12 ns
from clock to Q output For the counter to recycle from
1111 to 000, it takes a total of :
a) 12 ns
b) 24 ns
c) 48 ns
d) 26 ns
Answer :c
30. A pulse train with a frequency of 1 MHz is counted using mod 1024 ripple counter built
with J-K flip flops. For proper operation of counter the maximum permission able
propagation delay per flip flop stage is:
a) 100ns
b) 20 ns
c) 10ns
d) 50ns
Answer :a
31. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three

clock pulses, the data outputs are
a) 1110
b) 0001
c) 1100
d) 1000
Answer: a
UNIT 4
1. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
e)None of the above.
Answer: c
2. One of the major drawbacks to the use of asynchronous counters is that

a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high-
and low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-
frequency applications
e)none of the above
Answer: b
3. If the output of a digital circuit makes a momentary transition to logic 1,while otherwise
the output is logic 0,it is called a
a) Static-1 hazard
b) Static-0 hazard
c) Dynamic hazard
d) No hazard
e) All of the above
Answer: b
4. Which of the following statement is correct ?

a) Mealy machine output depends on input only.
b) Mealy machine output depends on input and current state.
c) Moore machine output depends on input only.
d) Moore machine output depends on input and current state
Answer: b
5. Two states are said to be equivalent if:

a) Set of inputs generate exactly same output
b) Set of inputs generate exactly same output and same next state
c) Set of inputs generate exactly same next state
d) All of the above
Answer: b
6. The process of assigning states of a physical device to sates of a sequential machine is

known as
a) State reduction
b) State assignment
c) State table
d) States
Answer: c
7. The number of directed arcs terminating on any of state diagram is:

a) 2n, where n is no. of input
b) 2n, where n is no. of flip flop in circuit
c) Independent of no. of input
d) Independent of no. of output
Answer: c
8. For designing a finite state machine K-map can be used for minimizing the :
a) Excitation expression of flip flop
b) No. of flip flpos
c) Output logic expression
d) All of the above
Answer: a
9. A ripple counter’s speed is limited by the propagation delay of

a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
e)none of the above
10. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total
of
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
e)none of the above
Answer: d
11. A ripple counter’s speed is limited by the propagation delay of

a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
e)none of the above
Answer: a
12. A reliable method for eliminating decoder spikes is the technique called
a) Strobing
b) Feeding
c) Wagging
d) Waving
Answer: a
13. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”.
The third and fourth stages will
a) Continue to count with correct outputs
b) Continue to count but have incorrect outputs
c) Stop counting
d) Turn into molten silicon
Answer: c
14. Modulus refers to

a) A method used to fabricate decade counter units
b) The modulus of elasticity, or the ability of a circuit to be stretched from one mode to
another
c) An input on a counter that is used to set the counter state, such as UP/DOWN
d) The maximum number of states in a counter sequence
e) none of the above.
Answer: d
15. What is a state diagram?
a) It provides the graphical representation of states
b) It provides exactly the same information as the state table
c) It is same as the truth table
d) It is similar to the characteristic equation
Answer: b
16. Program counter in a digital computer

a) Counts the number of programs run in the machine
b) Counts the number of times a subroutine
c) Counts the number of time the loops are executed
d) Points the memory address of the current or the next instruction
Answer: d
17. High speed counter is

a) Ring counter
b) Ripple counter
c) Synchronous counter
d) Asynchronous counter
Answer: c
18. A down counter using n-flip-flops count

a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
Answer: a
19. In order to check the CLR function of a counter

a) Apply the active level to the CLR input and check all of the Q outputs to see if they are
all in their reset state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make
sure that all of the Q outputs are toggling
Answer: a
20. An asynchronous binary up counter, made from a series of leading edge-triggered flip-
flops, can be changed to a down counter by
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)
c) Changing the flip-flops to trailing edge triggering
d) All of the Mentioned
e)none of the above
Answer: d
21. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the
most significant bit is
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Answer: a
22. Why is the extent of propagation delay in synchronous counter much lesser than that of
asynchronous counter?
a) Due to clocking of all flip flops at the same instant
b) Due to increase in number of states
c) Due to absence of connection between output of preceding flip flop and clock of
next one
d) Due to absence of mode control operation.
Answer: a
23. Which type of triggering phenomenon is exhibited by Counters?

a) Edge
b) Level
c) Pulse
d) All of the above
Answer: a
24. On which factor/s does the clock pulse frequency of a counter depend/s for its reliable
operation?
a) Number of flip flops
b) Width of strobe pulse
c) Propagation delay
d) All of the above
Answer: d
25. From the diagram shown below, if the circuit enters into state '5', its next state will be '7'.
If the circuit further enters at state'7', then what would be the desirable next state for
avoiding the lock out condition?
a) 0
b) 3
c) 5
d) 7
Answer: a
26. How many 'D' flip flops will be required for designing the synchronous counter for the
state diagram shown below?
a) 2
b) 3
c) 5
d) 7
Answer: b
27. Which among the following are the sequential circuits entering into the phenomenon of
lock out condition?
a) Bush circuits
b) Bushless circuits
c) Locked circuits
d) Unlocked circuits
Answer: b
28. If the number of states in a counter are 2n, then the value of 'n' is
a) Less than the number of flip flops
b) Greater than the number of flip flops
c) Equal to the number of flip flops
d) Unpredictable
Answer: c
29. From the generalized schematic of Moore circuit given below, what does the
combinational circuit 'C1 ' known as?
a) Previous state decoder

b) Present state decoder
c) Next state decoder
d) Output state decoder
Answer: c
30. According to Moore circuit, the output of synchronous sequential circuit depend/s on
of flip flop
a) Past state
b) Present state
c) Next state
d) External inputs
Answer: b
UNIT 4
1. The FPGA refers to
a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
Answer – b
2. Which type of device FPGA are?

a) SLD
b) SROM
c) EPROM
d) PLD
Answer – d
3. PLA can be use:

a) As a microprocessor
b) As a Dynamic memory
c) To realize a sequential logic circuit.
d) To realize a combinational logic circuit
Answer: d
4. A PLA is similar to a ROM in concept except that:

a) It hasn’t capability to read only
b) It hasn’t capability to read or write operation
c) It doesn’t provide full decoding to the variables
d) It hasn’t capability to write only
Answer: c
5. PLA contains:
a) AND and OR arrays
b) NAND and OR arrays
c) NOT and AND arrays
d) NOR and OR arrays
Answer: a
6. PLA refers to
a) Programmable Loaded Array
b) Programmable Array Logic
c) Programmable Logic Array
d) Programmed Array Logic
Answer: c
7. Permanent instructions that the computer uses when it is turned ON and that cannot be
changed by other instructions are contained in
a) ROM
b) RAM
c) ALU
d) SRAM
Answer: a
8. Density of Dynamic RAM is

a) More than that of static RAM
b) Less than that of the static RAM
c) Equal to that of static RAM
d) Equal to or more than that of the static RAM
Answer: a
9. Which of the following control signals are selected for read and write operations in a
RAM?
a) Data buffer
b) Chip select
c) Read and write
d) Memory
Answer: c
10. How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system?
a) 4
b) 6
c) 8
d) 12
Answer: c
11. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and
a word length of 8 bits?
a) 2
b) 4
c) 6
d) 8
Answer: d
12. The full form of PLD is

a) Programmable Load Devices
b) Programmable Logic Data
c) Programmable Logic Devices
d) Programmable Loaded Devices
Answer: c
13. In PLD, there are provisions to perform interconnections of the gates internally, because
of
a) High reliability
b) High conductivity
c) The desired logic implementation
d) The desired output
Answer: c
14. Why antifuses are implemented in a PLD?

a) To protect from high voltage
b) To increase the memory
c) To implement the programmes
d) As a switching devices
Answer: c
15. Which logic is the fastest of all the logic families?

a) TTL
b) ECL
c) HTL
d) DTL.
Answer: b
16. Sometimes ECL can also be named as _

a) EEL
b) CEL
c) CML
d) CCL
Answer: c
17. In an ECL the output is taken from

a) Emitter
b) Base
c) Collector
d) Junction of emitter and base
Answer: c
18. The ECL behaves as

a) NOT gate
b) NOR gate
c) NAND gate
d) AND gate
Answer: b
19. In ECL the fanout capability is

a) High
b) Low
c) Zero
d) Sometimes high and sometimes low
Answer: a
20. ECL’s major disadvantage is that

a) It requires more power
b) It’s fanout capability is high
c) It creates more noise
d) It is slow
Answer: a
21. The equivalent of emitter-coupled logic made out of FETs is called

a) CML
b) SCFL
c) FECL
d) EFCL
Answer: b
22. At the time of invention, an ECL was called as

a) Source-coupled logic
b) Current Mode Logic
c) Current-steering logic
d) Emitter-coupled logic
Answer: c
23. Integrated injection logic is a class of digital circuits built with

a) Single collector BJT
b) Double emitter BJT
c) Multiple emitter BJT
d) Multiple collector BJT
Answer: d
24. IIL has noise immunity.

a) High
b) Low
c) Neutral
d) Nil
Answer: a
25. In Integrated Injection, logic output is received through the

a) Emitter
b) Base
c) Collector
d) Base Emitter Junction
Answer: c
26. The full form of CMOS is
a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor
c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
Answer: c
27. Two important characteristics of CMOS devices are
a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
Answer: d
28. TTL is a
a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing
Answer: a
29. To increase fan-out of the gate in DTL

a) An additional capacitor may be used
b) An additional resister may be used
c) An additional transistor and diode may be used
d) Only an additional diode may be used
Answer: c
30. A disadvantage of DTL is

a) The input transistor to the resister
b) The input resister to the transistor
c) The increased fan-in
d) The increased fan-out
Answer: b

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Digital Electronics KEE-401

2. The following hexadecimal number (1E.43)16 is equivalent to

4. The representation of octal number (532.2)8 in decimal is

a) 6 * 162 + 13 * 161 + 14 * 160

6. 1’s complement can be easily obtained by using

8. The BCD code for a decimal(874)10 is

9. The Boolean function A+BC is a reduced form of

11. The expression Y=(A+B)(B+C)(C+A) shows the operation.

12. Convert the hexadecimal number (1E2)16 to decimal.

13. What is addition of (-64)10 and (80)16?

15. If (135)x +(144)x=(323)x then the value of X

16. What is the gray code for binary 101011

19. Which of the following is complement of essential prime implicant

20. The minterms expansion of f(P,Q,R)=PQ+QR’+PR’ is

21. On subtracting +28 and +29 using 2’s complement,we get

22. Excess -3 code for 597 is given by

a) Both 2 –level OR-AND and NOR logic circuits

24. Which of the following is/are non-weighted code.

a) F=AD’+AC+B’C and No. of two input NAND gate required=4

26. Minimize following 3 variable functions.

27. Minimize f = ∑m(1,5,6,12,13,14) + d(4) in SOP minimal form:

a) f = BC' + BC’D' + A'C'D

28. Simplify the following:

29. Convert (100001011001)BCD to Excess-3 code

a) (1011 1010 1100)Excess-3

30. Why do we require hamming codes?

2. The device shown here is most likely a

3. In a multiplexer the output depends on its

4. can be used as parallel to series converter.

5. The number of 4x16 decoder required to implement 8 x 256 decoder

6. A digital multiplexer can be used for

7. How many inputs are required for a 1-of-10 BCD decoder?

8. Which of the following statements is not correct

10. What distinguishes the look-ahead-carry adder?

11. What is one disadvantage of the ripple-carry adder?

12. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be

20. A binary full-subtractor

25. Procedure for the design of combinational circuits are:

C. Simplify the switching expression(s) for the output(s).

E. Write down the switching expression(s) for the output(s).

26. A digital system consists of types of circuits.

30. Half-adders have a major limitation in that they cannot

1. How would you describe the counter shown in the figure?

a) 3-bit binary synchronous up counter

3. When both inputs of SR latches are low, the latch

8. The difference between a combinational circuit and a flip-flop is that

12. Master Slave Flip flop consist of :

13. The difference between a combinational circuit and a flip-flop is that

16. High speed counter is

17. Which of the following statements are true?

18. In a 3-bit asynchronous down counter, the initial content is

19. Consider the following statements:

21. Assertion (A):An unclocked flip flop is called latch.

28. Assertion (A):A flip flop is bistable multi vibrator

31. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three

2. One of the major drawbacks to the use of asynchronous counters is that

4. Which of the following statement is correct ?

5. Two states are said to be equivalent if:

6. The process of assigning states of a physical device to sates of a sequential machine is

7. The number of directed arcs terminating on any of state diagram is:

9. A ripple counter’s speed is limited by the propagation delay of

11. A ripple counter’s speed is limited by the propagation delay of

14. Modulus refers to