Title: Introduction to circuit simulation using Spice –CMOS inverter.

Abstract:
The main objectives of this experiment is to learn the designing and implementation by
PSpice simulation software,were used to implement CMOS inverter gates which was derived from
previous experiment CMOS-Inverter. A new kind of inverter circuit was implemented using the
following CMOS Nor and NAND gates and transient analysis was taken.

Introduction:

The main purpose of this experiment was to familiarize with the designing and
implementation by PSpice simulation software of CMOS inverter. While conducting the
experiment, followings were performed:

a) To design an electronic circuit coding on Spice software.

b) To check all the wave shapes very carefully in the oscilloscope.
c) To compare the obtained wave shapes with the theoretical estimated wave shapes.
d) To find the reason for error, if occurred in result, and to draw conclusion on how to overcome.

Theory and Methodology:

CMOS inverter:

CMOS circuits are constructed in such a way that all PMOS transistors must have either an
input from the voltage source or from another PMOS transistor. Similarly, all NMOS
transistors must have either an input from ground or from another NMOS transistor. The
composition of a PMOS transistor creates low resistance between its source and drain contacts
when a low gate voltage is applied and high resistance when a high gate voltage is applied. On
the other hand, the composition of an NMOS transistor creates high resistance between source
and drain when a low gate voltage is applied and low resistance when a high gate voltage is
applied. CMOS accomplishes current reduction by complementing every nMOSFET with a
pMOSFET and connecting both gates and both drains together. A high voltage on the gates will
cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the
gates causes the reverse. This arrangement greatly reduces power consumption and heat
generation. However, during the switching time, both MOSFETs conduct briefly as the gate
voltage goes from one state to another. This induces a brief spike in power consumption and
becomes a serious issue at high frequencies.

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Pre-Lab Homework:
All the topics were gone through related to switching mode, regulator, and buck converter
were gone through.

Logic level of the State of mpu State of mnu Logic level of gate
input VA output
0 On Off 1
1 off on 0

Apparatus:

1. A Windows based PC with Microsoft word processor and Adobe or Foxit pdf reader.

2. Orcad PSpice simulation software student version 9.1.

Precautions:
All the files are saved in the current directory of PSPICE it has to be made sure first in “cir”
format. Otherwise, the files would not be found and executed when they are being called from the
command window.

Circuit Diagram:

Fig: CMOS inverter. Fig: CMOS NAND.

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 Fig: CMOS NOR.

Simulation and Measurement:

By using the PSpice software,the following circuits are designed and the following outputs
are obtained below:

INVERTER:
SIMULATION OF A CMOS INVERTER WITH ASYMMETRIC BEHAVIOR
*LOAD = 50 pF, GATE-LENGTH = 3um, GATE-WIDTH (NMOS) = 4 um, GATE-WIDTH
(PMOS) = 4um
***************DEVICE CONNECTIVITY***************
*MOS-device-name drain-node gate-node source-node body-node MOS-type gate-length gate-
width
mp 3 2 1 1 penh l=3u w=4u
mn 3 2 0 0 nenh l=3u w=4u
cl 3 0 50f
***************VOLTAGE SOURCES*******************
*Constant Voltage Source
*source-name node+ node- parameter
vdd 1 0 5
*Pulsed Voltage Source
*Source-name node+ node- pulse (vmin vmax td tr tf pw per)
vin 2 0 pulse (0 5 1ns 3ns 3ns 10ns 20ns)
**********************SIMULATION**********************
.probe
*dc analysis
* .dc vref vmin vmax vincr

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.dc vin 0 5 0.1
*Transient Analysis
*.tran tincr tstop
.tran 1ns 50ns
************DEVICE MODEL DESCRIPTIONS***************
.model nenh nmos level=2 vto=.85 kp=30e-6 tox=470e-10 nsub=38e14
+ld=0.6e-6 uo=624 uexp=0.055 vmax=20e4 neff=9.8 delta=2.0
+ cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 pb=0.81

.model penh pmos level=2 vto=-.85 kp=12e-6 tox=470e-10 nsub=8.7e14

+ld=0.5e-6 uo=200 uexp=0.18 vmax=12e4 neff=4.0 delta=2.0
+ cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 pb=0.7
**********************ENDING CODE**********************
.end

Fig: Output for Inverter.

NAND:
SIMULATION OF A CMOS INVERTER WITH SYMMETRIC BEHAVIOR
*LOAD = 50 pF, GATE-LENGTH = 3um, GATE-WIDTH (NMOS) = 4 um, GATE-WIDTH
(PMOS) = 12um

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***************DEVICE CONNECTIVITY***************
*MOS-device-name drain-node gate-node source-node body-node MOS-type gate-length gate-
width
mp1 5 2 1 1 penh l=3u w=12u
mp2 5 3 1 1 penh l=3u w=12u
mn1 5 2 4 4 nenh l=3u w=8u
mn2 4 3 0 0 nenh l=3u w=8u
cl 5 0 50f
***************VOLTAGE SOURCES*******************
*Constant Voltage Source
*source-name node+ node- parameter
vdd 1 0 5
*Pulsed Voltage Source
*Source-name node+ node- pulse (vmin vmax td tr tf pw per)
vA 2 0 pulse (0 5 1ns 3ns 3ns 10ns 20ns)
vB 3 0 pulse (0 5 1ns 3ns 3ns 20ns 40ns)
**********************SIMULATION**********************
.probe
*dc analysis
* .dc vref vmin vmax vincr
*.dc vin 0 5 0.1
*Transient Analysis
*.tran tincr tstop
.tran 1ns 80ns
**********************DEVICE MODEL DESCRIPTIONS**********************
.model nenh nmos level=2 vto=.85 kp=30e-6 tox=470e-10 nsub=38e14
+ld=0.6e-6 uo=624 uexp=0.055 vmax=20e4 neff=9.8 delta=2.0
+ cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 pb=0.81

.model penh pmos level=2 vto=-.85 kp=12e-6 tox=470e-10 nsub=8.7e14

+ld=0.5e-6 uo=200 uexp=0.18 vmax=12e4 neff=4.0 delta=2.0
+ cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 pb=0.7
**********************ENDING CODE**********************
.end

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 Fig: Output for NAND.

Results:
CMOS Inverter: Aspect Ratio: WP = 13 WN =4; Load: CL = 50 PF

Fig: DC Analysis Plot

From graph, the gate threshold voltage, Vth=2.5358V
But, Vdd=5V, So, Vdd/2=2.5. So there’s a little bit difference between them.

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 Fig: Transient Analysis Plot

Fig: Falling Time Fig: Rising Time

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CMOS Inverter: Aspect Ratio: WP = 4 WN =4; Load: CL = 50 PF

Fig: DC Analysis Plot

From graph, the gate threshold voltage, Vth=2.0358V

But, Vdd=5V, So, Vdd/2=2.5. So there’s a little bit difference between them.

Fig: Transient Analysis Plot

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 Fig: Falling Time Fig: Rising Time

CMOS Inverter: Aspect Ratio: WP = 20 WN =4; Load: CL = 50 PF.

Fig: DC Analysis Plot

From graph, the gate threshold voltage, Vth=2.0358V
But, Vdd=5V, So, Vdd/2=2.5. So there’s a little bit difference between them

09
 Fig: Transient Analysis Plot

Fig: Falling Time Fig: Rising Time

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DISCUSSIONS:

The code was given to pspice software according to the lab instructor. The software given
output was perfect and time delay was found out form the graph. Fall time and rise time
were not becoming same as it has to be the same.Then in the coding part the width was
made changed then the rise time and fall time was almost same.

CONCLUSIONS:

From the experiment the practical output of NAND and nor was verified using the pspice software.
So it can be said that the inverter’s characteristics depends on the width of the transistor.

References:

[1] Douglas A. Pucknell & Kamran Eshraghian,‟Basic Vlsi Design (Silicon Systems
Engineering)”,3rd edition, pp.# 233-260,Prentice-Hall of India Private LTD.,India,1995, ISBN:
13: 978-0130791535.

[2] by Etienne Sicard & Sonia Delmas Bendhia, “Advanced CMOS Cell Design (Professional
Engineering)”,1st edition,pp.# 250-278, McGraw-Hill, 2007.ISBN-13: 978-0071488365

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