Device Modelling

ENP 302

Submitted by
Mitesh Malani
BT19ECE067

Submitted to
Dr. P. Vasu
(Course Instructor)
 Question 1 -
Simulate the Common-Base(CB) Amplifier using NGSPICE?
(a) Find the gain using the plot?

Diagram -

Code -

Common base amplifier

R1 3 2 15k
R2 2 0 8k
R3 6 0 1k
R4 3 4 2.2k
R5 5 0 1k
C1 1 6 1uF
C2 2 0 1u
C3 4 5 1u
Q1 4 2 6 MOD1
v1 3 0 dc 25
vin 1 0 SIN(0 0.2 1kHz)

.model MOD1 NPN

+IS=1.87573e-15 BF=153.575 NF=0.897646 VAF=10
+IKF=0.410821 ISE=3.0484e-09 NE=4 BR=0.1
+NR=1.00903 VAR=1.92063 IKR=4.10821 ISC=1.94183e-12
+NC=3.92423 RB=8.70248 IRB=0.1 RBM=0.1
+RE=0.111394 RC=0.556972 XTB=1.76761 XTI=1
+EG=1.05 CJE=56.7e-12 VJE=0.83191 MJE=0.23
+TF=3.573e-10 XTF=0.941617 VTF=9.22508 ITF=0.0107017
+CJC=56.7e-12 VJC=0.760687 MJC=0.345235 XCJC=0.9
 +FC=0.49264 CJS=56.7e-12 VJS=0.75 MJS=0.5
+TR=3.55487e-06 PTF=0 KF=0 AF=1
.tran 0.01 10ms
.control
run
set xbrushwidth=3
plot V(5)
plot V(1)
.endc
.end

Input -
Output -
A.

Gain = 4

(b) Do the ac analysis for the above question and find out the mid-band
gain?

Code -

Common base amplifier

R1 3 2 15k
R2 2 0 8k
R3 6 0 1k
R4 3 4 2.2k
R5 5 0 1k
C1 1 6 0.01
C2 2 0 1u
C3 4 5 1u
Q1 4 2 6 MOD1
v1 1 3 0 dc 25
vin 1 0 dc 0 ac SIN(0 0.2 1kHz)
 .model MOD1 NPN
+IS=1.87573e-15 BF=153.575 NF=0.897646 VAF=10
+IKF=0.410821 ISE=3.0484e-09 NE=4 BR=0.1
+NR=1.00903 VAR=1.92063 IKR=4.10821 ISC=1.94183e-12
+NC=3.92423 RB=8.70248 IRB=0.1 RBM=0.1
+RE=0.111394 RC=0.556972 XTB=1.76761 XTI=1
+EG=1.05 CJE=56.7e-12 VJE=0.83191 MJE=0.23
+TF=3.573e-10 XTF=0.941617 VTF=9.22508 ITF=0.0107017
+CJC=56.7e-12 VJC=0.760687 MJC=0.345235 XCJC=0.9
+FC=0.49264 CJS=56.7e-12 VJS=0.75 MJS=0.5
+TR=3.55487e-06 PTF=0 KF=0 AF=1
.ac dec 10 1 5G
.control
run
set xbrushwidth=3
plot V(5)/V(1) xlog
.endc
.end

Output -

Peak value = 38312 Hz (approx)

 Question 2 -
Simulate the 3-input NOR Gate of RTL Logic (Resistor-Transistor
Logic) using NGSPICE?

Diagram -

Code -

*NOR gate using RTL

R1 1 4 1k
R2 2 5 1k
R3 3 6 1k
R4 8 7 1k
Q1 7 4 0 MOD1
Q2 7 5 0 MOD1
Q3 7 6 0 MOD1
V1 8 0 dc 12
Va 1 0 PULSE(0 12 0NS 0NS 0NS 1ms 3ms)
Vb 2 0 PULSE(0 12 0NS 0NS 0NS 3ms 6ms)
Vc 3 0 PULSE(0 12 0NS 0NS 0NS 6ms 12ms)
.model MOD1 NPN
.tran 0.01ms 20ms
.control
run
set xbrushwidth=3
plot V(1)
plot V(2)
plot V(3)
 plot V(7)
.endc
.end

Input -
1. A -

2. B -
3. C -

Output -
 Question 3 -
Simulate the 3-input NOR Gate of DTL Logic (Diode-Transistor
Logic) using NGSPICE?

Diagram -

Code -

R1 1 4 1k
R2 2 5 1k
R3 3 6 1k
R4 7 0 12k
R5 7 8 15k
R6 8 11 100k
R7 10 9 2.2k
C1 7 8 1nF
D1 4 7 Diode
D2 5 7 Diode
D3 6 7 Diode
Q1 9 8 0 MOD1
V1 11 0 -12
V2 10 0 12
Va 1 0 PULSE(0 12 0NS 0NS 0NS 1ms 3ms)
Vb 2 0 PULSE(0 12 0NS 0NS 0NS 3ms 6ms)
Vc 3 0 PULSE(0 12 0NS 0NS 0NS 6ms 12ms)
.model Diode D
.model MOD1 NPN
.tran 0.01ms 20ms
 .control
run
set xbrushwidth=3
plot V(1)
plot V(2)
plot V(3)
plot V(9)
.endc
.end

Input -
1. A -

2. B -
3. C -

Output -

Conclusion -
In question 2 and question 3 , both the outputs are identical.