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VLSI(ECE3002)
Lab Task – 05

Name: KOTARU DRONA PHANI KOWSHIK

Redg.No: 18BEC0175
SLOT: L13+L14
FACULTY: NITHISH KUMAR V

Reg.No:18BEC0175 ECE 3002 VLSI System Design Task. No: 05

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Aim:

Circuit Diagram:

Reg.No:18BEC0175 ECE 3002 VLSI System Design Task. No: 05

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OUTPUT

Now to find the time delay

For fall delay

V(d)= 1.0000015u sec

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V(q)=1.000016u sec

Fall delay(TPDF)=1.000016us-1.0000015us
=14.5ps

For Raise delay

V(d)=2.0000005u sec

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V(q)=2.000016 u sec

Raise Delay(TPDR) =2.000016us - 2.0000005us

=15.8ps
Total propagation delay=((raise delay)+(fall delay))/2
=15.15psec

Average power Consumed

Power of M8 = 4.3524n W

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Power of M5 = -0.311n W

Power of M2 = 44.022n W

Power of M1 = 23.956n W

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Power of M7 = -10.1n W

Power of M6 = 0.969n W

Power of M4 = 6.9405n W

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Power of M3 = -13.02n W

Average power=4.3524 -10.1+0.969-0.311+6.9405-13.02+44.022 + 23.956

=56.8089nW

Inference:

 Here we also get the power in negative for some mosfets.

 We can see in the functionality graph that when clock is 1 then output is equal to the
previous one. And when clock is 0 then output is equal to given input.
 Individual NMOS or PMOS cannot pass both high and low logic levels with equal strength
(i.e. on resistance). A single NMOS device can pass a strong logic 0 but will pass a weak
logic 1. Conversely, a single PMOS device can pass a strong logic 1 but will pass a weak
logic 0.

Result:
The functionality of the negative d-latch was plotted on Lt spice. The tpdr is 15.8 ps and tpdf is 14.5
ps. Then the average delay which is the average of fall delay and raie delay is 15.15ps.The average
power of d-latch is
56.8089nW.

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B.

D FLIP FLOPS

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D FLIP FLOP USING DFF BLOCK

Here the DFF is negative edge tigger so I used clk for making it positive edge
trigger

Output in LTSPICE

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INFERENCE
The D flip flop output ‘Q’ follows input ‘D’ at only raising edges of the clock
and at remaining time it stores the previous value of input .

RESULT
Implentation of D flipflop is done using transmission gate logic and
corresponding outputs are obtained .

Reg.No:18BEC0175 ECE 3002 VLSI System Design Task. No: 05