VLSI SYSTEM DESIGN

(LAB - TASK = 05)

Programme : B.Tech-ECE Semester : FALL-(2019-20)

Name : Pranav Kumar Course Code : ECE3002

REG-NO. : 17BEC0473 Slot : L15+L16

Faculty : Prof. Jagannadha Naidu K Max. Marks : 15

(CMOS INVERTER LAYOUT)

 TASK-05
AIM : - To design a layout for CMOS INVERTER and checking the functionality and
also finding the average propagation delay and average power.

CIRCUIT-DIAGRAM : - (I)-1.CMOS INVERTER (LAYOUT VIEW)

2. LAYOUT WITH NO DRC ERRORS FOUND:-
3. CMOS INVERTER LAYOUT (av_extracted view):-

CIRCUIT-DIAGRAM : - (II)- 1. CMOS INVERTER (SCHEMATIC-VIEW WITHOUT VOLTAGE SOURCES).

2. CMOS INVERTER LAYOUT (SYMBOL)

3. CMOS INVERTER (TEST_SCHEMATIC VIEW WITH VOLTAGE SOURCES) = CONFIG VIEW

4. CMOS INVERTER WITH HIERARCHY EDITOR (LAYOUT VIEW/av_extracted view) = CONFIG VIEW

5. CMOS INVERTER WITH HIERARCHY EDITOR (SCHEMATIC VIEW) = CONFIG VIEW

PLOTS : - 1. TRANSIENT-ANALYSIS (STOP-TIME = 100 ns)

1. CHECKING-FUNCTIONALITY :-

2. PLOTTING POWER SIGNAL :- (FOR CMOS INVERTER SCHEMATIC VIEW)

CALCULATIONS AND OBSERVATIONS :- (FOR CMOS INVERTER SCHEMATIC VIEW)

1. AVERAGE POWER DISSIPATED = 59.7 nW (SIMULATION RESULT SHOWN BELOW)

 2. AVERAGE PROPAGATION DELAY :- (BETWEEN in (I/P) TO out (O/P))

RISE-PROPAGATION DELAY (AT 50 PERCENT OF THE FINAL VALUE (VDD = 1.2 V)) :-

(I/P) t1 = 25.0015 ns , (O/P) t2 = 25.005 ns

tpdr = t2-t1 = 0.0035 ns = 3.5 ps

FALL-PROPAGATION DELAY (AT 50 PERCENT OF THE FINAL VALUE (VDD = 1.2 V)) :-

(I/P) t3 = 50.0005 ns , (O/P) t4 = 50.0064 ns

tpdf = t4-t3 = 0.0059 ns = 5.9 ps

AVERAGE-DELAY (tpd) = (tpdr + tpdf)/2 = (3.5 + 5.9)/2 = 4.7 ps.

PLOTS : - 3. TRANSIENT-ANALYSIS (PROPAGATION-DELAY)(BETWEEN in TO out)

(SCHEMATIC-VIEW)
 3. PLOTTING POWER SIGNAL :- (FOR CMOS INVERTER LAYOUT VIEW) = (av_extracted view)

CALCULATIONS AND OBSERVATIONS :- (FOR CMOS INVERTER LAYOUT VIEW) = (av_extracted view)

4. AVERAGE POWER DISSIPATED = 68.57 nW (SIMULATION RESULT SHOWN BELOW)

 5. AVERAGE PROPAGATION DELAY :- (BETWEEN in (I/P) TO out (O/P))

RISE-PROPAGATION DELAY (AT 50 PERCENT OF THE FINAL VALUE (VDD = 1.2 V)) :-

(I/P) t1 = 25.0015 ns , (O/P) t2 = 25.0063 ns

tpdr = t2-t1 = 0.0048 ns = 4.8 ps

FALL-PROPAGATION DELAY (AT 50 PERCENT OF THE FINAL VALUE (VDD = 1.2 V)) :-

(I/P) t3 = 50.0005 ns , (O/P) t4 = 50.0076 ns

tpdf = t4-t3 = 0.0071 ns = 7.1 ps

AVERAGE-DELAY (tpd) = (tpdr + tpdf)/2 = (4.8 + 7.1)/2 = 5.95 ps.

PLOTS : - 4. TRANSIENT-ANALYSIS (PROPAGATION-DELAY)(BETWEEN in TO out)

(LAYOUT-VIEW = (av_extracted view))

RESULT: - From the above calculations and observations we found that layout
view (i.e., av_extracted view) has more average propagation delay and average
power dissipation than schematic view of CMOS INVERTER.

Above plot shows that :- Blue curve = SCHEMATIC VIEW & Red curve = av_extracted view

Hence , that layout view (i.e., av_extracted view) has more average propagation
delay and average power dissipation than schematic view of CMOS INVERTER.

INFERENCE: - The layout for CMOS INVERTER was designed and the functionality
was also checked. The average power dissipated and propagation delay were also
calculated for both schematic and layout view.