PEDS2009

Digital Primary-Side Sensing Control for Flyback Converters

Che-Wei Chang, Yu-Tzung Lin, Student Member, IEEE and Ying-Yu Tzou, Member, IEEE
Power Electronic Systems & Chips Lab. Department of Electrical Engineering, National Chiao Tung Univ., Hsinchu, Taiwan.
AbstractPrimary-side sensing (PSS) technique can be used for the output voltage or current regulation by employing an auxiliary winding. However, the sensed voltage may be corrupted by switching noise due to leakage inductance, winding resistance, and nonlinearity of the magnetic core, therefore the sensed voltage can only achieve limited accuracy. With the advance of power control IC realization technology, more complicated control and estimation algorithms can be realized by using analog, digital, or mixed-signal technologies. This paper introduces a digital control method to make the influence of nonideal factors as low as possible. A key factor for accurate voltage sensing is the determination of sampling instant on the auxiliary winding. A prototype of a DCM DC/DC flyback converter with digital signal processor has been realized to verify the proposed digital PSS scheme. Index TermsPrimary-side sensing, digital control, flyback.

I. INTRODUCTION Conventional flyback converters utilize an error amplifier and an opto-coupler to implement the voltage feedback compensation and galvanic isolation. Although Flyback converter topology gets its wide applications in low-power and low-cost isolated switching power supplies due to its low component counts without a secondary output filter inductor, it suffers from the CTR (current transfer ratio) degradation due to temperature rise for low-cost optocouplers. This makes a constraint on operating temperature for the flyback converter in applications to high power loads. The elimination of the opto-coupler provides significant advantages such as higher power density, cost down, and lower standby power. Therefore, primary-side sensing (PSS) technique, which senses the output voltage from the primary or auxiliary winding of the transformer without using the opto-coupling circuit, becomes an important issue for the development of more sophisticated flyback control ICs. Another motivation to develop PSS technique is that there is a low frequency pole at 20-30 kHz from the opto-coupler. This pole complicates the feedback loop design and limits the crossover frequency. Recently, in order to get a higher crossover frequency in voltage loop, engineers may implement secondary-side control, which places the controller at the secondary side and transmits the pulsewidth-modulation (PWM) signal through a pulse transformer or a high-speed photodetector to eliminate the low frequency
This work was supported by the National Science Council, Taipei, Taiwan, R. O. C. Project no. NSC 96-2622-E-009-013.

pole, but the start-up circuit needs the electrical isolation from the input power [1]. Hence, PSS technique combines the advantages of primary-side control and secondary-side control to become an attractive choice. The output voltage appears on the primary winding during the power switch off state, therefore the PSS technique can extract the output voltage from the primary side [2]-[5]. The requirement for this method is the implementation of high voltage sensing circuits and suffers from coupling noises due to primary leakage inductance. Another approach is to adopt an additional auxiliary winding to detect the output voltage [6]-[10]. This auxiliary winding can be used for both power supplying and voltage sensing and it provides advantages such as low-voltage IC manufacturing process for the implementation of CMOS controller for cost reduction, better winding mechanism for the reduction of coupling noises, lower standby power consumption using the same IC manufacturing process. The accuracy of sensing the output voltage indirectly from the auxiliary winding will be influenced by practical factors, such as cross coupling effect, voltage drop across secondary winding, and switching oscillations induced by leakage inductance, magnetization inductance, and the output junction capacitance of the switching device. The PSS error analysis has been developed in [11]. In accordance with the regulatory agencies of the intended market, such as IEC950 in Europe and UL1950 in the U.S., Commercial flyback transformers must provide galvanic isolation between primary and secondary winding. Different approaches can be adopted to meet the required safety regulations. Cores and bobbins are usually selected large enough meet the creepage distance requirement as well as to maintain transformer coupling and reduce leakage inductance. Cross coupling between transformer windings should be attended when we sense the output voltage from the auxiliary winding. This paper describes PSS technique in section II. And then, the analysis and design of a DCM DC-DC flyback converter are discussed in section III. A prototype of a DCM DC-DC flyback is implemented to verify PSS technique, and the experimental results are shown in section IV. Finally, Section V is the conclusion.

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Llkp

ip

+ vin

vc +

L vM M +

Np

Ns

Llks

is

Co Na Llka ia

RL

+ vo

vM 1 v vM

M2

vM 3

+ vaux
Rac1 Rac 2

Duty

Co

+ Vcc

p i iM ic

Gate Drive

+ vsense

TMS320F2812

PWM Generator
VADC

Vduty

C ( z)
Vdelay

v fb A

vref

ia

a i s1 i t1 t2 t3 s 2 i t4 T3

Sampling instant

is

Fig. 1. The proposed flyback converter with primary-side sensing.

T1 T2
II. PRIMARY-SIDE SENSING TECHNIQUE In this paper, the output voltage is sensed from the auxiliary winding of the flyback transformer. The proposed flyback converter with PSS is conceptually shown in Fig. 1. All definitions and equations in this section are based on [11]. The power switch off state can be divided into three intervals T1, T2, and T3. The definitions of interval T1, T2, and T3 are shown in Fig. 2. All components and parameters in the secondary and auxiliary side converted to the primary side = nvo , where n are noted with prime as x. For instance, vo represents the turn ratio from the primary side to the secondary side. It is recommended to sense the output voltage during interval T3, so the lengths of interval T1, T2, and T3 are necessary to be estimated as

switch on

switch off

Fig. 2. The definitions of interval T1, T2, and T3.

Llks : leakage inductance in the secondary winding Llka : leakage inductance in the auxiliary winding vo : output voltage vaux : voltage on the auxiliary winding vc : clamp voltage on the RCD snubber p : peak current through the power switch. i When the output voltage is sensed in interval T3 from the auxiliary winding, the voltage on the auxiliary winding is
vaux = Ks Na (vo + v D + i s Rs ) 1+ Ks Ns

(4)

T1 =

p LM i Kp
p LM i Kp

1+ K p + Ks + Ka K a v aux vc (1 + K s + K a ) K s v o

(1)

= neff (vo + v D + is Rs )

T2 =

[K s vo + K p vc vaux (1 + K s + K p )]
K a v aux ] [vc (1 + K s + K a ) K s vo

(1 + K s + K a ) + v ) (v aux aux K s K s v o p LM (v v )(1 + K ) i aux o s T3 = v aux + K s (v aux vo ) vo

(2)

where neff is defined as the effective turns ratio, vD is the voltage drop of the secondary diode, and Rs is the winding resistance at the secondary side. The system estimates the output voltage from the voltage on the auxiliary winding. The sensing error can be derived as
v = vo,est vo = vaux vo neff

(5)

(3)

= v D + i s Rs .

where

, K a = LM Llka , K p = LM Llkp , and K s = LM Llks

LM : magnetizing inductance Llkp : leakage inductance in the primary winding

The proposed PSS control scheme was implemented by a single-chip DSP controller, the TMS320F2812, to study its feasibility. The control procedure includes three major steps: (1) sample the sensed voltage from the auxiliary winding. (2)

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Counter

VADC
Vduty
VdelayTCLK TCLK T3 VdelayTCLK T3

Vdelay

ref = 0 v
Vtri

C( z)

 V duty

DPWM

 d
sense v

o v (s)  d
H

o v

K ADC
Ts
Fig. 4.

T 1 + T2

T1 + T2

vaux

The block diagram of a DCM DC-DC Flyback Converter with PSS.

Sample and Hold

ref = 0 v
on off on off

C ( s)
Ts

 V duty

DPWM
sense v

 d

o v (s)  d
H

o v

Sampling instant

K ADC
The mechanism to set the sampling instant.

Fig. 3.

Fig. 5. The continuous time equivalent model of the digital control loop.

Calculate duty command Vduty to regulate the output voltage for flyback converters. (3) Set the sampling instant by VADC = Vdelay + Vduty. The mechanism to set the sampling instant is shown in Fig. 3. The more detailed timing diagram of PSS algorithm in the DSP chip will be mentioned in section IV. III. ANALYSIS AND DESIGN OF A DCM DC-DC FLYBACK CONVERTER WITH PSS A. Dynamic model Although the system is implemented by PSS, the controlto-output transfer function is the same as the conventional flyback converter and is expressed as ~ vin v 2 LM 1 o (6) with K = ~ (s) = s R d K 1+ L Ts 2 / RL Co where Ts is the switching period. For this prototype, the block diagram is shown in Fig. 4. The dynamic model of digital trailing edge pulse-width-modulation (DPWM) block is obtained from [12] and can be expressed as ~ e sDTs d ( ) = (7) s ~ Vtri Vduty where Vtri is the peak value of the sawtooth carrier in the DPWM. The exponential term represents a delay factor and can be simplified by the first-order Pade Approximation, so (7) can be expressed as
1 ~ 1 DTs s d 1 2 . (8) ~ ( s) 1 V Vduty tri 1 + DTs s 2 In (8), the DPWM is a linear phase system. The feedback path is composed by the transformer and the voltage divider, so the feedback gain H can be obtained as

H = neff

Rac 2 . Rac1 + Rac 2

(9)

For TMS320F2812, sixteen 12-bit ADCs are built-in. When ADCs are used to sample analog signals, the gain KADC should be concerned in the control loop, which is expressed as
K ADC = 2B vr

(10)

where B is the number of bits of ADCs and vr is the input range of ADCs. B. Digital PI controller This paper develops the continuous time equivalent model of the digital control loop in Fig. 5, which considers the controller is an analog controller. Because the control-tooutput transfer function in DCM flybacks is a first-order system. Then, a PI controller is a good choice and the backward Euler integration method can actually be implemented. We have to determine the loop gain for the block diagram of Fig. 5. The loop gain is given by the cascade connection of all blocks as follows
1 1 DTs s ~ vo KI 1 2 L( s ) = K P + (11) ~ ( s ) HK ADC . s Vtri 1 + 1 DT s d s 2 Choose a proper crossover frequency fCL and phase margin (PM) according to the desired specification. The parameters KP and KI can be obtained by solving the following equations with an assumption that KI = 2fCLKP.
~ 1 v o L( j 2f CL ) = 1 K P ~ ( j 2f CL ) HK ADC Vtri d DTs 1 180 + PM = 90 2 tan 2f CL 2 ~ KP v o ( j 2f CL ) + tan 1 ~ 2f CL K d I

(12)
.

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105

vaux
Normalized voltage regulation (%) 104

Modulating Vdelay constant Vdelay

103

is
VdelayTCLK

102

101

Sampling instant
Fig. 6. Constant sampling instant makes the sensed voltages different between two different loads.

100

99 20

30

40

50 60 Output power (W)

70

80

90

is

Fig. 8. Comparisons of voltage regulation with and without modulating the sampling instant.

toff 1

t off =

vin Vduty Ts . nvo Vtri

(14)

is
IV. EXPERIMENTAL RESULTS

toff 2

Fig. 7. The concept of modulating Vdelay with different loads.

C. Modulating the sampling instant Vdelay is a key parameter for the primary-side sensing technique. In order to sense the output voltage in interval T3, Vdelay times TCLK should be larger than T1 plus T2, where TCLK is the period of the counter. The ADC will sample the sensed voltage at VdelayTCLK after the switch turned off. There is a problem that a steady-state error occurs when using a constant Vdelay for different loads, which is shown in Fig. 6. This steady-state error is caused by the sensing error according to (5) that the current is at the sampling instant changes with different loads. To improve the voltage regulation, a method is to modulate the sampling instant with different loads. Figure 7 shows the concept of modulating the sampling instant. Let the conduction period of the rectified diode at the secondary side is toff. Set the sampling instant at t before the diode turned off, so that the current is is ideally the same. This enforces the sensed signals are almost identical with different loads. The Vdelay can be set as
Vdelay = t off t TCLK

To verify primary-side sensing (PSS) technique, a 90 W DCM flyback converter is designed for operation from the 100 V dc line. The nominal output voltage is 19 V, the switching frequency is 50 kHz, the magnetizing inductance is 120 H referred to the primary side, the flyback transformer turns ratio n is 2.9, the effective turns ratio neff is measured as 1/3, and the output capacitance is 200 F. A. Voltage regulation First, the voltage regulation results with and without modulating the sampling instant are shown in Fig. 8. The testing point is set from 20 W to 90 W. All results are normalized by 19 V. The voltage regulation with modulating the sampling instant has 1 % deviation when the load power is from 20 W to 90 W, and the voltage regulation with constant sampling instant has about 4 % deviation. As a result of modulating the sampling instant, the voltage regulation can be improved. B. Timing diagram of PSS algorithm in the DSP chip There is one interrupt service routine (ISR) program, which is called ADC_ISR, to implement PSS technique. The ADC interrupt is set to be compared interrupt flag, so ADC_ISR will be triggered when the register VADC is equal to the counter. In Fig. 9, the sensed voltage is converted to digital value by ADC first, which costs 0.49 s. Then, the digital PI controller calculates the next duty command according to the sensed value and the output voltage command, which costs 0.36 s. Finally, a modulating method in (13) is utilized to update the next sampling instant, which costs 0.54 s. The total duration of ADC_ISR is 1.39

(13)

where the interval toff can be estimated from the magnetizing current iM, so it can be derived as

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Counter

VADC
Vduty[n1]
Vdelay[n1]

420 s

Vduty[n]

Vdelay[n]
1V 700 mV

No LC filter

d
ADC_ISR
20 s 20 s

With LC filter

Output current

A/D Conversion

Digital PI controller

Modulating the sampling instant

Fig. 9. Timing diagram of PSS algorithm in the DSP chip.

Fig. 10. Load transient response from 20 % to 100 % output power with constant sampling instant.

s, which is about 7 % to the switching period.

420 s No LC filter

C. Load transient response We test the load transient from 20 % to 100 % with and without modulating the sampling instant. Figure 10 shows the result with constant sampling instant and Fig. 11 shows the result with modulating sampling instant. It is obvious that there is a steady-state error, 700 mV, in Fig. 10, which is caused by sensing error mentioned before. When the sampling instant is modulated by (13), the steady state error is reduced. Moreover, the modulation of the sampling instant does not affect the dynamic response because the waveforms in Fig. 10 and 11 are similar. For operating in DCM, the output voltage of flyback converters suffers from the ESR of the output capacitor. To improve this situation, install a small LC filter at the output. Both load transient responses are shown together in Fig. 10 and 11. PSS technique senses the voltage before the LC filter, so the dynamic response of the LC filter does not affect the controller design. The settling time in both cases is the same as 420 s. Because of the sampling frequency is 50 kHz, the output voltage enters into steady state after 21 cycles. The voltage drop is 1 V in Fig. 10, 5.3 % of nominal output while the voltage drop is 0.9 V in Fig. 11, 4.7 % of the nominal output. In order to check whether the sensed voltage for PSS is correct or not when the load changes from 20 % to 100 %, the sensed voltage in the DSP chip is transmitted to a digitalto-analog converter immediately after the A/D conversion and scaled to the same level of the output voltage. The results are shown in Fig. 12(a). Because we sense the output voltage from the auxiliary winding, the output voltage after the LC filter can not be obtained for voltage regulation. This phenomenon is obviously shown in Fig. 12(a), where the sensed voltage follows the output voltage before the LC filter. Figure 12(b) is the relation of the output voltage before the LC filter versus the sensed voltage. According to

0.9 V

With LC filter

Output current

Fig. 11. Load transient response from 20 % to 100 % output power with modulating sampling instant.

Fig. 12(b), it reveals that the sensed voltage and the output voltage before the LC filter are positive correlation. Figure 12(c) is the relation of the output voltage after the LC filter versus the sensed voltage. The dots are almost below the ideal curve because the output voltage after the LC filter drops more than the sensed voltage when a load step occurs. The voltage deviation can be also recognized in Fig. 12(c). V. CONCLUSION PSS technique gradually becomes the solution for low power applications. The sensing error caused by the winding resistance and the voltage drop of the secondary diode can be corrected by modulating the sampling instant. For controller design, the conventional model and design procedure of flyback converters are suitable for flyback converters with PSS technique. With the advance of power control IC realization technology, digital technique is able to implement more sophisticated control and protection to improve the performance of power systems. In this paper,

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20.5
vo (before LC) (V) 20 19.5 19 18.5 18 17.5 18 18.5 19 Sensed voltage (V)

20 19.5 19 18.5 18 17.5 17 0

Voltage ripple
19.5

Voltage ripple

(V)

Ideal curve
19.5 vo (after LC) (V)

(b)

deviation
vo (before LC) vo (after LC) Sensed Voltage 0.2 0.4 0.6 time (sec) 0.8 x 10 1
-3

19 18.5 18

deviation
17.5 17.5 18 18.5 Sensed voltage (V) 19 19.5

(a)

(c)

Fig. 12. (a) Experimental results of the output voltage and the sensed voltage by PSS. (b) The relation of the output voltage before the LC filter versus the sensed voltage. (c) The relation of the output voltage after the LC filter versus the sensed voltage.

we verify that the PSS technique is applicable to flyback converters. The performance of voltage regulation is excellent with only 1 % deviation. PSS technique only controls the output voltage before the LC filter, which means that the output voltage after the LC filter is uncontrolled. Therefore, the LC filter must be designed properly to avoid unstable conditions or a large voltage drop when a load step change occurs. REFERENCES
[1] Hua L. and Luo S., Design comparisons between primary-side control and secondary-side control using peak current mode controlled active clamp forward topology, in Proc. IEEE APEC Conf., Feb. 2006, pp. 886-892. J. Xiao, J. Wu, W. Li, and X. He, Primary-side controlled flyback converter with current compensation in micro-power application, in Proc. IEEE IPEMC Conf., May 2009, pp. 1361-1366. A. Ball and K. Valdez, Circuit and method for a switching power supply with primary side transformer sensing, US Patent 6,333,624, Dec. 25, 2001. R. Nalepa, N. Barry, and P. Meaney, Primary side control circuit of a flyback converter, IEEE APEC Conf. Proc., pp. 542-547, 2001.

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