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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

S-R FLIP FLOP VHDL CODE USING BEHAVIOURAL MODELING

Library ieee declaration.

library IEEE;

In ieee library std_logic_1164 package is declared


for std_logic data types (predefined data types).
use IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------entity s_rff is

Entity describes circuit external ports.


Port (s, r, clk, rst: in STD_LOGIC;

S, r, clk, rst: - input port to S-R flip flop.

q, qbar: - output port to S-R flip flop.


q, qbar : inout STD_LOGIC);

q:- present state, qbar: - next state.


end s_rff;
-------------------------------------------------------------architecture Behavioral_srff of s_rff is
-------------------------------------------------------------
signal temp: std_logic:='0';

-------------------------------------------------------------begin
Architecture begins.
-------------------------------------------------------------process(clk, rst, s,r)
begin
if (clk'event and clk='1') then

if (rst='0') then
if (s='0' and r='0') then

temp<= q;
elsif (s='0' and r='1') then

temp<='0';
elsif (s='1' and r='0') then
temp<= '1';
elsif (s='1' and r='1') then
temp<= 'Z';
else
temp<= q;
end if;
end if;
end if;
end process;
------------------------------------------------------------INFOOP2R.WIX.COM/OP2R

Declarative part of architecture.


Signal temp is declared as std_logic
data types, which holds initially 0.

In a process all the statements will be


executed sequentially.
If clock rising edge is +ve and reset is 0
then flip flop will work otherwise its
output will be previous state.
Truth table of S-R flip flops.
S
0

R
0

0
1
1

1
0
1

Q
Previous
state
1
0
Invalid

QBAR
Previous
sate
0
1
invalid

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

Concurrent statements.
q<= temp;

Declared out of process. These statements will


be executed without any sequences.
qbar<= not q;
------------------------------------------------------------End of architecture.
end Behavioral_srff;

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