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library IEEE;
-------------------------------------------------------------begin
Architecture begins.
-------------------------------------------------------------process(clk, rst, s,r)
begin
if (clk'event and clk='1') then
if (rst='0') then
if (s='0' and r='0') then
temp<= q;
elsif (s='0' and r='1') then
temp<='0';
elsif (s='1' and r='0') then
temp<= '1';
elsif (s='1' and r='1') then
temp<= 'Z';
else
temp<= q;
end if;
end if;
end if;
end process;
------------------------------------------------------------INFOOP2R.WIX.COM/OP2R
R
0
0
1
1
1
0
1
Q
Previous
state
1
0
Invalid
QBAR
Previous
sate
0
1
invalid
Concurrent statements.
q<= temp;
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