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D FLIP FLOP VHDL CODE USING STRUCTURAL MODELING

Library ieee declaration. In ieee library std_logic_1164 package is declared for std_logic data types (predefined data types).

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -----------------------------------------------entity dff_str is Port ( d,clk: in STD_LOGIC; q,qn : inout STD_LOGIC); end dff_str; ------------------------------------------------architecture Behavioral_str of dff_str is -------------------------------------------------signal s1,s2: std_logic; component nand_1 is Port ( i,j : in STD_LOGIC; k : out STD_LOGIC); end component; component and_1 is Port ( a,b : in STD_LOGIC; c: out STD_LOGIC); end component; -------------------------------------------------Architecture begins. Begin -------------------------------------------------z1: nand_1 port map (d, clk, s1); z2: nand_1 port map (not d, clk, s2); z3: nand_1 port map (s1, qn, q); z5: nand_1 port map (s2, q, qn); -------------------------------------------------end Behavioral_str;

Entity describes circuit external ports. d, clk, rst: - input port to D flip flop. q, qn: - output port to D flip flop. q:- present state, qn: - next state.

Declarative part of full adders Architecture. Signal declaration. Signal s1, s2 will act as inout port. Component (nand_1, and_1) declaration. Components represent the structure of full adder circuit.

Statements part of the architecture. Components are port mapped to perform full subtraction operation. g1 signal is assigned to signal s3 after 1ns. This delay is provided to calculate s3 value first, then after 1ns it will assigned to g1.

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