Assignment No.

4
1. A sequential circuit has four flip-flops A, B, C, D and an input x. It is described by the
following state equations:
A(t + 1) = (CD + CD)x + (CD + CD)x
B(t + 1) = A
C(t + 1) = B
D(t + 1) = C
(a) Obtain the sequence of states when x = 1, starting from state ABCD = 0001.
(b) Obtain the sequence of states when x = 0, starting from state ABCD = 0000.
2. A sequential circuit has two flip-flops (A and B), two inputs (x and y), and an output (z).
The flip-flop input functions and the circuit output function are as follows:
JA = xB + yB
KA = xyB
JB = xA
KB = xy + A
z = xyA + xyB
Obtain the logic diagram, state table, state diagram and state equations.
3. Design a BCD counter with JK flip-flops.
4. Design the binary counters having the following repeated binary sequence. Use JK flipflops.
(a) 0, 1, 2
(b) 0, 1, 2, 3, 4
(c) 0, 1, 2, 3, 4, 5, 6
5. Design a counter with the following binary sequence: 0, 1, 3, 2, 6, 4, 5, 7 and repeat. Use
RS flip-flops.
6. Design a counter with the following binary sequence: 0, 1, 3, 7, 6, 4 and repeat. Use T
flip-flops.
7. Design a counter with the following binary sequence: 0, 4, 2, 1, 6 and repeat. Use JK flipflops.
8. Design the sequential circuit described by the following state equations. Use JK flip-flops.
A(t + 1) = xAB + yAC + xy
B(t + 1) = xAc + yBC
C(t + 1) = xB + yAB
9. Reduce the number of states in the state table of Table 1. and tabulate the reduced state
table.

Table 1

10. (i)Starting from state a of the state table of Table 1 find the output sequence generated
for an input sequence 01110010011.
(ii)
Show that the same output sequence is obtained for the reduced state table.
11.The state diagram of a Sequential circuit is shown in Fig. 1. Design the sequential circuit
with (a) T flip-flops (b) RS flip-flops and (c) JK flip-flops.
12.Design a sequential circuit using D flip-flops to satisfy the following state equations:
Fig. 1.
A(t+1) = ABCD + ABC + ACD + ACD
B(t+1) = AC + CD + ABC
C(t+1) = B
D(t+1) = D
13. Obtain the logic diagram of a master-slave JK flipflop with AND and NOR gates. Include a provision
for setting and clearing the flip-flop asynchronously.
14. Obtain the logic diagram of a master-slave JK flipflop with NAND gates. Include a provision for setting
and clearing the flip-flop asynchronously.
15.Obtain the state table and state diagram of the logic
circuit shown in Fig. 2.

Fig. 2.
16. Derive the state table and state diagram of the sequential circuit of Fig. 3. What is the
function of this circuit ?

Fig. 3.
17. Derive the state equations for the sequential circuit specified by Table 2. List and use
dont care conditions for the same. Derive the flip-flop input functions from state
equations using (i) JK flip-flops and (ii) D flip-flops.
Table 2