Digital Integrated circuits 

are produced using

several different circuit configurations and
production technologies. Each such approach
is called a specific logic family. A logic family is
a collection of different integrated circuit chips
 that have similar input, output, and internal
circuit characteristics, but they perform
different logic gate functions such
as AND, OR, NOT, etc.
Pass transistor strong and degraded outputs
 CMOS STEADY-STATE ELECTRICAL BEHAVIOR
•The complete input-output transfer characteristic of a CMOS Inverter is shown in fig.,
where the input voltage is varied from 0 to 5 V, as shown on the X axis; the Y axis plots the
output voltage.
•If we define a CMOS LOW input level as any voltage under 2.4 V, and a HIGH input level
as anything over 2.6 V, then only when the input is between 2.4 and 2.6 V does the
inverter produce a non logic output voltage under this definition.
Comparison of Static CMOS and Dynamic CMOS
Dynamic CMOS Inverter
Dynamic CMOS
Dynamic CMOS Implementation
 Cascading in Dynamic CMOS Logic

Drawback of cascading in high impedance state-Output is undefined so a

possibility of false operation
Layout Design
Stick Diagram of NOR Gate
Stick Diagram of NAND Gate
Stick Diagram of inverse of (A+B).C
 Stick Diagrams
 Stick diagrams represents layer information using simple
diagrams.
 layer information is conveyed through color codes (or
monochrome encoding).
 Acts as an interface between symbolic circuit and the actual
layout
Stick Diagrams Notations

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick Diagrams Rules
 Rule 1: When two or more ‘sticks’ of the same type cross or touch each other that represents
electrical contact.

 Rule 2: When two or more sticks of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection explicitly)

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick Diagrams Rules
 Rule 3: When a poly crosses diffusion it represents a transistor
Note: If a contact is shown then it is not a transistor

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick Diagrams Rules
 Rule 4: In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All
PMOS must lie on one side of the line and all NMOS will have to be on the other side.

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
Example of Stick Diagrams: CMOS
inverter

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
Stick diagram for NAND gate using CMOS logic
Stick diagram for NAND gate using CMOS logic
VDD

GND
Stick diagram for NAND gate using CMOS logic
VDD

G
D S D S

D S D S

G
G
GND
 Stick diagram for NAND gate using CMOS logic
VDD
G G
D S D S

N-Well

PMOS Logic
D S D S

NMOS G
Logic
GND
 Stick diagram for NAND gate using CMOS logic
VDD
G G
D S D S

B
A
N-Well
PMOS Logic Vout

S D S
D

NMOS G
Logic
GND
Stick diagram for NOR gate using CMOS logic
VDD

GND
 Stick diagram for NOR gate using CMOS logic
VDD

G
S S D
D

S D D S

G
G
GND
 Stick diagram for NOR gate using CMOS logic
VDD
G G
S D S D

B
A
N-Well
Vout
PMOS Logic

S D
D S

NMOS G
Logic
GND
Example of Stick Diagrams: NOR gate

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick diagrams limitations
Does not show

Exact placement of components

Transistor sizes – Wire lengths, wire widths, tub boundaries –
Any other low level details such as parasitics

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Layout
 Representation of an integrated circuit in terms of
planar geometric shapes
Correspond to the patterns of metal, oxide, or
semiconductor layers that make up the components
of the integrated circuit.
 Layout design rules
 Layout design rules describe how small features can be and how closely they can
be reliably packed in a particular manufacturing process
 Industrial design rules are usually specified in microns.
 Migrating from one process to a more advanced process or a different foundry’s
process is difficult in microns rule.
 Layout design rules
Mead and Conway [Mead80] popularized scalable design rules based on a single parameter, λ.

λ is generally half of the minimum drawn transistor channel length

Channel length is the distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire

For example, a 180 nm process has a minimum polysilicon width (and hence transistor length)
of 0.18 µm and uses design rules with λ = 0.09µm
 Layout design rules
Metal and diffusion have minimum width and spacing of 4 λ.

Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
Distance between two contacts-- 3 λ

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
 Layout design rules
 Polysilicon uses a width of 2 λ

 N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Layout of CMOS inverter

CMOS inverter

Layout

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Layout of Three input NAND gate

Three input NAND gate Layout

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Layout Design of an Inverter
 Layout Design of an Inverter

2λ

Polysilicon
layer
 Layout of NMOS Transistor

Diffusion
area
(Source/
Drain)
 Lambda rule for NMOS
2λ

Metal contact or 1.5λ

Active area contact 2λ 2λ 1.5λ
2λ 2λ
Or diffusion area
contact 1.5λ 1.5λ

Poly contact or 2λ
Gate contact
 Layout of PMOS Transistor
10λ

2λ N-
Well

1.5λ
Metal contact or 2λ 2λ 1.5λ
2λ 2λ
Active area contact
Or diffusion area 1.5λ 1.5λ
contact

Poly contact 2λ
or
Gate contact
 10λ

3λ N-Well
Metal Layer
Layer

2λ 2λ

2λ

Metal contact in PMOS Transistor

Step 1- Create Vdd and Gnd layer
VDD 3λ

Gnd 3λ
Step 2- Place the transistor
VDD
2λ
2λ
3λ Active area

Poly silicon
Layer

3λ Active area
2λ
2λ
Gnd
Step 3- Create contacts
VDD

2λ
2λ
Active metal
contact

Poly metal
contact

Gnd
Step 4- complete the wire connection
VDD

Source Drain

Gate

Source Drain

Gnd
 VDD

Vin Vout
6λ

Gnd
Layout for NAND Gate
Step 1- Create Vdd and Gnd layer
VDD 3λ

Gnd 3λ
Layout for NAND Gate
VDD 3λ

Gnd 3λ
Layout for NAND Gate
VDD 3λ

3λ

3λ

2λ 2λ
Gnd 3λ
Layout for NAND Gate
VDD 3λ

D S S D
3λ

Vout
A B

3λ

S D S D
2λ 2λ
Gnd 3λ