Fundamentals of CMOS VLSI 3-35 Circuit Design Processes

3.6 Translation of Symbolic Diagrams to Mask Form

Mask layouts can also be directly derived from symbolic diagram by the i
from one to the other. Consider the symboiic form of
translation standards a
1-bit CMOS shift register cell given earlier in Fig. 3.5 (e). It is reproduced here
(Fig. 3.17 (a) for convenience of comparison with the corresponding mask
layout given in Fig. 317 (b). The figures are also self-explanatory for
understanding the translation process.

3.7 Stick Diagrams for nMOS

Monochrome Encoding for nMOS Stick Diagram

STICK ENCODING LAYERS

n-diffusion or thinox region

Polysilicon1

Metal

Implant
-

Contact

n-channel erhancement MOSFET

n-channel depletion MOSFET

Fundamentals of CMOS VLSI 3-36 Circuit Design Processes

3.7.1 Two Inputs nMOS NAND Gate

Statement: Design stick diagram for two inputs nMOS NAND gate.

nMOS NAND Gate

Circuit diagram:
VoD

Y AB

Ao

GND

Fig. 3.18 Two inputs nMOS NAND gate

Monochrome encoding is used for stick diagram.
Step 1: Draw VpD and GND rails in parallel as shown in Fig. 3.19.

VDD

GND

Fig. 3.19 VpD and GND rails

Step 2: Draw n-diffusion stick with appropriate contacts as shown in Fig. 3.20.

VDD

GND

Fig. 3.20 n-diffusion path

 Fundamentals of CMOS VLSI 3- 37 Circuit Design Processes

and
Step 3 Polysilicon crosses n diffusion paths, where transistors are required
implant is drawn for depletion mode transistor.
Implant

VDD

Polysilicon
Y= AB

A THIRA

GND

Fig. 3.21 Stick diagram for two inputs NAND gate

3.7.2 Two Inputs nMOS NOR Gate

Statement Design stick diagram for two inputs nMOS NOR gate.

nMOS NOR gate

Circuit diagram
VpD

Y = A+B

A-

Fig. 3.22 Two inputs nMOS NOR gate

Step 1 Draw VpD and GND rails in parallel as shown in Fig. 3.23.
VpD

GND

Fig. 3.23 VpD and GND ralls

Fundamentals of CMoS VLSI 3-38 Circuit Design Processes

Step 2: Draw n-diffusion sticks with necessary contacts.

VpO

GND
Fig. 3.24 n-diffusion paths and contacis
Step 3: Now
polysilicon crosses n-diffusion paths wherever transistors
and are required
implants are drawn for depletion mode transistor.
VDD

SLKS EE2Y= (A+B)

A RRNR BMRSNEPERE

GND

Fig. 3.25 Stick diagram of two inputs nMOS NOR gate

3.7.3 nMOS EX-OR Gate

Statement: Designa stick diagram for nMOS EX-OR gate.

Circuit diagram
EX-OR logic:Y = A B + AB

Y = A B

VDD

Y= AB +AB
A

Fig. 3.26 nMOS EX-OR logic

Fundamentals of CMOS Circuit Design Processes
VLS 3- 39

Stick diagram
Step 1 Draw VpD and GND rails as shown in Fig. 3.27.

VoD

GND

Fig. 3.27 VpD and GND rails

Step 2 Draw n-diffusion and other thinox region.

VpD

GND

Fig. 3.28 n-diffusion thinox paths and rails

shown in Fig. 3.29.
Step 3: Polysilicon and implants are

VpD
L

R
Y = AB +AB

A KANEA BRETER RCTEENE

A KERE B RENNI

GND

Fig.3.29 Stick diagram of nMOS EX-OR logic gate

Fundamentals of CMOS VLSI 3-40 Circuit Design Processes

Example 3.1: Design a stick diagram for nMOS logic showm as Y = A + B+C.

Solution: Y =A+ B+C represents a three inputs NOR gate

Circuit diagram
VpD

Y=A+B+C

GND
Fig. 3.30 Three inputs nMOS NOR
gate
Stick diagram
Step 1 Draw VpD and GND rails as
shown in Fig. 3.31
VDD
VoD

GND
Fig. 3.31 VpD and GND rails
Step 2 Draw n-diffusion and other thinox
regions with appropriate contacts.
VDD

GND
Fig. 3.32 n-diffusion and rails
Fundamentals of CMOS VLSI 3-41 Circuit Design Processes
Step 3
Polysilicon and implants shown
are
in Fig. 3.33.

VpD

RRRNRERERAE Y= (A+ B+C)

A BLR CRakR

K GND

Fig. 3.33 Stick diagram of three inputs nMOs NOR gate

Example 3.2 Design stick diagram for nMOS logic Y = (A+ B)C.

Solution : Circuit diagram:

VpD

E)
Y =(A+B) C

c
GND

Fig. 3.34 Circuit diagram for Y =(A + B) C

Fundamentals of CMOS VLSI 3-42 Circuit Design Processa

Stick diagram
Sep 1: Draw VpD and GND rails as shown in Fig. 3.35.

VoD

GND
Fig. 3.35 Vpo and GND rails
Step 2 Draw n-diffusion and other thinox region.

VoD

GND

Fig. 3.36 n-diffusion and rails

Step 3: Polysilicon and implants are shown in Fig. 3.37.

VpD

SASTAAS Y=(A+B) C

A BRhBSY

GND

Fig. 3.37 Stick diagram

 MOS and BICMOS circuit design 69
processes
() Shift register cell (i) Logic function X= A+ BC

Voo VpD

GND
GND
(a) Rails and thinox paths

VpD VoD
s 4:1
(n 8:1

snt

1:2

N 1:1( 1:2
Poly GND
1:1

GND

(b) Pull-up and pull-down structures (polysilicon), implants, and ratios

- VoD VoD
Bounding
box
8:1

1:1
VP 13
1:1
1:11 1:2
Bus
GND
(
---. A
GND
C
(c) Buses, control signals, interconnections, and 'leaf-cel"'boundaries

Figure 3-3 Examples of nMOS stick layout design style

 Subsystem design and
lay
CMOS (complementay) BICMOS
nMOS

VDD VoD VoD VDD

L1:W1
HE PE
Vout Vout
Vin Vout Vin Vout Vin
L2:W2

GND
GND Vss Vss VsS
(a) Circuit symbols (Wote: n-and p-transistors assumed to be min. size unless stated otherwise.)

Ratio may be indicated here if

4:1 appropriate but otherwise
or (8:1) assumed to be 1:1

nMOS CMOS BICMOS

(b) Logic symbols

VpD VDD
VpD
L1:W1
Vout
Vout
- Vout
www w Vin
Vin Vin
L2:W2

GND Vss Simple BiCMOS

VsS
nMOS CMOS (complementary)
Overall ratio = 1 / 1
L2/W2

(c) Stick and symbolic diagrams

inverters
Figure 6-3 nMOS, CMOS and BiCMOS

to consider the very simple circuit

Nand gate with n inputs, it is only necessary
when all n pull-down transistors are conducting
model of the gate in the condition
as in Figure 6-7.
must be near enough to
The critical factor here is that the output voltage Vout
that is
ground to turn off any following inverter-like stages,

VoutV,=0.2Vpp
 and layout 153
Subsystem design

CMOS (complementary) BICMOS

nMOS (ratio 4:1)
Vpo
VoD VoD
4:1
X x
Vout Vout A Voul
1:2

GND GND Vss

unless stated otherwise.
(a) Circuit diagrams Note: n- and p- transistors assumed to be minimum size

4:1

VoD
(b) Logic symbols

VoD VDD
4:1 Demarcation
line Vout
Vout
Vout X Demarcation
line
006888808NR

1:2 A
B 1:2 B

ss
GND Vss Symbolic form (BiCMOs)
(c) Stick diagrams (nMOS and CMOS)
to 1.25:1 (or better) owing to the two
Note: The natural 2.5:1 asymmetry of the CMOS inverter is improved
transistors in series for the two VP Nand.
n-type pull-down
Demarcation line (edge of n-well) may be shown if required.

Figures 6-6(a)-(c) nMOS, CMOS and BiCMOS 2-input Nand gates

Thus
VDD XnLp.d.
nzp.d. t2p.u. 0.2VpD
where Z,d applies for any one pull-down transistor. The boundary condition then
is

nzp.d.
nZp.d. t Zp.u
= 0.2

whence nMOS Nand ratio =

np.d.4
p.d.
 Subsystem design and layout 157
nMOS CMOS (complementary) BICMOS

VDD Vpo
4:1

Vout

Vout B
Vout

B
GND -Vss
(a) Circuit diagrams

4:1 or 8:1 Vss

Note: For CMOS and BICMOS all transistors
4:1 or 8:1 are assumod to be of minimum size.

(b) Logic symbol

nMOS CMOS
BICMOS VoP VDD
Vout

Demarcation line B

Vout

Vss
(c) Stick diagrams (nMOS and CMOS) and symbolic form (BiCMOS) Demarcation line

"Demarcation line (edge of n-wel) may be shown if fequired.

Figures 6-8(a)-(c) nMOS, CMOS and BiCMOS two-input Nor gate

devices is aggravated in its effect by the number connected in series.

Rise-time
and fall-time asymmetry on capacitive loads is thus increased and
there will also
be a shift in the transfer (Vin vs Vou) Characteristic which will reduce noise immunity.
For these reasons, CMOS (complementary logic) Nor gates with more
than two
of the p-and/or n- transistor geometries (L: Wratios).
inputs may require adjustment
The CMOS Nand gate, on the other hand, benefits from the connection of p-
transistors in parallel, but once again the geometries may require thought when
several inputs are required.