EE 577A Spring 2022 – VLSI System Design

Homework 1
Assigned: 13th Jan for T, Th Section, and 14th Jan for Fri-Fri Section
Due: Jan 27th 11:59PM Pacific Time. Submissions to be done online using DEN for T, Th Section and
through Blackboard for Fri-Fri Section.
Score: 50 Points. No late submissions.

1) (12 Points) Short answer questions.

a) (2 Points) What does ‘Static’ and ‘Dynamic’ refer to in Static and Dynamic CMOS logic,
respectively? Why is static logic more robust against noise compared to dynamic logic?
b) (2 Points) In context of MOSFETs briefly explain why channel strain engineering is used in
advanced MOSFET devices?
c) (2 Points) What is electromigration?
d) (2 Points) Mention one advantage and one disadvantage of using subthreshold CMOS circuits?
e) (2 Points) What does FF, SS, SF, FS, TT process corners represent? Explain.
f) (2 Points) What do ‘static’, ‘dynamic’ and ‘leakage’ power refer to?

2) (6 Points) Mark the Source and Drain terminals and identify the region of operation for each of
the transistor configurations shown below ( For both PMOS and NMOS |VT| = 400mV).

3) (10 Points) The log VGS-ID characteristics is a key graph that helps to understand the behavior
of a given transistor technology. The following questions help to highlight key insights that could
be understood using the VGS-Id characteristics. Referring to Fig. 2, answer the following questions
a) (2 Points) Fig.2 shows the VGS-Id characteristics, using log scale for y-axis. Draw the
corresponding VGS-Id characteristic using linear x- and y-axis.
b) (2 Points) Mark the region on the x-axis that corresponds to the VT of the two transistors on the
linear VGS-Id characteristics?
 c) (2 Points) Assuming both Transistor-1 and Transistor-2 have same device dimensions, and VDD,
which transistor technology, Transistor-1 versus Transistor-2 would you choose to create circuits
with low-leakage power dissipation. Why?
d) (2 Points) Assuming both Transistor-1 and Transistor-2 have same device dimensions, and VDD,
which transistor technology, Transistor-1 versus Transistor-2 would you choose to create high-speed
circuits. Why?
e) (2 Points) Shade the corresponding regions in Fig. 2 that would correspond to sub-threshold
region of operation for Transistor-1 and Transistor-2.

Fig. 2: VGS versus log(Id) characteristics.

4) (5 Points) This question is designed to help you understand how different voltages ‘pass’
through various nodes in a CMOS circuit. Calculate the steady state voltages at nodes A, B, C, D and
E. At time ‘t’, the voltage at the gate of transistor M1 goes from 0V to VDD. Nodes A, B, D and E are at
0V before time ‘t’, while node C is at VDD before time ‘t’. Assume VT = |500mV| for both PMOS and
NMOS transistors, the inverter (marked as 1) trip point is at 0.7V and the VDD is 1.5V. NMOS M4
has a forward body bias (FBB) that reduces its VT by 300mV. Also assume transistor currents to be
zero in cut-off region of operation. Show your work. Ignore Body effect on all other transistors
except for M4.
5) (12 Points) For the circuit shown below, assume node Out was initially at 0V and is being
charged by the PMOS shown in the figure. (Assume the width of transistor is W and threshold
voltage is VT, also all the parasitic capacitances associated with the transistor are negligible.)

a) (3 Points) Derive the expression for the total energy supplied by the voltage source VDD
during the charging process.
b) (2 Points) How would the total energy consumed from the voltage source VDD change if the
transistor VT is increased by 25%?
c) (2 Points) How would the total energy consumed from the voltage source VDD change if the
overdrive voltage i.e. (VSG-|VT|) is increased by 25% by pulling the gate terminal to a negative
voltage?
d) (2 Points) How would the total energy consumption from the voltage source VDD change if the
value of VDD is increased by 25%?
e) (3 Points) Derive the expression for the total energy consumed from the voltage source VDD if
the PMOS is replaced by NMOS (and the gate of NMOS is connected to VDD). Assume zero
current through the NMOS in cut-off region.
6) ( 5 Points) Referring to the Pull Up Network shown below:

a) (2 Points) Draw the dual Pull Down Network (PDN) for the circuit shown below.
b) (2 Points) Size the NMOS and PMOS transistors assuming the mobility of holes is equal to the
mobility of electrons.
c) (1 Points) Assuming that the PUN is optimized for speed, which among the signals A, B, C, D, E,
G, should be the latest signal to arrive? Justify your answer.