Digital Integrated Circuit Design

Subject Code:18EC2019

Dr. G.Manoj
CONTENT

• Introduction
• Schematic Fundamentals
• Inverter
• Schematic Fundamentals LOGIC GATES
• Schematic Fundamentals COMPLEX CIRCUITS
• Schematic Fundamentals TRANMISSION GATES
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FUNDAMENTALS
Logic circuits are built with transistors.

Transistors is the smallest building block or device.

Transistor operates as a simple switch.

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SCHEMATIC FUNDAMENTALS
The most popular type of transistor for implementing a simple switch is the
Complementary Metal Oxide Semiconductor (CMOS).

In CMOS there are two types of transistors, PMOS and NMOS and together
they complement each other.

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SCHEMATIC FUNDAMENTALS
DEVICES
NMOS PMOS
Gate Gate

x = “high”/ “1”
x = “low”/
Source Drain Drain VDD “0”Source
Substrate (Body)
GND x = “low”/
Substrate (Body) x = “high”/ “1”
(a) NMOS Transistor “0” (a) PMOS Transistor

VG VG

VS VD VD VS

(b) Simplified Symbol for an (b) Simplified Symbol for an PMOS

NMOS Transistor Transistor

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SCHEMATIC FUNDAMENTALS
DEVICES
NMOS PMOS
VD = 0 V
VD VD VS = VDD VDD

VG = VDD VG = vDD

VS = 0V VD
V
VDD= VDD
Closed switch when VG = VDD Open switch when VG = VDD
Closed switch when VG = 0V
Open switch when VG = 0
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SCHEMATIC FUNDAMENTALS
A simpler way to visualise the operation of the transistors is a resistor when it
is ON.

The amount of current that flows through the transistor is limited by the
equivalent resistance of the transistor.

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SCHEMATIC FUNDAMENTALS
The first schemes for building logic gates with MOSFETs became popular in
the 1970s and relied on either PMOS or NMOS transistors, but not both.

Since the early 1980s, a combination of both NMOS and PMOS transistors
has been used.

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SCHEMATIC FUNDAMENTALS
The part of the circuit that involves VDD
NMOS transistors is known as pull-
Pull-up network
down network (PDN). (PUN)

The concept of CMOS circuits is

Vf
based on replacing the pull-up device
with a pull-up network (PUN) that is Vx1 Pull-down network
Vx2 (PUN)
built using PMOS transistors.

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SCHEMATIC FUNDAMENTALS
The functions realised by the PDN and PUN networks are complements of each
other. Then a logic circuit can be implemented .
For any given valuation of the input signals, either PDN pull Vf down to Gnd or the
PUN pulls Vf up to VDD.

The PDN and the PUN have equal number of transistors, which are arranged so
that the two networks are duals of one another.
Wherever the PDN has NMOS transistors in series, the PUN has PMOS transistors in
parallel, and vice versa.

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SCHEMATIC FUNDAMENTALS Inverter

The inverter is the simplest logic gate.

Its function is to invert the signal received on the input node to the opposite
polarity to the output node.

CMOS logic by its very own nature is always inverting.

The NMOS and PMOS are never “ON” at the same time.

This is why CMOS is a low-power style of circuit design.

Once the gate switches state, there is no DC current path between VDD and GND

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SCHEMATIC FUNDAMENTALS INVERTER

INVERTER
VDD
VDD x f P1 N1

P1
0 1 on off
P1 = off
on 1 0 off on
x f
x = 10 f = 01
N1
N1 = off
on
N1
P1 0 1
0 1 -
x f 1 - 0
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SCHEMATIC FUNDAMENTALS
NMOS CIRCUITS
VDD
If Vx1 = Vx2 = 5 V, both transistors will
be ON.
Vf

x1 x2 f Vf will be close to 0V.

Vx1
0 0 1
0 1 1
If either Vx1 or Vx2 is 0, then no current
Vx2
1 0 1
will flow through the series-connected
1 1 0
transistors.
x1
x2
f Vf will be pulled up to 5V.

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SCHEMATIC FUNDAMENTALS
NAND Gate VDD VDD
VDD
x1 x2 f P1 N1 P2 N2
x1 x2
0 0 1 on off on off
P1 P2
0 1 1 on off off on
f
1 0 1 off on on off
x1 N1

x1 1 1 0 off on off on
x2 N2

x2
x2 x1 0 1
0 1 1
x1 1 1 0
x2 f

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SCHEMATIC FUNDAMENTALS LOGIC GATES

VDD
AND Gate

P1 P2 P3

?
x1 N2 N1

x2 N3

Draw, 2 – input AND gate Schematic Diagram.

x1
x2 f

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SCHEMATIC FUNDAMENTALS
NMOS CIRCUITS
VDD
If either Vx1 or Vx2 is 5 V, then
x1 x2 f
Vf will be close to 0V.
Vf 0 0 1
0 1 0 If both Vx1 = Vx2 = 0 V, then
Vx1 Vx2 1 0 0
1 1 0 Vf will be pulled up to 5 V.

x1
f
x2

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SCHEMATIC FUNDAMENTALS
NOR Gate VDD
VDD x1 x2 f P1 N1 P2 N2

x1 0 0 1 on off on off
x1 P1
0 1 0 on off off on
1 0 0 off on on off
x2 P2
x2 1 1 0 off on off on
f
N2 N1

x2
x1 0 1
0 1 0
x1 x1 x2
f
x2 1 0 0

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SCHEMATIC FUNDAMENTALS
V DD
OR Gate

x1 P1

?
x2 P2 P3

f
N2 N1 N3

Draw, 2 – input OR gate Schematic Diagram.

x1
x2 f

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SCHEMATIC FUNDAMENTALS
XOR Gate VDD

X1' P1 P2 X1

?
X2 P3 P4 X2'

X1 ' N1 N2 X1

Draw, 2 – input XOR gate Schematic Diagram.

X2 ' N3 N4 X2

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SCHEMATIC FUNDAMENTALS
Complex Circuits
CD
A B C D F AB 00 01 11 10 VDD
F = ((A+B+C)D)’ 0
0
0
0
0
0
0
1
1
1
00
01
1
1
1
0
0
0
1
1 A
0 0 1 0 1 11 1 0 0 1
0 0 1 1 0 10 1 0 0 1
0 1 0 0 1 B D
0 1 0 1 0 F = D’+A’B’C’
0 1 1 0 1 F’ = BD + AD + CD
0 1 1 1 0 C
= D(A+B+C)
1 0 0 0 1
F
1 0 0 1 0
1 0 1 0 1
D
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
A B C
1 1 1 1 0

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SCHEMATIC FUNDAMENTALS
Complex Circuits
CD
A B C D F AB 00 01 11 10 VDD
F = A’+(B’+C’)D’ 0
0
0
0
0
0
0
1
1
1
00
01
1
1
1
1
1
1
1
1 B C
0 0 1 0 1 11 1 0 0 0
A
0 0 1 1 1 10 1 0 0 1
0 1 0 0 1 D
0 1 0 1 1 F = A’+C’D’+B’D’
F
0 1 1 0 1
0 1 1 1 1 F’ = AD+ABC
A
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
D
1 0 1 1 0 B
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0 C
1 1 1 1 0

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SCHEMATIC FUNDAMENTALS
Transmission Gates
This configuration allows for

noninverting propagation of the input signal,

blocking of the input signal when both control signals disabled the
PMOS and NMOS transistors.

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SCHEMATIC FUNDAMENTALS
Transmission Gates
in A B out
PMOS transistors are 0 0 0 0*
0 0 1 0
connected to generate logical 0 1 0 X

“1” levels and NMOS logical 0 1 1 0

1 0 0 1
“0” and almost never reverse 1 0 1 1
1 1 0 X
the reverse. 1 1 1 1*

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SCHEMATIC FUNDAMENTALS
Transmission Gates
in A B out
*PMOS transistors are able to 0 0 0 0*
0 0 1 0
pass “0” levels, but degrade the 0 1 0 X

“0” level (weak 0). 0 1 1 0

1 0 0 1

NMOS transistors are able to 1 0 1 1

1 1 0 X
pass “1” levels, but degrade “1 1 1 1 1*

level” (weak 1).

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SCHEMATIC FUNDAMENTALS
Transmission Gates
in A B out
Usually both controls are 0 0 0 0*
0 0 1 0
implemented such that the 0 1 0 X

transmission gate is either 0 1 1 0

1 0 0 1
completely “ON” or “OFF” 1 0 1 1
1 1 0 X
(both transistors) but not 1 1 1 1*

halfway.

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SCHEMATIC FUNDAMENTALS
XOR Gate_v2 B
VDD VDD

A BB’

A’
? OUT OUT

Draw, 2 – input XOR gate Schematic Diagram Using Transmission Gate.

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SCHEMATIC FUNDAMENTALS
XNOR Gate B

B’

A’
? OUT

Draw, 2 – input XNOR gate Schematic Diagram Using Transmission Gate.

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SCHEMATIC FUNDAMENTALS
2-to-1 MUX
S

D0 Draw, 2-to-1 MUX Schematic

?
D0
Y S Y
Diagram0Using Transmission
D0
D1
S’ Y Gate. 1 D1
S
D1

S
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THANK YOU!
FOR PATIENT LSITENING

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