Digital Integrated Circuits: A Design Perspective

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Designing Combinational
Logic Circuits
November 2002.
1
© Digital
EE141 Integrated Circuits2nd Combinational Circuits
Combinational vs. Sequential Logic
In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit
State
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
2
© Digital
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
3
© Digital
Static Complementary CMOS
VDD
In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN
PUN and PDN are dual logic networks
4
© Digital
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1

5
© Digital
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0

6
© Digital
Threshold Drops
VDD VDD
PUN
S D
VDD
D 0  VDD S 0  VDD - VTn

VGS
CL CL
PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD
S D
7
© Digital
Complementary CMOS Logic Style
8
© Digital
Example Gate: NAND
9
© Digital
Example Gate: NOR
10
© Digital
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B C
11
© Digital
Constructing a Complex Gate
VDD VDD
C
SN1 F SN4 A
F
SN2 B
A A
D D SN3
B C B C D
(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C
(c) complete gate
12
© Digital
Cell Design
 Standard Cells
 General purpose logic
 Can be synthesized
 Same height, varying width
 Datapath Cells
 For regular, structured designs (arithmetic)
 Includes some wiring in the cell
 Fixed height and width
13
© Digital
Standard Cell Layout Methodology –
1980s
Routing
channel
VDD
signals
GND
14
© Digital
Standard Cell Layout Methodology –
1990s
Mirrored Cell
No Routing VDD
channels
VDD
M2
M3
GND
Mirrored Cell GND
15
© Digital
Standard Cells
N Well
VDD Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
Cell height is “12 pitch”
Out
In
2
Rails ~10
GND
Cell boundary
16
© Digital
Standard Cells
With minimal VDD With silicided VDD
diffusion diffusion
routing
VDD
M2
Out In Out
In
In Out
M1
GND GND
17
© Digital
Standard Cells
VDD 2-input NAND gate
VDD
B
A B
Out
A
GND
18
© Digital
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD VDD
Inverter
NAND2
Out Out
In A B
GND GND
19
© Digital
Stick Diagrams
Logic Graph X PUN
A
j C
B C
X i VDD
X = C • (A + B)
C
i B j A
A B
PDN
A GND
B
C
20
© Digital
Two Versions of C • (A + B)
A C B A B C
VDD VDD
X X
GND GND
21
© Digital
Consistent Euler Path
X i VDD
B j A
GND A B C
22
© Digital
OAI22 Logic Graph
X PUN
A C
B D D C
X VDD
X = (A+B)•(C+D)
C D
B A
A B PDN
A GND
B
C
D
23
© Digital
Example: x = ab+cd
x x
b c b c
x VDD x VD D
a d a d
GND GND
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
VD D
GND
a b c d
(c) stick diagram for ordering {a b c d}
24
© Digital
Multi-Fingered Transistors
One finger Two fingers (folded)
Less diffusion capacitance
25
© Digital
Properties of Complementary CMOS Gates
Snapshot
High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)
26
© Digital
CMOS Properties
 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay function of load
capacitance and resistance of transistors
27
© Digital
Switch Delay Model
A Req
A
Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV
28
© Digital
Input Pattern Effects on Delay
 Delay is dependent on
Rp Rp the pattern of inputs
A B  Low to high transition
 both inputs go low
Rn CL – delay is 0.69 Rp/2 CL
B  one input goes low
– delay is 0.69 Rp CL
Rn
Cint  High to low transition
A
 both inputs go high
– delay is 0.69 2Rn CL
29
© Digital
Delay Dependence on Input Patterns
3
Input Data Delay
2.5 A=B=10
Pattern (psec)
2 A=B=01 67
A=1 0, B=1
A=1, B=01 64
Voltage [V]
1.5
1
A=1, B=10 A= 01, B=1 61
0.5 A=B=10 45
0 A=1, B=10 80
0 100 200 300 400 A= 10, B=1 81
-0.5
time [ps] NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF 30
© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
Transistor Sizing
Rp Rp Rp
2 A B 2 4 B
Rn Rp Cint
CL 4
2 A
B
Rn Rn Rn CL
2 Cint
1
A A B 1
31
© Digital
Transistor Sizing a Complex
CMOS Gate
B 8 6
A 4 3
C 8 6
D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2
32
© Digital
Fan-In Considerations
A B C D
A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
33
© Digital
tp as a Function of Fan-In
1250
quadratic
1000
Gates with a
750
fan-in
tp (psec)
tpH tp greater than

500
L
4 should be
250 tpL avoided.
H linear
0
2 4 6 8 10 12 14 16
fan-in
34
© Digital
tp as a Function of Fan-Out
All gates
tpNOR2 tpNAND2 have the
same drive
tpINV current.
tp (psec)
Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out
35
© Digital
tp as a Function of Fan-In and Fan-Out
 Fan-in: quadratic due to increasing

resistance and capacitance
 Fan-out: each additional fan-out gate
adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
36
© Digital
Fast Complex Gates:
Design Technique 1
 Transistor sizing
 as long as fan-out capacitance dominates
 Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)
In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
37
© Digital
Fast Complex Gates:
Design Technique 2
 Transistor ordering
critical path critical path
charged 01
In3 1 M3 CL In1 M3 CLcharged
In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01
delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL
38
© Digital
Fast Complex Gates:
Design Technique 3
 Alternative logic structures
F = ABCDEFGH
39
© Digital
Fast Complex Gates:
Design Technique 4
 Isolating fan-in from fan-out using buffer
insertion
CL CL
40
© Digital
Fast Complex Gates:
Design Technique 5
 Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )

 linear reduction in delay
 also reduces power consumption
 But the following gate is much slower!
 Or requires use of “sense amplifiers” on the
receiving end to restore the signal level
(memory design)
41
© Digital
Sizing Logic Paths for Speed
 Frequently, input capacitance of a logic path
is constrained
 Logic also has to drive some capacitance
 Example: ALU load in an Intel’s
microprocessor is 0.5pF
 How do we size the ALU datapath to achieve
maximum speed?
 We have already solved this for the inverter
chain – can we generalize it for any type of
logic?
42
© Digital
Buffer Example
In Out
1 2 N CL
N
Delay    pi  g i  f i  (in units of tinv)
i 1
For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
43
© Digital
Logical Effort
 CL 
Delay  k  RunitCunit 1  
 Cin 
t p  g  f 
p – intrinsic delay (3kRunitCunit) - gate parameter  f(W)
g – logical effort (kRunitCunit) – gate parameter  f(W)
f – effective fanout
Normalize everything to an inverter:

ginv =1, pinv = 1
Divide everything by tinv

(everything is measured in unit delays tinv)
Assume  = 1.
44
© Digital
Delay in a Logic Gate
Gate delay:
d=h+p
effort delay intrinsic delay
Effort delay:
h=gf
logical effective fanout =

effort Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
45
© Digital
Logical Effort
 Inverter has the smallest logical effort and

intrinsic delay of all static CMOS gates
 Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
 Logical effort increases with the gate
complexity
46
© Digital
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD VDD VDD
A 2 A 2 B 2 B 4
F
F
A 4
A 2
A 1 F
A 1 B 1
B 2
Inverter 2-input NAND 2-input NOR
g=1 g = 4/3 g = 5/3

47
© Digital
Logical Effort of Gates
t pNAND
Normalized delay (d)
g= t pINV
p=
d=
g=
p=
d=
F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)
48
© Digital
t pNAND
Normalized delay (d)
g = 4/3 t pINV
p=2
d = (4/3)h+2
g=1
p=1
d = h+1
F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)
49
© Digital
2
=
p
3;
4/
5 1
=
p=
g
Normalized Delay
D:
4 AN 1;
g =
:
tN
e r
ert
pu
3 v
in
In Effort
2-
Delay
2
1
Intrinsic
Delay
1 2 3 4 5
Fanout f
50
© Digital
Add Branching Effort
Branching effort:
Con path  Coff  path

b
Con path
51
© Digital
Multistage Networks
N
Delay    pi  g i  f i 
i 1
Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Sdi = Spi + Shi

52
© Digital
Optimum Effort per Stage
When each stage bears the same effort:

hN  H
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage: f i  h g i
Minimum path delay
Dˆ   gi f i  pi   NH 1/ N  P
53
© Digital
Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
D  NH 1/ N  Npinv
D
N
 
  H 1/ N ln H 1/ N  H 1/ N  pinv  0
1/ Nˆ
Substitute ‘best stage effort’ hH
54
© Digital
Logical Effort
From Sutherland, Sproull

55
© Digital
Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c
Effective fanout, F =
G=
H=
h=
a=
b=
56
© Digital
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c
Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59
57
© Digital
1 b c
a 5
g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1
Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59
58
© Digital
Example – 8-input AND
59
© Digital
Method of Logical Effort
 Compute the path effort: F = GBH

 Find the best number of stages N ~ log4F
 Compute the stage effort f = F1/N
 Sketch the path with this number of stages
 Work either from either end, find sizes:
Cin = Cout*g/f
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
60
© Digital
Summary
Sutherland,
Sproull
Harris
61
© Digital
Ratioed Logic
62
© Digital
Ratioed Logic
VDD VDD VDD
Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3
VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
63
© Digital
Ratioed Logic
VDD
• N transistors + Load
Resistive
Load • VOH = V DD
RL
• VOL = RPN
F RPN + RL
In1 • Assymetrical response

In2 PDN
In3 • Static power consumption
• tpL= 0.69 RLCL

VSS
64
© Digital
Active Loads
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
depletion load NMOS pseudo-NMOS
65
© Digital
Pseudo-NMOS
VDD
F
CL
A B C D
VOH = VDD (similar to complementary CMOS)
 V2  k 2
OL p
k  V – V V – -------------  = ------  V – V 
n DD Tn OL 2  2 DD Tp

kp
V = V –V  1– 1 – ------ (assuming that V = V = V )
OL DD T k T Tn Tp
n
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

66
© Digital
Pseudo-NMOS VTC
3.0
2.5
2.0 W/Lp = 4
1.5
Vout [V]
W/Lp = 2
1.0
W/Lp = 0.5 W/Lp = 1

0.5
W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]
67
© Digital
Improved Loads
VDD
M1 M1 >> M2
Enable M2
CL
A B C D
Adaptive Load
68
© Digital
Improved Loads (2)
VDD VDD
M1 M2
Out Out
A
A PDN1 PDN2
B
B
VSS VSS
Differential Cascode Voltage Switch Logic (DCVSL)
69
© Digital
DCVSL Example
Out
Out
B B B B
A A
XOR-NXOR gate
70
© Digital
DCVSL Transient Response
2.5
AB
V olta ge [V]
1.5
AB
A,B
0.5 A,B
-0.5 0 0.2 0.4 0.6 0.8 1.0

Time [ns]
71
© Digital
Pass-Transistor
Logic
72
© Digital
Pass-Transistor Logic
Switch Out A
Out
Inputs
Network B
B
• N transistors
• No static consumption
73
© Digital
Example: AND Gate
A
B
F = AB
74
© Digital
NMOS-Only Logic
3.0
In
In
Out
1.5m/0.25m 2.0
Voltage [V]
VD D x x
Out
0.5m/0.25m
0.5m/0.25m 1.0
0.0
0 0.5 1 1.5 2
Time [ns]
75
© Digital
NMOS-only Switch
C = 2.5V C = 2.5 V
M2
A = 2.5 V A = 2.5 V B
Mn
B
CL M1
VB does not pull up to 2.5V, but 2.5V - VTN

Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
76
© Digital
NMOS Only Logic:
Level Restoring Transistor
VDD
VDD
Level Restorer
Mr
B
M2
X
A Mn Out
M1
• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X
• Ratio problem 77
© Digital
Restorer Sizing
3.0
•Upper limit on restorer size
•Pass-transistor pull-down
2.0 can have several transistors in
Voltage [V]
W/Lr =1.75/0.25
stack
W/L r =1.50/0.25
1.0
W/Lr =1.0/0.25 W/L r =1.25/0.25
0.0
0 100 200 300 400 500
Time [ps]
78
© Digital
Solution 2: Single Transistor Pass Gate with
VT=0
VDD
VDD
0V 2.5V
VDD 0V Out
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
79
© Digital
Complementary Pass Transistor Logic
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network
B B B B B B
A A A
B F=AB B F=A+B A F=AÝ
A A A
(b)
B F=AB B F=A+B A F=AÝ
AND/NAND OR/NOR EXOR/NEXOR

80
© Digital
Solution 3: Transmission Gate
C
C
A B A B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V
81
© Digital
Resistance of Transmission Gate
30
2.5 V
Rn Rn
Resistance, ohms
20 Rp
2.5 V Vou t
Rp
0V
10
Rn || Rp
0
0.0 1.0 2.0
Vou t , V
82
© Digital
Pass-Transistor Based Multiplexer
S S
VDD
VDD
S
A
M2
S F
M1
GND
In1 S S In2
83
© Digital
Transmission Gate XOR
B
M2
A
A
F
M1 M3/M4
B
84
© Digital
Delay in Transmission Gate Networks
2.5 2.5 2.5 2.5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In
C C C C C
0 0 0 0
(a)
Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In
C C C C C
(b)
m
Req Req Req Req Req Req

In
C CC C C CC C
(c)
85
© Digital
Delay Optimization
86
© Digital
Transmission Gate Full Adder
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P
Similar delays for sum and carry

87
© Digital
Dynamic Logic
88
© Digital
Dynamic CMOS
 In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type)
devices
 Dynamic circuits rely on the temporary

storage of signal values on the capacitance of
high impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type)
transistors
89
© Digital
Dynamic Gate
off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on
Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
91
© Digital
Conditions on Output
 Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.
 Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL
92
© Digital
Properties of Dynamic Gates
 Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static complementary
CMOS)
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect
the logic levels
 Faster switching speeds
 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL
93
© Digital
Properties of Dynamic Gates
 Overall power dissipation usually higher than static
CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk
 PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
 low noise margin (NML)
 Needs a precharge/evaluate clock
94
© Digital
Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk Mp
Out
A CL
VOut Evaluate
Clk Me
Precharge
Leakage sources
Dominant component is subthreshold current

95
© Digital
Solution to Charge Leakage
Keeper
Clk Mp Mkp
A Out
CL
B
Clk Me
Same approach as level restorer for pass-transistor logic
96
© Digital
Charge Sharing
Charge stored originally on

Clk Mp CL is redistributed (shared)
Out over CL and CA leading to
A CL reduced robustness
B=0 CA
Clk Me CB
97
© Digital
Charge Sharing Example
Clk
Out
A A CL=50fF
Ca=15fF B B B !B Cb=15fF
Cc=15fF C C Cd=10fF
Clk
98
© Digital
Charge Sharing
VDD
VDD case 1) if V out < VTn
Clk Mp
 Mp C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
Out
Out
or
CL
A Ma CL Ca
A Ma V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
XX CL
= CC a
BB 00 M
Mbb
a
case 2) if V out > VTn
Ca 
 ---------------------
CC
bb Vout = –V DD  -
Clk  Mee
M C
 a + C L
99
© Digital
Solution to Charge Redistribution
Clk Mp Mkp Clk

Out
A
Clk Me
Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)
100
© Digital
Backgate Coupling
Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2
B=0
Clk Me
Dynamic NAND Static NAND
101
© Digital
Backgate Coupling Effect
3
2
Out1
1 Clk
0
In Out2
-1
0 2 Time, ns 4 6
102
© Digital
Issues in Dynamic Design 4: Clock
Feedthrough
Coupling between Out and

Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
voltage of Out can rise
B
above VDD. The fast rising
Clk Me (and falling edges) of the
clock couple to Out.
103
© Digital
Clock Feedthrough
Clock feedthrough
Clk
Out 2.5
In1
In2 1.5
In3 In &
0.5 Clk
In4 Out
Clk -0.5
0 0.5 Time, ns 1
Clock feedthrough
104
© Digital
Other Effects
 Capacitive coupling
 Substrate coupling
 Minority charge injection
 Supply noise (ground bounce)
105
© Digital
Cascading Dynamic Gates
V
Clk Clk Clk

Mp Mp
Out2
Out1
In
In
Clk Clk VTn

Me Me Out1
V
Out2
Only 0  1 transitions allowed at inputs!

106
© Digital
Domino Logic
Clk Mp Clk Mp Mkp

11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5
Clk Me Clk Me
107
© Digital
Why Domino?
Clk
Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk
Like falling dominos!

108
© Digital
Properties of Domino Logic
 Only non-inverting logic can be implemented

 Very high speed
 static inverter can be skewed, only L-H transition
 Input capacitance reduced – smaller logical effort
109
© Digital
Designing with Domino Logic
VDD VDD
VDD
Clk Mp Clk Mp Mr
Out1
Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!
Clk Me Clk Me
Inputs = 0
during precharge
110
© Digital
Footless Domino
VDD VDD VDD
Clk Mp Clk Mp Clk Mp

Out1 Out2 Outn
0 1 0 1 0 1
In1 In2 In3 Inn
1 0 1 0 1 0 1 0
The first gate in the chain needs a foot switch

Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage
111
© Digital
Differential (Dual Rail) Domino
off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B
Clk Me
Solves the problem of non-inverting logic

112
© Digital
np-CMOS
Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp
Only 0  1 transitions allowed at inputs of PDN

Only 1  0 transitions allowed at inputs of PUN
113
© Digital
NORA Logic
Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp
to other to other
PDN’s PUN’s
WARNING: Very sensitive to noise!

114
© Digital

Digital Integrated Circuits: A Design Perspective

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Digital Integrated Circuits: A Design Perspective

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Digital Integrated

Output = f(In) Output = f(In, Previous In)

PUN and PDN are dual logic networks

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors pass a “strong” 1 but a “weak” 0

D 0  VDD S 0  VDD - VTn

PDN VDD  0 VDD  |VTp|

(a) pull-down network (b) Deriving the pull-up network A

(c) complete gate

Cell height is “12 pitch”

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

Less diffusion capacitance

High noise margins:

tpH tp greater than

 Fan-in: quadratic due to increasing

tp = a1FI + a2FI2 + a3FO

In2 M2 C2 Can reduce delay by more than

In2 1 M2 In2 1 M2 C2 discharged

delay determined by time to delay determined by time to

= 0.69 (3/4 (CL Vswing)/ IDSATn )

For given N: Ci+1/Ci = Ci/Ci-1

Normalize everything to an inverter:

Divide everything by tinv

logical effective fanout =

 Inverter has the smallest logical effort and

Inverter 2-input NAND 2-input NOR

g=1 g = 4/3 g = 5/3

Con path  Coff  path

Stage effort: hi = gifi

Path delay D = Sdi = Spi + Shi

When each stage bears the same effort:

Effective fanout of each stage: f i  h g i

Minimum path delay

From Sutherland, Sproull

 Compute the path effort: F = GBH

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

VDD VDD VDD

Resistive Depletion PMOS

VSS VSS VSS

Goal: to reduce the number of devices over complementary CMOS

In1 • Assymetrical response

• tpL= 0.69 RLCL

depletion load NMOS pseudo-NMOS

VOH = VDD (similar to complementary CMOS)

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

W/Lp = 0.5 W/Lp = 1

Differential Cascode Voltage Switch Logic (DCVSL)

-0.5 0 0.2 0.4 0.6 0.8 1.0

VB does not pull up to 2.5V, but 2.5V - VTN

• Advantage: Full Swing

W/Lr =1.0/0.25 W/L r =1.25/0.25

WATCH OUT FOR LEAKAGE CURRENTS

B F=AB B F=A+B A F=AÝ

B F=AB B F=A+B A F=AÝ

AND/NAND OR/NOR EXOR/NEXOR

Req Req Req Req

Req Req Req Req Req Req

Similar delays for sum and carry

 Dynamic circuits rely on the temporary

Two phase operation

 Output can be in the high impedance state

Dominant component is subthreshold current

Same approach as level restorer for pass-transistor logic