6/8/2018

ECE4740:
Digital VLSI Design
Lecture 15: Dynamic logic

542

Recap

Pseudo NMOS and

pass-transistor logic

543

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Ratio’ed logic
VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

• Goal: Reduce # of transistors over CMOS

• Ratio’ed = functionality depends on ratios!
• Static power  When exactly? 544
Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris

Improving loads is critical

VDD VDD

M1 M2

Out Out

!A
A PDN2
B PDN1
!B

VSS VSS

• Differential cascode voltage switch logic (DCVSL)

• No static power consumption but more routing
• Gates keep state  why could this be useful?
545
Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris

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Pass transistor logic: AND gate

B A B F=A*
B
A
0 0 0
B
F=A*B 0 1 0
0 1 0 0
1 1 1

• Requires 4 logic gates (needs an inverter)

• CMOS logic would require 6 logic gates
• The gate has no rail-to-rail swing
• Non-inverting logic 546

Key issue: static power

In = VDD
M2
A = VDD Vx = VDD-VTn

M1

• Pass transistor suffers from body effect

• M2 may be weakly conducting forming a
path from VDD to GND
• Can fix with level-restorer transistor
547

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We can go faster

Dynamic logic

548

Do not confuse with sequential logic

combinational sequential

In sequential or Out
Combinational
sequential Combinational
In Logic Out static CMOS
Logic
logic circuit
Circuit logic circuit
Circuit

state
State
CLK
CLK

• Sequential logic circuit considers input history

• Dynamic logic may also have a clock input!
549

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What is dynamic CMOS?

• Static CMOS circuits:
– Output is (except during switching) connected
to GND or VDD via low-resistance path
– N-input gate requires at least 2N transistors

• Dynamic circuits:
– Circuits rely on temporary storage of signal
values on capacitance of high impedance nodes
– N-input gate requires (at least) N+2 transistors

550

Principle of dynamic gate

precharge
transistor
CLK Mp
Out CLK Mp on
1
In1 CL Out
In2 PDN
In3 A
C
CLK Me evaluation B
transistor

CLK Me off
• Two-phase operation:
– Precharge  CLK=0
precharge
– Evaluation  CLK=1
551

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Principle of dynamic gate (cont’d)

CLK Mp
Out CLK Mp off
In1 CL Out
!(AB+C)
In2 PDN
In3 A
C
CLK Me B

CLK Me on
• Two-phase operation:
– Precharge  CLK=0
evaluation
– Evaluation  CLK=1
552

Conditions on output

• Once output of dynamic gate is discharged,

it cannot be charged again until next cycle
• Inputs to gate can make at most one
transition during evaluation: no glitches
• Output can be in high-impedance state
during and after evaluation (PDN off)
– State is temporarily stored on CL

553

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Why not this?

• Clock signal needs to
have higher voltage to
enable evaluation CLK Mp
Out
transistor  slower
CLK Me CL
• Body effect increases VT
In1
even further In2 PDN
• Worse clock feed- In3

through  I will talk

about that today
554

Properties of dynamic gates

• Logic function implemented by PDN only

– # of transistors is N+2 (vs. 2N for CMOS)
– Smaller area than static CMOS
• Full swing outputs (VOL=GND, VOH=VDD)
• Unratio’ed*: sizing only for performance
• No cross-over current: all current provided
by PDN goes into discharging CL

*ignoring parasitic effects 555

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Properties of dynamic gates (cont’d)

• Faster switching speeds
– Reduced load capacitance due to lower number
of transistors per gate  lower logical effort
– Reduced CL due to smaller fan-out
• Power dissipation should be better?
– Consumes only dynamic power, no cross-over
(or short circuit power)
– Lower CL: Cint and Cext FREE LUNCH!?
– No glitching
556

What are the disadvantages?

• Power usually much higher than CMOS
– Higher transition probabilities (due to precharge)
– Extra load on clock signal
– Clock signal switches every cycle
– Every gate needs a clock input
• PDN starts to work as soon as input signals
exceed VTn: VM=VIH=VIL=VTn
– Low noise margin (NML)
• Needs a precharge/evaluate clock
557

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Dynamic behavior
CLK Mp
2.5
Out evaluate
In1
1.5 precharge time
In2 determined by
width of Mp
In3
0.5 In &
In4 CLK
Out precharge
CLK -0.5
0 0.5 1
Time, ns

#Trns VOH VOL VM NMH NML tpHL tpLH tpre

6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps
558
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

Gate parameters are time dependent

• Amount of output voltage drop depends on
– Input voltage
– Available evaluation time (short is better)
CLK
2.5

Vout (VG=0.45)
1.5
Voltage (V)

Vout (VG=0.55)
Vout (VG=0.5)
0.5
VG
-0.5
could be an 0 20 40 60 80 100
input glitch Time (ns)
559

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Power consumption

• Power only dissipated

Mp
when previous Out=0
CLK
Out

In1 CL • Switching activity can be

In2 PDN higher than static CMOS
In3
– Activity does not depend
CLK Me on previous state
– Activity depends on signal
probabilities only

560

Dynamic logic

Issues and solutions

561

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Issue 1: charge leakage

PMOS leakage
mitigates issue a bit CLK
evaluate

Clk Mp
Out

A CL
VOut

Clk Me precharge

load capacitance
• Reverse-biased diode discharges

• Subthreshold current (dominant)

• Limits minimum clock frequency
562
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

Issue 1: charge leakage (cont’d)

• Output settles at voltage determined by
resistive divider of PMOS & NMOS

2.5

intermediate
Out voltage
1.5
Voltage (V)

0.5
CLK
leakage limits
min. clock rate
-0.5
0 20 40
to a few kHz
Time (ms)
563

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Solution to charge leakage

keeper • During precharge
Clk Mp Mkp
0 – Out=VDD and
1
!Out=GND
A Out
CL
B • During evaluation
off requires
Clk Me inverter – PDN off: keeper helps
to retain charge
– PDN on: if Mkp is
similar idea as for weak, PDN wins
pass-transistor logic  ratio’ed logic!
564

Issue 2: charge sharing

• Charge stored originally on
CLK Mp CL is redistributed (shared)
Out over CL and CA
A CL
• Leads to static power
B=0 CA
consumption by
CLK Me CB downstream gates and
possible malfunction
• When Vout = -VDD(CA/(CA+CL)) drop in Vout is
below the threshold of driving gate  malfunction
“capacitive
voltage divider” 565

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Charge sharing example: XOR3

• What is worst-case voltage drop on node y?
CLK
y=ABC

A !A CL=50fF
a

B b
CA=15fF !B B !B CB=15fF
c d

CC=15fF !C C CD=10fF

CLK

Assume all inputs are low during precharge & caps = 0V 566
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

Worst-case charge sharing

• Expose maximum amount of internal
capacitance!
CLK
y=ABC
!A*B*C=[011] A !A
a CL=50fF

B b
CA=15fF !B B !B CB=15fF
c d

CC=15fF !C C CD=10fF

CLK
Vout = -VDD((CA+CC)/(CA+CC+CL))
567

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Worst-case charge sharing (cont’d)

• 2nd solution:
A*!B*C=[101]
CLK
y=ABC

A !A CL=50fF
a

B b
CA=15fF !B B !B CB=15fF
c d

CC=15fF !C C CD=10fF

CLK
Vout = -VDD((CB+CC)/(CB+CC+CL))=-VDD(30/80)
568

(“Solution” to charge sharing)

precharge
transistor • Precharge all internal
(and critical) nodes
CLK Mp Mpt CLK using PMOS
Out
A
– Increases area
– Increases power (larger
B
capacitance)
CLK Me – Reduces speed (larger
capacitance)

569

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Issue 3: capacitive & backgate coupling

• Susceptible to crosstalk
– High-impedance output node
– Capacitive coupling from neighboring node
• Backgate coupling:
CLK Mp M6 M5
Out1 =1
Out2 0
A=0 M1 M4
CL1 CL2

B=0 M2 M3 In
off voltage
CLK Me reduces output
goes low
570
dynamic NAND static NAND

Backgate coupling effect

overshoots due to
3 clock feed-through

2
Out1
voltage drops due
1 Clk to backgate effect

0 Out2
In
never fully goes to
zero (coupling)
-1
0 2 Time, ns 4 6

If Out1 drops too much  incorrect behavior  careful with layout!

571
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic

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Issue 4: Clock feedthrough

• Capacitive coupling between CLK input of
precharge transistor and dynamic node
• Coupling between Out and
CLK Mp
CLK input of precharge
Out
A CL
device due to CGD
B
• Voltage of Out can rise
above VDD
CLK Me
• Fast rising (falling edges)
of clock couple to Out
572

Remember? dynamic behavior

clock or signal
feedthrough!
CLK Mp
2.5 evaluate
Out
In1
1.5
In2

In3
0.5 In &
In4 CLK
Out precharge
CLK -0.5
0 0.5 1
Time, nsclock or signal
feedthrough!
Does not only happen for dynamic circuits 573

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It’s not that easy

Problem with cascading

dynamic gates

574

Cascading causes problems

Two inverters: V

Clk
Clk Mp Clk Mp
Out2
In
Out1
In
VTn
Out1
Clk Me Clk Me
V
Out2

also discharges, t
because Out1 is
initially at VDD
575

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Cascading causes problems (cont’d)

• As nodes are charged

Clk Mp Clk Mp
to 1, they may cause
Out2 unwanted discharge
Out1
In
• Setting all inputs to 0
Clk Me Clk Me
during precharge
would fix the problem

• Only a single 0  1 transition allowed at

inputs during the evaluation period!
576

Cascading causes problems (cont’d)

• As nodes are charged

Clk Mp Clk Mp
to 1, they may cause
Out2 unwanted discharge
Out1
In
• Setting all inputs to 0
Clk Me Clk Me
during precharge
would fix the problem

• Only a single 0  1 transition allowed at

inputs during the evaluation period!
577

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Solution: domino logic

static CMOS
inverter

Mp CLK Mp
CLK 1 Out1 Out2
0
In1
In2 PDN In4 PDN

In3 In5 at end of

Me
precharge
CLK Me CLK

• Inputs to domino gate are set to 0 at end

of precharge period
578

Solution: domino logic (cont’d)

Mp CLK Mp
CLK
11 Out1 Out2
00
In1
In2 PDN In4 PDN

In3 In5 during

Me
evaluation
CLK Me CLK

• Inputs to domino gate are set to 0 at end

of precharge period
579

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Solution: domino logic (cont’d)

Mp CLK Mp
CLK
10 Out1 Out2
01
In1
In2 PDN In4 PDN

In3 In5 during

Me
evaluation
CLK Me CLK

• Only possible transition is 01, which

guarantees signal integrity
580

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