Topic – 6

Floor Planning & On-Chip Protection

Techniques

2019
2019//01/08 Shen-
Shen-Li Chen (NUU) 1

OUTLINE

I. Floor Planning (全晶片規劃)

II. Considerations of Analog Layout
III. I/O Design Concepts (I/O 設計觀念)

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 I. Floor Planning

(全晶片規劃)

VLSI Design Process

Floor Plan (全晶片規劃)


Physical (Layout) Design (佈局設計)

Tape Out (佈局圖寄出)

Mask Generation (光罩製作)

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General Layout Considerations

Whole IC: tight and formal (緊密且正式)

Power/grond routing: strong (強大)
Critical signal: clean and short (乾淨且短)

IC Design Considerations (IC設計考量)

 5 factors :
 NMOS, PMOS, wire, VDD, temperature
 4 factors :
 NMOS, PMOS, VDD, temperature
 3 factors :
 NMOS, PMOS, environment
 2 factors :
 NMOS, PMOS

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Floor Planning in an IC (IC全晶片規劃)

 Floorplanning
 Creating a sketch of the layout (佈局整體圖)
 A good floorplan includes
 An outline of the die (晶粒略圖),
 Placements of all pads (銲墊擺置), and
sizes and locations of all major cells (所有
 The
設計單元位置及大小)

Considerations in Floor Planning

What should be considered ?

Noise Immunity (雜訊免疫)
Signal routing (訊號佈線)
Power grid (電力網)

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Block Floor Plan (全晶片方塊規劃)

 Block Size (方塊大小)

 Power/Ground width and routing
 I/O and pin, size and orientation
 Cell allocation (基本單元分配)
 Interconnect routing, e.g.
Metal1 for horizontal
Metal2 for vertical

Floorplanning Strategies (全晶片規劃策略)

 Floorplanning must take into account blocks

of varying function, size, shape.
 Must design:
Space allocation (空間分配),
Signal routing (信號佈線),
Clock distribution (時脈佈線),
Power supply routing (電源線佈線).

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 電源線佈線 時脈佈線

Power tree Clock tree

VDD

VSS

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Benefit of Floorplanning (全晶片規劃之優點)

(規劃前) (規劃後)

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Floorplan Example

blocks

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Ex. : An Arithmetic Processor (運算處理器)

 Pad limited : 160

pin
 ...

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佈局：對稱擺置  電性對稱
 Symmetrical arrangement used to obtain electric symmetry

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Case1: Bandgap Circuit (Schematic)

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Case1: Bandgap Circuit (Layout)

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II. Considerations of Analog Layout

(類比電路佈局考量)

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Mixed-Signal Layout Strategy: Layout Procedure

(連導線議題)

(遮蔽議題)

(匹配議題)

(電源接地議題)

(全晶片規劃)

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Ex: 類比電路

 Mirror-image placement of two identical amps. (兩相同

放大器需對稱性佈局)
 The sensitive input circuitry to be placed far away from
the power devices.(輸入敏感性線路需遠離功率元件或
電源) 20
 混合訊號 IC 之問題

 Noise immunity (雜訊免疫力)

Analog circuit is very sensitive to noise
Sensitive analog nodes must be protected
 Ground and power supply routing (接地與電
源佈線)
Separate routing channels for analog and
digital circuitry

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Ex.: A Mixed-signal Floorplanning

 Sensitive analog unit: low-level signal, high-impedance nodes
 High-swing analog: comparators, output-buffer amplifier
(高擺幅 (振幅) 類比單元)

(敏感性類比單元)
(中擺幅類比單元)

(高擺幅類比單元)

(低速數位單元)

(高速數位單元)
(數位輸出驅動單元)
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The worst interference source : digital O/P
The most sensitive interference sensor : analog I/P
Low-speed ones are placed closer to the analog section

(中振幅 類比單元)

(高振幅 類比單元)
(低速數位單元)

(高速數位單元)
(數位輸出驅動單元)

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1). Power/Ground Supply

(電源接地議題)

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 1). Power/Ground Supply (電源接地議題)

(a) Poor noise immunity (b) Better noise immunity

(c) Best:
Using separate power
and ground pins to
achieve even better
noise immunity
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Power Supply Switching Noise

d (Id  Ia )
V  L  R1 ( I d  I a )  R2 I a
dt

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 Adding more power supply pins to distribute the current
In the same manner, if it is physically impossible to
increase the pin count for all bonding pads.
 VDD or VSS double bonding

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2). Matching (匹配議題)

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Matching (匹配議題)

The same size, or the same size unit;

The same placement ,orientation;
The same surrounding;
Not only for devices, but for routings

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(1). Ex.1: 電阻的佈局

(dummy) (dummy)
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Ex.2: 電阻的佈局

R R
1 2

Dummy strip
Dummy strip

R R
1 2

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High-value resistor
 Made by well diffusion
 Adding substrate bias guard ring to prevent noise
injection from substrate

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Thermal Gradient Effect

 Temperature coefficient of resistivity

Bad Good

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(2). Capacitor Layouts

Major errors caused by the overetching and an

oxide-thickness gradient.
 CI = Cox x1 y1

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Solutions: (1) Realizing larger capacitors from a parallel
 combination of smaller, unit-sized capacitors.
 (2) Common-centroid layout .
 (3) To minimize errors in capacitor rations due to
 overetching, their perimeter-to-area ratios
 should be kept the same.

p1 p
 2 k
A1 A2

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Adding Dummy Elements

Dummy
Elements

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(3). Ex.: 二極體的佈局

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(4). Ex.: MOSFET Device Matching

case1 case2
Differential
input stage

Case 3 (Best)
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Transistor Layouts

 Transistors in analog circuits are much wider

than in digital circuits.

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(a) Multiple-gate Fingers Type (多指狀)

 For a single large transistor

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(b) Interdigitalized Fingers Type

 For a differential pair transistors (數位交錯型; M1, M2)

 Match errors caused by the gradient effects
(temperature or gate-oxide thickness variation)
Drain (M1) Source (M1, M2)

Gate (M2)

Gate (M1)

Drain (M2) 42
(c) Interdigitalized Fingers Type

 For a differential pair transistors (4 n-MOSFETs)

(數位交錯型; M1, M2, M3, M4)

Source(M3)
Gate(M3,M4)

Gate(M1)
Gate(M2)

Ground
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(d) Common-Centroid Type (共心型)

 For a differential pair transistors (4 n-MOSFETs)

G1

G2

VSS

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 3). Block Shielding
(遮蔽議題)

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Block Shielding (遮蔽議題)

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Shielding: Use a M1 Shielding Layer
 Shielding a sensitive analog signal from a digital signal

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Shielding: Use a Dummy Metal

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 Shield all sensitive circuits, devices, and interconnection
lines.
(類比連接線)
(遮蔽用接地線)

(數位連接線)

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 Guard rings are placed around entire section

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Guard Rings (保護環)

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Guard Ring of Internal Circuits

PAD PAD

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Guard Ring of Internal Circuits

CORE

nMOS nMOS

PAD PAD PAD

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Placement and Biasing of Guardring

(數位保護環) (類比保護環)

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 Power distribution of mixed-mode ICs

(保護環)

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III. I/O Design Concepts

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過電壓的故障 (§4.8.6 )
 MOSFET電晶體很容易被外部的突波(靜電放電)所
損害，例如：氧化層崩潰、接面擊穿、與時間相關
之閘氧化層崩潰，都會形成過電壓(overvoltage)可
靠度的問題。
 當過電壓作用於閘極時，就會引發薄氧化層的崩潰
(breakdown)與電弧擊穿(arcing)，而摧毀元件。把
高於正常值的電壓作用在源極與汲極之間，而使源
極/汲極空乏區互相接觸，就會造成接面擊穿
(punchthrough)。
降低電源供應的電壓值、減少電源供應的雜訊、在
I/O 銲墊上使用較厚的氧化層，均可改善可靠度。
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Why is ESD a Problem ? (為什麼ESD突波是個問題?)

 The ESD event produces a large current and

high electric field in the semiconductor devices.
 Energy associated with the ESD released into
a small volume object, such as a protection
device, generates “self-heating”.
 Heat gives rise to a sudden temperature
increase.
 Device may be damaged if the heat cannot be
dissipated quick enough.

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Why Need ESD Protection Circuits ?
(為什麼 I/O 需要 ESD 防護電路？)

The rapid advanced in VLSI technology, ESD

damages are serious for the small geometry
device and high packing density.

The role of protection circuits become more and

more importance in ensuring the yield and
reliability (保證製程良率及可靠度) of the
integrated circuits.

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IC Pad Frame --- ESD Protection Circuits

I/O cells
I/O cells
I/O cells

Core
Circuits

I/O cells

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IC Pad Frame --- ESD Protection Circuits

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IC Pad Frame --- ESD Protection Circuits

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Whole Chip ESD Protections (全晶片ESD防護)

 I/O : PD, ND, PS, NS modes

Power pins : VDD2VSS mode
VDD


ESD2

ESD4

I/P Core O/P ESD5

ESD1 ESD3

GND
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Goal of ESD Protection Circuits

(I/O ESD防護電路之目標)

 Main protection circuit must be :

Small in area (面積小)

Turn on quickly to conduct a large amount
of current in a very short duration of time.
(在非常短時間內可以很快速導掉大電流)

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Co-related Factors of ESD Immunity

ESD Latch-up
突波 閂鎖

Noise
雜訊

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Influential Factors of ESD Immunity

ESD protection, LU, and noise are all influenced by
electrical, thermal, and spatial conductivity in a chip.

Electrical Thermal
電性 熱
ESD

Spatial
空間傳導
性 66
ESD Protection Circuits Response
(ESD 防護電路的反應)

 ESD protection circuits must divert ESD pluses before it

reaches the transistors on a chip, but at other times
they should not disturb the normal flow of data signals.

By pass
ESD
current 67

ESD Protection Circuits Response

(ESD 防護電路的反應)

When normal
signal is applied

When ESD
stress is applied

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 ESD Protection Circuits Response
(ESD 防護電路的反應)

Normal signal ESD transient

path path

Input Output Input Output

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On-Chip ESD Protection (晶片級ESD防護)

 The purpose is to limit the voltage (限制電壓) that appear at

the various circuit nodes and to dissipate the ESD current
through a know path (傳導ESD電流流過已知路徑).

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ESD Protection Circuits Should be
(ESD 防護電路應具備之條件)

(respond in 200ps)

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