A 1 V 6-bit 2.

4 GS/s Nyquist CMOS DAC for UWB Systems

Bong Chan Kim, Min-Hyung Cho, Yi-Gyeong Kim, and Jong-Kee Kwon

Electronics and Telecommunications Research Institute, 138 Gaj eongno, Yuseong-gu, Daej eon, 305-700,
Republic of Korea

Abstract - A 6-bit 2.4 GS/s current-steering DAC fabricated
in a 65 nm CMOS technology for ultra-wideband (UWB) systems
is presented. T he prototype achieves a measured spurious-free
dynamic range (SFDR) of more than 36 dB over the Nyquist
bandwidth at 2.4 GS/s. Among the 50 measured samples, DNL/
INL of 0.02/0.02 LSB was the lowest achievable value. T he DAC
core occupies an area of merely 0.023 mm2 through simplified
circuit and careful layout. To operate from a relatively low analog
power supply of 1 V, a portion of current cell is implemented
using low threshold voltage devices. Total maximum power
consumption, including the low voltage differential signaling
(LVDS) stage, is 14 mW at 2.4 GS/s.
Index Terms - digital-to-analog converter (DAC), full-Nyquist,
low threshold voltage, very high-speed, ultra-wideband (UWB).
I. INTRODUCTION
applied to compromise between static linearity versus area,
complexity, and power consumptions. Thermometer decoder
generates 7-bit unary code from the combination of 3 most
significant bits of the latched digital inputs. Each unary code
bit drives a current cell with 8 unit current sources connected
in parallel. 3 least significant bits of the latched digital input
are left in binary format to control the switches of the binary­
weighted current cells. Operations of the input latches and the
switch drivers are mutually exclusive. Input latches pass input
data to output when the clock is high whereas switch drivers
are transparent when the clock is low. These two operations
make DAC to update its output at negative clock edge. Sepa­
rate power supplies are used to isolate analog blocks from
noisy digital blocks.

Advancement in modem ultra-wideband (UWB) wireless OTIID Interface

CLK---.
systems demands high-speed and low- to moderate-resolution o Digital Block CLK/.. ••
data converters with sampling frequency in the order of o Analog Block
gigahertz. Even though the signal bandwidth necessary for
UWB communication (528 MHz for Multi-Band Orthogonal
Frequency Division Multiplexing (MB-OFDM» is smaller
than the Nyquist bandwidth of multi-GS/s DAC, attaining
higher sampling rate to some extent is advantageous in overall
system perspective. For a fixed signal bandwidth, increasing
the sampling rate mitigates the stop-band slope requirement of
the subsequent reconstruction filter and hence reduces the
complexity and power consumption. Low supply voltage and
low power consumption as well as small chip area are the
critical performance criteria for DACs operating in embedded
wireless environment. Satisfying these criteria to a reasonable '----------....--+OUTI
...
level enables cost-effective systems with long-lasting oper­ Fig. 1. Block diagram.
ation period from a minimum sized battery.
This paper presents low voltage, low power, and small area
DAC targeted for embedded UWB wireless applications.
III. CIRCUIT IMPLEMENTATION
Design process for current cell utilizing low threshold voltage
devices is described in detail. The DAC was fabricated in a 65 A. Interface Stage and Synchronized Decoders
nm CMOS technology achieving measured spurious-free dyn­
Prior to the synchronizing input latches, low voltage
amic range (SFDR) of more than 36 dB over the Nyquist
differential signaling (LVDS) stage is employed as an
range at 2.4 GS/s consuming maximum power of 14 mW.
interface to transmit high speed clock signals up to 2.4 GS/s
and the associated half clock rate digital input data to the DAC
II. DAC ARCHITECTURE core. Since the design has to support up to the sampling
frequency of 2.4 GHz, tight timing constraint is imposed on
Among several architectures of DACs, current-steering
the digital blocks. In order to ease this timing requirement,
structures are suitable for high-speed or UWB applications
input latches are inserted before the decoder blocks to
owing to their capability to directly drive the output resistive
load without the need for a buffer. Fig. 1 shows the block synchronize their inputs. Delays of the logic gates (NAND,
diagram of the implemented DAC. 3+3 segmentation has been NOR, etc.) in the thermometer decoder are optimized to meet

978-1-4244-7732-6/10/$26.00 ©2010 IEEE 912 IMS 2010

 the strict tImIng constraint. Although the 3-bit binary code
from the latched digital inputs and 7-bit unary code are
synchronized by the switch drivers prior to controlling the
switches, dummy decoder block is employed to reduce their
delay mismatches. In spite of the synchronization, the delay
mismatches between the current switch control signals for
unary and binary-weighted current cells could degrade dyn­
amic performance by producing large glitch energy at the
output waveform through capacitive feedthrough. Therefore,
the dummy decoder implemented with cascaded inverters is
designed to have approximately the same delay as the
thermometer decoder.
--Current Cell_ _Switch Driver__
�K
Fig. 2. Current celJ and switch driver.
B. Switch Drivers
Timings of the current switch control signals are critical to
achieve high dynamic linearity performance apart from the
strict timing constraint for high speed application. Switching
time mismatches cause distortion in the output signal and thus
degrade SFDR [ 1 ]. Circuit diagram of the switch driver with
low glitch is shown in Fig. 2. The switch drivers function as to
generate synchronized complementary switch control signals
from single-ended decoder outputs. Cross-coupled inverters
are used to reduce the transition time for the synchronized
inputs to stabilize and to maintain its value during off state of
the transmission gates. To enhance the synchronization, clock
routing is laid out as tree configuration. Moreover, to reduce
the routing area, complementary clock signals are generated at
the end of each branch node. 10 out of 1 6 clock routing
branches are connected to complementary clock generating
buffer that enables the switch drivers for 7 unary and 3 binary­
weighted current cells. Residual 6 branches are also connected
to the complementary clock generating dummy buffer to
match the delay of each branch. The ratio of PMOS width Wp
to NMOS width WN was set to 8 to realize high crossing point
of the driver's complementary output (CTRL, CTRLI). High
crossing point of complementary switch control signals
prevents the simultaneous tum off state of the differential
switches in the current cell, which would result in data
978-1-4244-7732-6/10/$26.00 ©2010 IEEE
dependent voltage variation at the common-source node of the
switches and in increased output transition time [2].
c. Current Cell
In order to minimize parasitic capacitance at the common­
source node of the switches and to ensure enough voltage
headroom for the current cells operating from a relatively low
1 V supply, low threshold voltage devices are used for
differential switches and cascode transistor. When imple­
menting the current cell, two design considerations namely the
matching property of the unit current sources and the dynamic
output impedance should meet the specified conditions to
achieve static and dynamic linearity performances, res­
pectively. The area of the unit current source transistor which
is related with the unit current matching property is
determined by ( 1 ) [3]
[ 4,,2 1( 2
J
2 "VT
I
WL= A + 2 . __
(1)
f! (V�S - )
V; u(l) ·
All and A IT are technology dependent mismatch parameters,
I and (J(I) are unit current and standard deviation of unit
current, respectively. To achieve 3(J (99.7%) INL-yield (ratio
of the number of DAC with INL < 0.5 LSB to the total
number of measured DAC) for 8-bit resolution (design margin
has been given), relative standard deviation (J(!)/I of the unit
current should be less than 0.0 1 [4]. Utilizing the details
explained above and the predetermined 5 mA full scale
current, length and width of the unit current source transistor
are set to 2 11m and 1 7.2 11m, respectively, ensuring tolerable
random mismatch.
Before making the decision on what type of device to use
for the current source transistor, output impedance and bias
line noise immunity were compared between the current cells
with standard (enhancement type) and low threshold
(depletion type) current sources. While comparing the two
cases, length and width of the unit current source transistors
were set to the value determined above assuming that the unit
currents, identical for both cases, are controlled by the gate­
source voltage only. This is acceptable since the foundry
provided mismatch parameters (Ap, Avr) of standard and low
threshold types are almost the same. Fig. 3(a) shows the
output impedance characteristics of the two current cells.
Current cell implemented with standard current source
exhibits higher output impedance than that with low threshold
current source by more than a factor of 2 (7 dB). The output
impedance of the current cell at steady-state with switch Mswi
turned OFF is approximated by (Fig. 2)
(2)
913 IMS 2010
 140������� attention has been given to the measurement environment to

\:: f:f:hl tl1 -� -40

\iii
-45
alleviate external interference on the DAC performance. For
example, printed circuit board (PCB) with equal lengths of
signal and clock routings was used to match propagation
delays from the pattern generator to the chip. Nominally
N ' " '. ' ,
C; 100 L----L--L---l-a--L--l 0 -50 identical 50 samples were measured for static linearity
o
: : : : �.J. : >
performance. INL distribution in Fig. 5 is consistent with the
(5 : : : : ""'.___L �
N 90 _._ Low Threshold _: Cl
o expected 3(J INL-yield for 8-bit resolution. The worst case
80 -.- Standard ___
�� (5
N INL is 0. 1 1 LSB6bit which is equivalent to 0.44 LSBSbit «0.5
100k 1M 10M100M 1G 10G 100k 1M 10M 100M 1G 10G LSBsbit). The sample with DNLIINL of 0.02/0.02 LSB6bit
Frequency [Hz] Frequency [Hz] achieves the highest static linearity. Single-ended output
Fig. 3. Simulation results of (a) output impedance and (b) bias signal for SFDR measurement is obtained by a transformer
noise immunity. which is connected to the common nodes of differential DAC
outputs and doubly terminated 50 n output resistive load. Fig.
Since the bias conditions of Msw and MCAS are identical for 6 shows output spectrum for 1 . 1 6 GHz signal at 2.4 GS/s. Fig.
the two cases, roes will be the determinant factor that brings 7 shows that SFDR considering third-order intermodulation
about the difference in the output impedance. Generally, bias distortion (IMD3) for 232 MHz and 24 1 .4 MHz signals is
providing metal wire extends through relatively long distance roughly 55 dB. SFDR plots versus normalized signal fre­
in order to supply constant gate-source voltage to all of the quency are shown in Fig. 8(a). DAC achieves more than 6-bit
unit current sources. Therefore, it is vulnerable to various (36 dB) dynamic linearity over the full-Nyquist range up to
types of noise such as capacitive coupling and circuit noises. 2.4 GS/s. Fig. 8 (b) shows SFDR as a function of sampling
Bias noise immunity is defined by the ratio of output voltage frequency for near-Nyquist and relatively low signal fre­
fluctuation �VOUT to bias voltage fluctuation �VBIAS (Fig. 2). quencies. The power consumption is 1 4 mW for near-Nyquist
Fig. 3(b) shows that standard type has 2 dB better bias noise signal at 2.4 GS/s. Table I summarizes the specification and
immunity than its low threshold counterpart. To enhance the measurement results. The presented DAC is compared with
suppression of the bias line noise, bypass capacitors are used recent low-resolution, very high-speed DACs for UWB
in bias circuit. According to the comparison results, we can applications in Table II.
conclude that selecting the standard type device for current
source is beneficial. Mismatches induced by systematic errors 20 ......
such as gradients in physical parameters over the wafer and
edge effects are compensated by common-centroid layout 1/1 15 ......
technique and by placing dummies around the current source Q.
:E
array, respectively. Current cell with single unit current source () 10 ......
-
is designed to have output impedance of 45 ill (93 dB) at 1 .2 o
'*I:
GHz to achieve >36 dB SFDR up to that frequency (Fig. 3(a)).

0.10

Fig. 5. INL histogram.

TABLE I
SPECIFICATION AND PERFORMANCE SUMMARY
Process 65 nm IP7M CMOS

Resolution 6 bit

Sampling rate 2.4 GS/s

Supply voltage 1 V (analog, digital)

DNUINL 0.02/0.02 LSB

Fig. 4. Chip photograph.
SFDR 36 dB (1.16 GHz @ 2.4 GS/s)

55 dB (232 MHz and 241.4 MHz

SFDR (IMD3)
@ 2.4 GS/s)
IV. MEASUREMENT RESULTS
Power consumption 14 mW (1.16GHz @ 2.4GS/s)
The chip shown in Fig. 4 was fabricated in a 65 nm IP7M
2 Core area 0.023 mm2
CMOS technology which has a core area of 0.023 mm • Much

978-1-4244-7732-6/10/$26.00 C2010 IEEE 914 IMS 2010

 V. CONCLUSION

The presented current-steering DAC achieves the smallest

area and the lowest FoM value compared with other recently
published very high-speed CMOS DACs for UWB appli­
2
cations. The core area is only 0.023 mm and maximum power
consumption is 14 mW at 1 V supply. It achieves 6-bit
dynamic linearity (36 dB SFDR) over the full-Nyquist range
at 2.4 GS/s and DNL/INL of 0.02/0.02 LSB. Regarding the
current source device, simulation results show that standard
type is superior to low threshold voltage type in terms of
output impedance (7 dB) and gate bias noise immunity (2 dB).

ACKNOWLEDGEMENT
Fig. 6. Output spectrum for near-Nyquist signal at 2.4 GS/s.
This work was supported by IT R&D program of
MKE/IITA, Rep. of Korea [2009-S-0l5-0l, Development of
Analog Circuit Techniques for Mixed SoC based on 45 nm
CMOS Technology].
."
•

REFERENCES

[1] T. Chen, et aI., "The Analysis and Improvement of a Current­

Steering DAC's Dynamic SFDR-II: The Output Dependent
Delay Differences," IEEE Trans. Circuits Syst. I, vol. 54, pp.
268-279, Feb. 2007.
[2] A. Van den Bosch, et aI., "A lO-bit I-GSample/s Nyquist
Current-Steering CMOS D/A Converter," IEEE 1. Solid-State
Circuits, vol. 36, pp. 315-324, Mar. 2001.
[3] X. Wu, et aI., "A 130 nm CMOS 6-bit Full Nyquist 3 GS/s
SPRH 75.2 "Hz DAC," IEEE 1. Solid-State Circuits, vol. 43, pp. 2396-2403,
SWP Be _sec

Fig. 7. Two-tone output spectrum at 2.4 GS/s. Nov. 2008.

----:.-
[4] A. Van den Bosch, et aI., "An Accurate Statistical Yield Model

. r ,, -. I" T for CMOS Current Steering DIA Converters," Proc. IEEE Int.
48 Symp. Circuits and Syst.,
I -------- I ---------- , ---------- I----------- I ---------- I ----

pp. IV.! 05-IV.108, May 2000.

:. : : : (aj
: ��,-. : : [5] S. M. Lin, et aI., "I V 1.25 GS/s 8 mW D/A converters for MB­
Proc. IEEE Int. Con! Ultra­
---1-------- -��r�-� �·i�.i----
- - - - ii l-- -
OFDM UWB transceivers,"
Wideband, pp. 453-456, Sept. 2007.
---J-----------,----------��-
--@O.5GS/s i
[6] R. Chen and S. Chang, "A 5-bit 1. 35-GSPS DAC for UWB
Transceivers," Proc. IEEE Int. Con! Ultra-Wideband, pp. 175-
�__ i i
- @1.0GS/s : : � : 179, Sept. 2009.
---. --@2.4 GS/s _:----------�-----------�-------:A :----
, I I ,

TABLE II
0.0 0.1 0.2 0.3 0.4 0.5
COMPARISON WITH OTHER DACs

FSIG/FCLK This work [3] [ 5] [6]

48 --- -------:---------------: ------------- � ------------- � - 65 nm l30 nm l30 nm 180 nm
e� Process

---�------i--------------i-���,,<==�--t-
CMOS CMOS CMOS CMOS
i e----r-e--.L i (b) i
Iii' 44 Resolution 6 bit 6 bit 6 bit 5 bit
�
��
Sample rate 2.4 GS/s 3 GS/s 1.5 GS/s 1.5 GS/s
� 40 +-
----- ----- . f �
------------ ------------- -
Power 14 mW 29 mW 9 mW lO .4 mW
LL
� FSIG/FCLK=O.484
·-------ii-------------
.-+- i---------�-.... -ii -
(J) Core area 0.023 mm2 0.2 mm2 0.08 mm2 0.19m m2
36 - Fs1iFcLK=O.172
FoM 0.091 pJ 0.15 pJ 0.094 pJ 0.22 pJ

0.5 1.0 1.5 2.0 2.5 N

* FoM is defined as Power/(2 'Sample rate).

FCLK [GS/s]
Fig. 8. SFDR vs. (a) signal frequency normalized to sampling
frequency and (b) sampling frequency.

978-1-4244-7732-6/10/$26.00 C2010 IEEE 915 IMS 2010