Proceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems"
0,;(' '(6,*1
June 27-29, 2019, Rzeszów, Poland

A Low Power, Low Chip Area, Two-stage

Current-mode DAC Implemented
in CMOS 130 nm Technology
Jakub Dalecki1 , Rafał Długosz1,2 , Tomasz Talaśka1,2 , Gunter Fischer3
1
UTP University of Science and Technology
Faculty of Telecommunication, Computer Science and Electrical Engineering
ul. Kaliskiego 7, 85-796, Bydgoszcz, Poland
2
Aptiv Servics Poland
ul. Podgórki Tynieckie 2, 30–399, Kraków, Poland
3
IHP – Innovations for High Performance Microelectronics
Technologiepark 25, 15236 Frankfurt (Oder), Germany
e-mails: jakub.dalecki@gmail.com, rafal.dlugosz@gmail.com, rafal.dlugosz@aptiv.com,
tomasz.talaska@gmail.com, gfischer@ihp-microelectronics.com

Abstract—The paper presents measurement results of a current
mode digital-to-analog converter (DAC), implemented in the IHP
CMOS 130 nm technology. The proposed two-stage DAC is
composed of 10 branches, so theoretically 10 bits of the resolution
may be obtained. The circuit is reconfigurable. This means that if
smaller resolutions are sufficient, the user may select the branches
that are used in data conversion. The measurements were carried-
out using a programmable measurement setup, designed for this
purpose, equipped with precise current sources. Five samples of
the prototype chip were tested. The measurements were carried
out for different values of particular parameters. The circuit has
been designed as one of the components of a Successive Ap-
proximation Register (SAR) analog-to-digital converter (ADC).
However, it can be used as a separate block also for other
purposes. The chip area of the overall ADC does not exceed
0.01 mm2 , with the DAC occupying 60 % of this area.
Keywords—DAC, current mode, CMOS technology, pro-
grammable circuit
I. I NTRODUCTION
Digital-to-analog converters (DACs) play an important role
in signal processing. They join systems that operate with
digital and analog signals. Their task is to convert the digital
input signal into a corresponding current or voltage analog
signal. Converters of this type are widely used in many
different applications, such as metrology [1], electronics [2],
[3], [4], control [5], telecommunication [6], [7], etc. DACs are
one of the basic blocks of successive approximation register
(SAR) analog-to-digital converters (ADC) [8]. They are also
used in artificial neural networks [9].
Depending on where they are used, different parameters
play a key role. The metrology usually requires high reso-
lution and accuracies. On the other hand, in wireless control
systems, speed and power consumption are the most important
parameters. For this reason, there exists various development
approaches of the DACs reported in the literature. They are
made both in bipolar and unipolar technologies.
The development of DACs and the improvement in their
parameters and properties was possible due to their implemen-
tation in the form of application specific integrated circuits
(ASICs). Depending on their type and the application, they
may be built of resistors (optional transistors), capacitors,
power sources. The configuration (connection to each other)
of these elements are controlled by switches.
The most popular architectures of the DAC include:
• parallel (string) DACs (based on a Kelvin divider [10],
[11]). Circuits of this type require a large number of
switches, which makes them not attractive in practical
usage,
• binary weighted converters [12], [13], including the most
popular ones that are based on the, so-called, R-2R
divider. In this approach, the accuracy and the linearity of
the converter is determined by ratios between particular
resistances, and not on their absolute values. Difficulties
in fabrication of resistors with precise values caused that
only two resistance values (R and 2R) are usually used,
• cascaded (segmented DAC) [14] that combine different
types of approaches, e.g. the above-mentioned DAC ar-
chitectures, to increase the resolution,
• interpolative DACs with oversampling [15]. In this case,
the number of switches compared to the above mentioned
solutions is smaller and amounts to one. We pay for
it with substantial over-sampling of the signal. This
approach is used for high resolution converters.
• multiplying DAC (MDAC), etc.
In this work, we present laboratory tests of a two-stage DAC
working in the current mode. The converter is based on two
multi-output current mirrors, with appropriately selected gains
of particular branches. This converter was initially designed
for the use as a component of a SAR ADC, to provide
reference current [8]. However, a similar circuit may also
be used in artificial CWTA (Conciences Winner Takes All)
neuron networks to support the conscience mechanism of the
neurons.

*QTv`B;?i Ü kyRN #v .2T`iK2Mi Q7 JB+`Q2H2+i`QMB+b  *QKTmi2` a+B2M+2- GQ/x lMBp2`bBiv Q7 h2+?MQHQ;v R8R
 The work is a continuation of our previous work [8], where
the concept of the circuit, as well as the simulation results were
presented. The converter has been implemented in the IHP
CMOS 130 nm technology and verified by means of Spectre
simulations.
The paper is structured as follows. Next Section presents
the structure of the proposed DAC. Described is the idea of
the circuit as well as provided are equations describing the
concept of the circuit. In the following Section we present
selected verification (simulation and measurement results).
The obtained results are discussed in this Section a well.
Conclusions are formulated in last Section.
II. T HE P ROPOSED 2- STAGE DAC AND I TS
I MPLEMENTATION
The concept of the proposed current-mode 2-stage DAC is
shown in Fig. 1. It is based on the cascoded current mirrors
(CMs), used to increase the circuit precision.
A usual phenomenon observed in CMs is its sensitivity to
transistor mismatch. One of the possibilities to reduce the
impact of this effect on the circuit precision is to oversize
the transistors. However, in case of a multi-output CM with
binary weighted gains of particular branches, if the number
of bits is large, the sizes of particular transistors become very
large. For example, for 10 bits of the resolution, the width of
the transistors in the branch representing the most significant
bit (MSB) is 512 times larger than the one in the branch
representing the least significant bit (LSB). In this situation,
if we oversize the smallest transistor with a unit width (UW),
this in practice limits the resolution of the converter.
(a)
(b)
Fig. 1. Structure of the 2-stage current-mode n-bits DAC: (a) general idea, (b) CMOS implementation.
R8k
To solve this problem we proposed a technique, in which
the DAC is realized as a cascade connection of two CMs. The
first of them (1st stage) is a multi-output PMOS mirror. Its
particular n outputs are connected to NMOS CMs (2nd stage),
in which transistors are not binary weighted. The gains of
particular resultant 2-stage branches are products of the gains
of particular CMs. This allows for keeping spreads between
transistor in particular intermediate CMs much smaller than in
a single-stage binary-weighted approach and thus to increase
the value of UW.
An input current Itr allows for scaling an upper range of the
reference current Iref . This current is copied to each branch
of the first (PMOS) CM, with the following gains:
k1,n = {1, 1, 2, 2, 4, 4, 8, 16, 16, 16}/G (1)
where G is a gain between the Itr and the current in the LSB
branch of the first CM (25 or 32). Resultant currents I1,n are
provided to their counterpart NMOS CMs, with the following
gains:
k2,n = {1, 2, 2, 4, 4, 8, 8, 8, 16, 32} (2)
The resultant output currents I2,n are binary weighted, as
in a conventional single-stage approach:
kn = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512} (3)
An appropriate selection of the k1,n and the k2,n coefficients
allows for a substantial reduction of the sum of the widths in
all transistors used in the DAC. For the applied resolution of case, therefore the LSB equals 40 nA (G = 25 in this case).
10 bits, the sum of the widths in a single-stage approach would Fig. 3 illustrate the results for the same Itr and all branches
equal being active. Thus the LSB equals 10 nA in this case.
These results, reported already in [8], are presented here
SUW,1 = (1023 + G) · UW = 1055 · UW (4) as a background for the new measurement results, obtained
recently. The simulations show that the gains of particular
For the comparison, in the proposed implementation of the
branches of the DAC have been selected properly. Both Figures
2-stage DAC, for the coefficients given by 1 and 3, the sum
illustrate the reference current Iref , raising up for following
of the widths equals:
input codes, as well as a total supply current IDD . The resultant
  power dissipation for 7 and 10 bits of the resolution equals
SUW,2 = ( k1,n + k2,n +G+10)·UW = 197·UW (5) 20 μW and 35 μW, respectively.

Factor 10 in 5 is due to the fact that in the second stage of

the DAC, in each branch in addition to the output transistor
with the width k2,n UW, there is also an input transistor with
a width of 1 UW. For the simplicity, in these calculations, we
do not take into account multiple transistors used in cascoded
CMs. A disadvantage of the proposed approach is a larger
number of branches in both stages of the DAC, resulting in a
slightly higher summary current (increased by ca. 5 %).
The circuit has been realized in the IHP CMOS 130 nm
technology and thoroughly verified by means of both the
transistor level simulations performed in Spectre environment
and the laboratory measurements.
The overall prototype chip that includes the proposed DAC
may be programmed. One of the possibilities is to select
the range of branches that are used in a given situation. It
enables selecting the resolution of the DAC, and thus of the
overall ADC, as well as other parameters. The DAC and
the ADC are programmed using a 10 bit, P , signal that
provides an appropriate configuration code. The principle is
as follows, the first ‘0’ in the P parameter turns on a block
of branches used in the conversion process, while the second Fig. 2. Simulations of the DAC for the resolution of 7 bits (P =‘1101111110’,
Itr = 250 nA → LSB ∼ 40 nA).
‘0’ turns off the remaining branches. For example, for P1 =
‘0111111111’ all branches are turned on, so the DAC operates
in 10 bit mode. If for example only 7 bits are required, we
can indicate which branches are used. For example, for P2 =
‘0111111011’ we disable three most significant branches. In
another example, for P3 = ’1101111110’, we disable two least
significant branches and a single most significant one.
The possibility of programming the converter is one of the
advantages of the proposed solution. It allows for scaling the
Iref current and thus the power dissipation and data rate of
the DAC, without the use of additional amplifiers.
III. V ERIFICATION OF THE P ROPOSED DAC
A. Transistor level simulations
The DAC was thoroughly verified before the fabrication of
the chip, by means of the Spectre simulations [8]. The tests
that were carried out at this step included a corner analysis,
performed for several transistor models (typical, slow and
fast), and temperatures varying in-between -40 and 100 ◦ C
degrees. Figs. 2 and 3 illustrate selected results for 7 and 10
bits of the resolution, respectively. Fig. 2 presents the results
for branches No. 3, 4, ..., 9 being active. The Itr current was Fig. 3. Simulations of the DAC for the resolution of 10 bits
set to 250 nA. Since two LSB branches are not used in this (P =‘0111111111’, Itr = 320 nA → LSB ∼ 10 nA).

R8j
 B. Measurements of the proposed DAC
1) Measurement setup: The designed measurement setup
was based on the National Instruments MyRio measuring
device. Appropriate current sources providing the Iref and
a bias currant, as well as the measurement equipment have
been connected to the device directly through the USB ports,
managed by MyRio. The device was also responsible for
communication with the prototype chip, through the LVTTL
interface.
The MyRio device operates under the control of the Lab-
View environment. A labview vi file is, through the USB
interface, provided to the device and launched. The proto-
type chip is equipped with a set of multiplexers that enable
testing particular internal blocks in various configurations (a
multiphase programmable clock, the DAC and the ADC).
Before starting standard measurements, it is necessary to
configure the multiplexers. We have written a special tool for
generating both the programming and testing signals [16]. The
tool generates a file with signals for particular inputs of the
chip. The file is placed in the memory of MyRio device. A
general measurement scheme (carried out automatically) was
as follows:
(a) configuration of the current sources and the measure-
ment equipment,
(b) configuration and programming the chip,
(c) selection of the resolution of the DAC and the range of
active branches,
(d) measurements and readout of data from the measure-
ment devices,
(e) aggregation and data storage.
Points (c) and (d) are executed in a loop, depending on the
resolution of the converter. For 10 bits of the resolution, the
number of iterations equals 1024. The measurement results are
stored into an output csv file.
The current sources used in the measurements were Keithley
2400 working in the range of 10 μA (accuracy 0.033 % +/-
2 nA). The Tektronix DMM4050 multimeters were used to
measure the output current from the DAC. In order to improve
the measurement accuracy, the “Integration Time” has been
increased. This allowed to record stable and repeatable results
with a resolution of 100 pA.
The measurement setup – a PC board used to control the
chip and to communicate with it – provides necessary power
supply. It also contains a Xilinx CPLD device, who plays a
role of a signal wrapper between the MyRio device and the
chip.
2) Laboratory tests: The measurements were carried out
for different DAC resolutions (in-between 5 and 10) and for
different values of the Itr current: 80, 160, 320 and 640 nA.
Figs. 4, 5, 6, 7 and 8 illustrate the input-output characteristic
of the DAC – the output current Iref as a function of a multi-
bit digital input signal, for selected values of the Itr current.
The presented tests were carried out at the room temperature,
i.e. about 20 ◦ C degree.
R89
The results are presented for one of five tested samples of
the chip. Each sample was tested many time, to avoid random
measurement errors. The error is illustrated in Fig. 9. It was
determined by the comparison of the measurement results with
average values obtained over all measurements of a given
sample, for a given value. As can be observed, the repeatability
of the measurement results is large. A small error below 2 %
occurs only for the LSBs.
In the presented measurement results, one can observe that
at the moment when the 7 th branch is switched over, a certain
systematic error appears in the input-output characteristic.
A similar effect appeared in all tested samples, however, at
different branches. For a given sample, the same relative error
is observed, independently on the value of the configuration
currents. In our opinion, it indicates that this error appeared
during the fabrication process of the chip, as in the simulations
we did not observe this effect.
3) Discussion of the obtained results: Observing the mea-
surement results, one can notice some non-linearities in the
input-output characteristics. The problem are discrepancies of
the gains of selected branches compared to their assumed
theoretical values. It was surprising that the nonlinearity may
occurs in the branches corresponding to older bits, and not (as
expected) for the younger ones, for whom smaller transistors
were used. Based on the analysis of the results and the
structure of the DAC, we think that the NMOS current mirrors
used in the second stage of the DAC is a potential problem.
In these mirrors, the input transistor has sizes comparable to
those that in the PMOS CM correspond to the youngest bits.
In the next prototype, this will be taken into account and the
sizes of these transistors will be increased.
A brief comparison with other state-of-the art DACs de-
scribed earlier is presented in Table I. To facilitate the com-
parison, we defined two Figure-of-Merits (FOM), to assess the
performance at the signal processing level, and to compre the
chip ares. The first FOM is defined as the power dissipation
over data rate, normalized to the number of bits (thus the 2n
factor in the denominator):
FOMP = P/(2n · fS ) (6)
The second FOM is defined as the chip area normalized to
the number of bits, as in 6:
FOMA = A/(2n ) (7)
In Table I in case of the proposed solution we provide two
numbers of the FOM_P. One is for a theoretical resolution
of 10 bits, while the second one is for real resolution of 7
bits, after taking into account the described nonlinearities.
We suppose that after the redesign of the DAC we will
achieve higher real resolutions, without worsening remaining
parameters. Even for 7 bits of the resolution, the obtained
results are comparable with some of other DACs. Much better
results have been achieved for the FOM_A factor. It is one of
the main advantages, as the DAC and the overall ADC were
designed just to reach as small chip area as possible.
Fig. 4. Measurements of the DAC for the resolution of 10 bits
(P =‘0111111111’, for the Itr current equal to 80, 160, 320 and 640 nA.
Fig. 5. Measurements of the DAC for the resolution of 9 bits
(P =‘0111111110’, for the Itr current equal to 80, 160, 320 and 640 nA.
Fig. 6. Measurements of the DAC for the resolution of 8 bits
(P =‘0011111111’, for the Itr current equal to 80, 160, 320 and 640 nA.
IV. C ONCLUSIONS
The paper may be viewed a measurement report of a
novel 10-bit programmable current-mode, two-stage DAC,
implemented in the IHP CMOS 130 nm technology. The
proposed circuit in the current form is a flexible solution, as
different ranges of the branches may be used (thus different
parameters), depending on needs. An initial project assumption
was to develop a low resolution SAR ADC (up to 7 or 8
bits) with the DAC used as a source of the reference signal.
Fig. 7. Measurements of the DAC for the resolution of 6 bits
(P =‘0000111111’, for the Itr current equal to 80, 160, 320 and 640 nA.
Fig. 8. Measurements of the DAC for the resolution of 5 bits
(P =‘0000011111’, for the Itr current equal to 80, 160, 320 and 640 nA.
Fig. 9. Measurement error of the DAC in subsequent measurement sessions
for a single sample, compared to an average value obtained in all measure-
ments.
Finally we decided to realize a circuit with higher resolution,
to increase the testing abilities of the proposed concept. In
this context, the obtained results may be treated as temporary,
while the circuit needs to be slightly redesigned. The main
objective was to obtain an ADC with very low chip area, as
there are applications in which many such ADCs are required
in a single chip. The overall ADC in the current form occupies
only 0.01 mm2 of silicon.
R88
 TABLE I
C OMPARISON OF SELECTED DAC S IMPLEMENTED IN CMOS TECHNOLOGY

Ref. Supply Res. fS P A FOM (power) FOM (area)

(Techn.) [V] bits [MSmpl./s] [mW] [mm2 ] fJ/conv [μm2 ]/bit
[15]
3.3 ND 6.144 7.26 0.61 ND ND
(130 nm)
[12]
1.8 10 1000 27 0.2 26.37 195.3
(180 nm)
[3]
1.1 6 4000 13 0.09 50.78 1406
(40 nm)
[11]
3.3 12 0.0285 0.00792 0.04 67.84 9.765
(0.35 μm)
[2]
1.2 10 ND 0.00522 0.16 ND 156.25
(65 nm)
This
1.2 10 1 0.009 0.006 9.79 (*) / 70 (**) 5.86
work
(*) for the resolution of 10 bits (chip design – theoretical)
(**) for the resolution of 7 bits (worst case – for which the linearity is achieved)

R EFERENCES [9] T. Talaśka, A. Rydlewski, R. Długosz, “A new realization of the

[1] R. Kochan, A. Sachenko, V. Kochan, “Double cascade digital to
analogue converter for metrology testing,” IEEE Instrumentation and
Measurement Technology Conference, Vol. 2, 2014.
[2] L. Koushaeian, B. Ghafari, F. Goodarzy and R. Evans, “A 5.22 uW
digital-to-analog converter based on I-2I CMOS architecture, ” IEEE
2013 Tencon - Spring, 2013.
[3] Long Zhao, Ji He, Yuhua Cheng, “A 6bit 4GS/s current-steering digital-
to-analog converter in 40nm CMOS with adjustable bias and DfT block,”
International Conference on ASIC (ASICON), 2015.
[4] Olga Joy L. Gerasta, Ace Virgil D. Villaruz, “Reconstruction filter for
Delta-Sigma oversampling digital-to-analog converter implemented in
0.18um CMOS technology,” International Conference on Humanoid,
Nanotechnology, Information Technology,Communication and Control,
Environment and Management (HNICEM), 2015.
[5] H.K. Lam, “Sampled-data fuzzy-model-based control systems: stability
analysis with consideration of analogue-to-digital converter and digital-
to-analogue converter,”, IET Control Theory & Applications, Vol. 4. Iss.
7, 2010.
[6] J.J. Wikner, N. Tan, “Modelling of CMOS digital-to-analog converters
for telecommunication ,” IEEE International Symposium on Circuits and
Systems(ISCAS), Vol. 1, 1998.
[7] N. Tan, J.J. Wikner, “A CMOS digital-to-analog converter chipset for
telecommunication,” IEEE Circuits and Devices Magazine, Vol. 13. Iss.
5, 1997.
[8] R. Długosz, and G. Fischer, “Low Chip Area, Low Power Dissipation,
Programmable, Current Mode, 10-bits, SAR ADC Implemented in the
CMOS 130nm Technology,” International Conference Mixed Design of
Integrated Circuits and Systems (MIXDES), Gdynia, Poland, 2015.
conscience mechanism for self-organizing neural networks implemented
in CMOS technology,” International Conference on Microelectronics
(MIEL) , Belgrad, Serbia, 2014.
[10] Hyeon-Cheon Seol, Seong-Kwan Hong, Oh-Kyong Kwon, “An Area-
Efficient High-Resolution Resistor-String DAC with Reverse Ordering
Scheme for Active Matrix Flat-Panel Display Data Driver ICs,” Journal
of Display Technology, Vol. 12, Iss. 8, 2016.
[11] Dong-Kyu Jung, et. all, “A 12-bit Multi-Channel R-R DAC Using
a Shared Resistor String Scheme for Area-Efficient Display Source
Driver,” IEEE Transactions on Circuits and Systems I: Regular Papers,
Vol. 65 , Iss. 11, 2018.
[12] Ding-Lan Shen, Yuan-Chun Lai, Tai-Cheng Lee, “A 10-bit binary-
weighted DAC with digital background LMS calibration,” IEEE Asian
Solid-State Circuits Conference, 2007.
[13] D. Arbet, G. Nagy, V. Stopjaková, G. Gyepes, “A self-calibrated binary
weighted DAC in 90nm CMOS technology,” International Conference
on Microelectronics MIEL, Belgrade, Serbia, 2014.
[14] M. S. Yenuchenko “Alternative structures of a segmented current-
steering DAC," International Symposium on Consumer Technologies
(ISCT), St. Petersburg, Russia, 2018
[15] Yujin Park, Han Yang, Hyunjong Kim, Jun Soo Cho, Suhwan Kim, “Low
noise output stage for oversampling audio DAC," IEEE International
System-on-Chip Conference (SOCC), Beijnig, China, 2015
[16] M. Banach, T. Talaśka, J. Dalecki, R. Długosz, “New technologies
for smart cities - high- resolution air pollution maps based on intelli-
gent sensors,” Concurrency Computat Pract Exper. 2019;e5179., Wiley,
DOI:10.1002/cpe.5179, 2019.

R8e