This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TNS.2016.2602391, IEEE
Transactions on Nuclear Science
Ultra-low power fast multi-channel 10-bit ADC
ASIC for readout of particle physics detectors
Sz. Bugiel, R. Dasgupta, M. Firlej, T. Fiutowski, Member, IEEE, M. Idzik, Member, IEEE, M. Kopec, J. Moron,
K. Swientek
Abstract—The design and measurement results of an ultra-
low power multi-channel fast 10-bit Analog-to-Digital Converter
(ADC) ASIC, developed for readout systems in future particle
physics experiments, are discussed. An 8-channel prototype with
a PLL-based data serialization and a fast data transmission was
designed and fabricated in a 130 nm CMOS process. The ADC
converts analog data with sampling rates from about 10 kS/s
to 40 MS/s, with power consumption proportional to sampling
rate. The resulting Figure of Merit (FOM), for sampling rates 5–
40 MS/s, is 35–42 fJ/conv.-step, per ADC channel. Similar power
contribution is spent for fast data serialization and the largest
contribution goes to data transmission. A wide spectrum of static
and dynamic measurements confirm very good performance
of this multi-channel ADC with ENOB∼9.2 bits, an excellent
channel uniformity, and negligible crosstalk. The ADC works
asynchronously and so it is not limited to systems with uniform
time sampling. The ADC is designed using dynamic circuitry
which eliminates static power consumption (except leakage), as a
consequence it is ready for applications requiring power cycling.
Index Terms—Multi-channel ADC; SAR ADC; Ultra-low
power; Serialization; PLL.
I. I NTRODUCTION
W ITH the challenges for higher density and speed of
detectors in future particle physics experiments the
demand for fast ultra-low power multi-channel efficient read-
out systems is growing continuously. Such fast and efficient
signal processing is much easier when digitized signals are
available already in front-end Application Specific Integrated
Circuit (ASIC) and digital signal processing (DSP) can be
directly applied. This potential has not been used in the past
and existing experiments (except systems with binary readout)
because of huge power needed for Analog-to-Digital Converter
(ADC). Recently, with the availability of new smaller size
CMOS technologies and fast progress in ultra-low power
ADC architectures, it has become possible to overcome this
bottleneck [1]. Nowadays, it is feasible to design a front-end
readout chain comprising fast medium/high resolution ADC
per channel, in which the ADC power contribution is only a
small fraction of total power.
The multi-channel 10-bit ADC discussed in this paper is
being developed for the readout of luminosity detector (Lumi-
Cal) in the forward region [2] of future linear collider (ILC
Manuscript received 22 April 2016; Revised 11 July 2016
Authors are with the Faculty of Physics and Applied Computer
Science, AGH University of Science and Technology, e-mail:
Krzysztof.Swientek@agh.edu.pl.
This work was supported by Polish National Science Centre (NCN), grant
reference number DEC-2012/07/B/ST7/01456. The authors would also like to
thank the FCAL collaboration for encouragement and fruitful discussions.
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1
– International Linear Collider or CLIC – Compact LInear
Collider), replacing the previously developed digitizer in older
technology [3]. However, the architecture and parameters of
the ASIC do not limit its application to this detector. In fact,
the ADC may be used in any readout ASIC requiring similar
resolution and sampling rate. For the LumiCal an important
requirement is to have an ASIC operating in wide, power-
scalable sampling range. In the ILC detector implementation
a sampling rate of about 3 MS/s would be needed [4]. On
the other hand, for the beam-test runs, where the ILC-like
trigger is usually not available, a much higher 20–25 MS/s
rate is favorable, which allows to sample the shape of the
front-end pulse and then to perform its deconvolution [2].
Increasing the ADC sampling rate even further to 40 MS/s
one could extend its applicability to various Large Hadron
Collider (LHC) detector readout systems. In summary, the
ADC covering the sampling rate from single MS/s to 40 MS/s
can be of interest for various newly developed readout systems.
For the linear collider applications an important additional
requirement is to reduce as much as possible power dissipation
between beam trains, applying so called power cycling. Based
on the above considerations the main goal of this work was
to design an ultra-low power multi-channel 10-bit ADC with
sampling rate up to 40 MS/s and comprising the power cycling.
Depending on further processing another important feature,
which may be requested in multi-channel ADC readout, is an
efficient data serialization and a fast data transmission. These
issues are also studied and discussed in this paper.
The paper is organized in two main parts. In section two
the design of multi-channel ADC ASIC comprising a block
of ADC cores, a serialization circuitry, and a Scalable Low-
Voltage Signaling (SLVS) I/O interface, is presented. In the
third section the results of static and dynamic measurements
performed on the prototype ASICs, covering also various
multi-channel aspects like uniformity, crosstalk, or power
supply dependence, are presented. A comparison to other
works is also given in this section.
II. A RCHITECTURE AND D ESIGN
The developed multi-channel 10-bit ADC ASIC comprises
an ultra-low power 8-channel 10-bit ADC block, a fast se-
rializer based on dedicated Phase Locked Loop (PLL), and a
SLVS I/O interface. The present prototype contains eight ADC
channels, although the final goal is to obtain a higher ASIC
integration, comprising multi-channel analog front-end with
ADC conversion and possibly with further DSP functionalities,
in one System-on-Chip (SoC) readout ASIC. The final number
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Vcm
Vref
Bootstrapped
switches
32C
Vin+
Split 6b/3b DAC
Vin
32C
Sampling Vref
clock Vcm
Fig. 1. Architecture of 10-bit SAR ADC.
of channels should match the sensor segmentation, which
for the LumiCal, containing 64 sensor pads in a sector, will
most probably be 64. In this design no special attention was
given to radiation hardness aspects, although the 130 nm
CMOS process should allow significant radiation immunity.
The detailed radiation hardness studies will be done in the
future.
A. 10-bit ADC Channel Core
The ADCs performing successive approximations are
among the most popular due to their simplicity and a very
small number of mostly digital components. During last
decade the improvements in Successive Approximation Reg-
ister (SAR) ADC architecture have brought a continuous
increase of their speed (presently beyond 300 MS/s for a
10-bit ADC [5]) and a huge drop in dissipated power. As
discussed before, the latter is of crucial importance for future
high density detector readout systems, and for this reason the
SAR architecture has been chosen in this work.
The design and measurement results of the SAR ADC core
used in this work have been already presented in detail and
published [6]. Here we summarize only the main features.
The architecture of the implemented 10-bit ADC core is
shown in Fig. 1. The ADC comprises an input sampling
circuitry, a Digital to Analogue Converter (DAC), a compara-
tor, and a SAR control logic. A fully differential solution is
used to improve the immunity to digital cross-talk and other
disturbances. A capacitive DAC eliminates the static power
and achieves the lowest power consumption. For the same
reason all transistor-based circuitry is dynamic. In result the
ADC does not consume any power (except leakage) when
not converting and its power dissipation is proportional to
the sampling frequency. An asynchronous control logic is
implemented to eliminate the clock tree and to increase the
conversion speed. The asynchronous operation together with
the dynamic implementation enscan notures the power cycling.
To optimize the ADC speed a variable internal delay during
each bit processing was implemented. It can be set through
internal registers.
The ADC core occupies a 950 µm x 146 µm area. It was
verified [6] that the ADC core works properly for sampling
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Transactions on Nuclear Science
2
GND
Control signals
Dynamic
comparator
2C C 8C 2C 16C
Asynchronous,
2C 10-bit
dynamic
2C output
SAR logic
2C C 8C 2C 16C
GND
rates 0.01–40 MS/s, and in the range 10–30 MS/s it achieves
the Effective Number of Bits (ENOB) 9.2–9.35 and the Figure
of Merit (FOM) 34–37 fJ/conv.-step.
B. Serializer
To serialize the data from continuously running multi-
channel ADC, a multiple of the sampling clock is needed. In
commercial multi-channel ADCs a dedicated PLL is usually
used for this purpose. In the developed ASIC the PLL was
implemented but the serializer can be also configured to work
in different ways.
1) Serializer Architecture: The output data from multi-
channel ADC can be serialized and sent out in different ways,
according to the selected serializer mode.
• Single channel mode – in this mode a 10-bit data of the
selected channel is sent to ten parallel SLVS transmitters
with the sampling clock frequency and so the readout and
sampling frequency are the same.
• Parallel mode without PLL – in this mode the 10-bit data
of each channel is serialized and sent into a single SLVS
transmitter with an external readout clock 10-times faster
than the ADC sampling clock. The ADC sampling clock
is obtained by division of the external readout clock.
• Parallel mode with PLL – in this mode the 10-bit data
of each channel is serialized and sent into a single SLVS
transmitter with an internal readout clock 10-times faster
than the ADC sampling clock. The readout clock is
generated by an internal PLL which multiplies by ten
the ADC sampling clock.
• Serial mode without PLL – in this mode the 10-bit data
from eight channels is serialized and sent into a single
SLVS transmitter with the external readout clock 80-
times faster than the ADC sampling clock. The ADC
sampling clock is obtained by division of the external
readout clock.
• Serial mode with PLL – in this mode the 10-bit data from
eight channels is serialized and sent into a single SLVS
transmitter with the internal readout clock 80-times faster
than the ADC sampling clock. The ADC sampling clock
is obtained dividing by ten the external clock, while the
readout clock is generated by the internal PLL which
multiplies the external clock by eight.
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Transactions on Nuclear Science
3

In each mode the readout clock is used for synchronization Ref U

of the ADC data sent from the chip. Since the implemented PFD D
CP LPF
synchronous data transmission works up to about 400 MHz
the ADC operation in serial modes is limited to sampling AFMS VO

frequencies below 5 MHz. This mode would be interesting

VCO
for synchronous operation in a final ILC-like experimental
Div Clock
configuration, but since it cannot be used for higher sampling Divider
rates, it is not discussed in this paper. Also the single channel
Out
mode is not discussed because it is not in the scope of this
work. For standard operation it is assumed that the ASIC Fig. 3. PLL block diagram.
receives only the sampling clock and for this reason the default
mode of operation is the parallel mode with PLL. Only this
readout mode will be discussed in the following part of this counter can be configured for forward or reverse counting
work. while each LFSR counter can change the primitive polynomial
The block diagram of the parallel serialization with PLL is between 1+x3 +x10 and 1+x7 +x10 . In addition, the counters
shown in Fig. 2. The data are always sent out starting from in the first four channels start from a different value than in
the next four channels.
SLVS
10b 1b
Vin[0] SAR 0 serialiser 0 C. Fast Power-Efficient SLVS I/O
...
...
...

A fast power-efficient differential I/O interface is needed to

10b transmit the serialized high frequency ADC data. For a 1.2 V
Vin[4] SAR 4 serialiser 4
power supply of CMOS 130 nm process the successor of the
Vin[5] SAR 5 serialiser
1b
5
SLVS commonly accepted LVDS interface i.e. the SLVS was chosen.
...

...

...

For a transmitter, a modified architecture proposed in [9],

10b 1b
7 was used. The schematic diagram of the implemented SLVS
Vin[7] SAR 7 serialiser transmitter is shown in Fig. 4. Additional source followers
start_frame
ext_clk PLL readout_clk VDD
clk x10 vp Vbias2 vp Vbias2
MU M10 M7 M8

Fig. 2. Block diagram of multi-channel serialization.

selB sel
M3 M4
the most significant bit (MSB). Apart from the readout clock M5 M6
OUT+
OUT-

os
and eight SLVS data transmitters, an additional start f rame os
sel
M1 M2 selB M11 vn
Vbias1 SLVSref
SLVS transmitter is used, which is needed to mark the begin- M12
ning of the 10-bit ADC sample.
M9
2) PLL: The PLL used for serialization of the multi- vn
MD
channel ADC data was designed as a general purpose ultra-low VSS
power (< 1mW at 1 GHz) circuit, which can operate in a very
wide MHz–GHz frequency range. Figure 3 shows the block Fig. 4. Schematic diagram of SLVS transmitter.
diagram of the developed PLL. It consists of a Phase and
Frequency Detector (PFD), a Charge Pump (CP) with a Low M11, M12 were added to the original scheme to allow very
Pass Filter (LPF), a single-ended Voltage-Controlled Oscillator low (≤ 400 mV) common-mode voltage. Since the transmitter
(VCO), a clock divider, and an Automatic Frequency Mode is the most power-consuming block and 10 SLVS transmitters
Setting (AFMS) block. It can operate with different division are needed to transmit 8-channel data output, the SLVS power
factors but for the multi-channel ADC only divisions by consumption may be varied by changing its bias current. In
8 (serial mode) and 10 (parallel mode) are used. For data addition the common-mode voltage is controlled by an external
serialization the readout frequency range 10–400 MHz is used reference voltage SLV Sref .
in this work. The PLL operation was positively verified before For the SLVS receiver, a self-biasing amplifier configuration
its implementation in the multi-channel ADC ASIC. The proposed in [10] was implemented, as shown in Fig. 5. In
design and measurements of the prototype PLL are discussed default operating conditions the simulated power consumption
in detail in [7]. of the transmitter and receiver is about 2.1 mW and 0.6 mW
3) Testability: To verify the serializer itself and the digital respectively. Simulations showed that for standard 100 Ω
transmission a known pattern can be sent to the serializer input termination and small capacitive load (∼2pF), the transmitter-
instead of ADC data. Two types of 10 bit-wide pattern are receiver chain can work up to about 2 GHz.
generated by a dedicated binary or pseudo-random internal
counters. The pseudo-random counters are linear feedback D. ASIC Integration, Floorplan and Layout
shift registers (LFSR) avoiding a forbidden state [8]. To avoid The layout of the prototype ASIC is optimized for multi-
generation of the same data in each channel, each binary channel architecture and consequently the vertical size of

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VDD
bias
IN+ IN-
OUT
VSS
Fig. 5. Schematic diagram of SLVS receiver.
ASIC is driven by the chosen ADC pitch of 146 µm. The
146 µm pitch matches the size of differential input and output
SLVS pads. For the chosen pitch the resulting area of the 8-
channel ADC block is 950 µm x 1168 µm. The total area of
the ASIC, determined by number of channels and supply pads,
is 2000 µm x 2220 µm, giving 4.44 mm2 .
To allow detailed power consumption studies the ASIC
uses separate pads for various voltage domains and lines:
ADC analog (ADC ana), ADC digital (ADC dig), ADC
reference voltage (ADC V ref ), ADC common-mode volt-
age (ADC V cm), serializer and digital control (SER), PLL
(P LL), and SLVS I/O (SLV S). The analog and digital power
supply buses are distributed across the channels with multiple
bonding pads at both sides of the chip. All vertical buses
are tapped to the horizontal (along the channels) ones, which
distribute power supplies along each channel. To ensure a
stable power supply, a large area of decoupling capacitors
(of the order of nF ) based on gate oxide were provided,
particularly for the ADC reference voltage.
The layout of the ASIC is shown in Fig. 6. The eight
channels are seen on the left, while the large area on the
right side contains the digital part (serializer and control logic,
together with decoupling capacitors) and PLL. The SLVS
transmitter pads are placed on the right edge.
SLVS transmitters
PLL
SAR ADC
Serializer
8 channels
& slow
control
Fig. 6. Layout of prototype ASIC.
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4
III. M EASUREMENT R ESULTS
The prototype ASIC was fabricated in a 130 nm, eight-metal
CMOS technology. The results presented in this paper were
obtained doing a complete set of systematic measurements for
one prototype ASIC. In addition, a number of measurements
were performed for three other ASICs, giving practically the
same results. In one of these ASICs a single not functioning
channel was found. However, the statistics are too low to make
any conclusion about the yield.
The presented measurements were performed for ADC
working in the parallel serialization mode with PLL. Other
serialization modes were positively verified only qualitatively,
in particular the parallel serialization mode without PLL, to
check the ADC operation down to 10 kHz sampling frequency,
but they are not discussed here because this work is focused
on the fast ADC operation. All the measurements performed
at a given sampling frequency were done for the same settings
of internal delays in the ADC core. These delays were always
chosen in order to get the maximum ENOB value.
A. Test Setup
To verify the multi-channel ADC performance a dedicated
test setup based on a Field Programmable Gate Array (FPGA)
was developed. It is a modified version of the setup previously
used [3], [6] for similar measurements. For static measure-
ments a DC signal was delivered to the ADC inputs from the
Agilent B1500A Semiconductor Device Parameter Analyzer
and the 10-bit digital output was read out through differential
interface of Xilinx FPGA of the Genesys evaluation board
from Digilent. For dynamic measurements the Agilent 81150A
arbitrary waveform generator was used to deliver sine signal.
The ADC signal input range was set by ADC V ref value. To
facilitate current/voltage monitoring during the measurements,
all supply voltages were also delivered from the B1500A
Analyzer.
B. Static Measurements
The static measurements were performed at various sam-
pling frequencies and with differential input voltage ramped
from -1 V to 1 V. To reduce the noise influence, the measure-
ments were repeated several thousand times.
1) Uniformity of Gain and Offset: To compare the perfor-
mance of all ADC channels, the transfer curves (not shown
because of full overlapping) were measured for the same signal
sent to all ADC inputs. The gains and offsets calculated for
each channel of prototype ASIC are presented in histograms
shown in Fig. 7. The gain and offset spreads were estimated
to be about 0.2% and 1.5 LSB respectively, confirming very
good uniformity of ADC channels.
2) INL & DNL Measurements: The ADC static perfor-
mance is quantified with the integral (INL) and differential
(DNL) nonlinearity measurements. Both parameters are ob-
tained with the histogramming method [11]. An example of
typical INL, DNL distributions is shown in Fig. 8.
The maximum values of INL and DNL parameters in
function of sampling frequency are presented in Fig. 9.
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5

5 5 In the sampling frequency range up to 35 MHz the minimum

4 4 measured DNL is always better than -1 LSB and so no missing
codes are seen. The maximum observed DNL are around
entries

entries
3 3

2 2 1 LSB. The worst values appear only for few codes, when most
1 1 significant bits are changed (typical for SAR architecture). A
0 0
typical INL/DNL behavior can be better described by Root
433.75 434.25 434.75 435.25 435.75 506 508 510 512 514 516
Mean Square (RMS) value. The DN LRM S is about 0.25 LSB,
gain (LSB/V) offset (LSB)
while the IN LRM S is about 0.32 LSB.. The measured INL
Fig. 7. Histograms of gain and offset calculated from transfer curves (8 ADC in the sampling frequency range up to 35 MHz stays always
channels). between -1–1 LSB. At 40 MHz sampling the linearity starts
to deteriorate and the worst INL, DNL values exceed the -1–
1 1 LSB range. In fact, few missing codes per channel appear
0.5
often at 40 MHz sampling frequency for the codes close to
INL (LSB)

the transition points of the most significant ADC bits, meaning

0
that the time available to charge the capacitive DACs becomes
-0.5
too short for precise conversion.
-1
0 128 256 384 512 640 768 896 1k
It was verified that changing the internal delay settings of
Code (LSB) the ADC a better linearity could be obtained at a cost of worse
ENOB in dynamic measurements. For the presented results
1.5
such changes were not applied to keep the same settings for
1
both static and dynamic measurements.
DNL (LSB)

0.5
0
C. Dynamic Measurements
-0.5
-1 For the evaluation of dynamic circuit performance, Fast
0 128 256 384 512 640 768 896 1k
Code (LSB)
Fourier Transform (FFT) spectra were calculated from the
measurements done with a near full-scale sine input sig-
Fig. 8. Example of INL and DNL measured at 25 MHz sampling frequency nal [11]. The standard ADC metrics i.e. the Signal to Non Har-
for channel 3 and calculated using the histogramming method. monic Ratio (SNHR), the Total Harmonic Distortion (THD)
ratio, the Spurious Free Dynamic Range (SFDR) and the
ch0 ch2 ch4 ch6
ch1 ch3 ch5 ch7 Signal to Noise and Distortion Ratio (SINAD), were calculated
from the FFT spectrum. From these metrics the ENOB was
1.5
obtained. Since the measurements at high input signal fre-
1 quencies require significantly more effort (additional filtering),
systematic measurements for all ADC channels were done at
0.5 one fifth of Nyquist frequency, which is close to the mid-
INL (LSB)

band of a typical semi-gaussian shaper with peaking time

0
equal to the reciprocal of the sampling frequency. The ADC
-0.5 performance at higher input frequencies is also shown but only
for exemplary channels.
-1 1) Dynamic Metrics: An example set of all dynamic met-
rics (SNHR, THD, SFDR, SINAD, ENOB) measured as a
-1.5
1.5 function of sampling frequency, for input signal frequency
equal one fifth of Nyquist frequency (1/10th of sampling
1 frequency) is shown in Fig. 10. The ENOB is rather flat
0.5
and above 9.3 bits up to 30 MHz sampling frequency. For
higher frequencies it decreases and equals 9 at 40 MHz. The
DNL (LSB)

0 resolution is limited by noise (SNHR and SINAD overlap).

The dynamic performance of all channels of prototype
-0.5
ASIC is summarized in Fig. 11 where the ENOB (left) and
-1 SINAD (right) are shown versus sampling frequency. The main
conclusion from this plot is the same as from the example
-1.5 above – the ENOB is above 9.2 bits and rather flat up to
5 10 15 20 25 30 35 40
Sampling frequency (MHz)
30 MHz sampling, and starts to decrease slowly above this
frequency. In addition, a good uniformity between the channels
Fig. 9. Minimum and maximum INL and DNL values versus sampling is seen, only at 40 MHz sampling frequency the spread of the
frequency. results is slightly increased. To improve the static and dynamic
performance at 40 MHz additional design optimization would
be needed.

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13 80.0 number of supply lines is limited. For this reason the ADC
resolution was studied (for exemplary ADC channel) for
12 74.0 different power supply configurations. The ENOB and SINAD
results versus sampling frequency are shown in Fig. 13. The
11 68.0
ENOB

(dB)
SINAD(ENOB) SNHR
THD SFDR
9.4 58.35
10 62.0

9.2 57.14

9 55.9
9 55.94

SINAD (dB)
Separated

ENOB
8.8 ADC_ana+ADC_dig 54.74
8 49.9 ADC_ana+ADC_dig+ADC_Vref
0 5 10 15 20 25 30 35 40 ADC_all+SER
Sampling frequency (MHz) 8.6 53.53

8.4 52.33
Fig. 10. ADC dynamic performance of channel 6 as a function of sampling
frequency obtained with input signal frequency 1/10th of sampling frequency. 8.2 51.12

8 49.92
0 5 10 15 20 25 30 35 40
9.4 58.35 Sampling frequency (MHz)

9.2 57.14 Fig. 13. ENOB and SINAD for channel 3 measured for different configura-
tions of supply and reference voltage.
9 55.94
SINAD (dB)
ENOB

8.8 ch0 ch2 ch4 ch6 54.74 curve Separated is the reference corresponding to the already
ch1 ch3 ch5 ch7
8.6 53.53 presented measurements. The ADC ana + ADC dig curve
was obtained merging the analog and digital supply lines of the
8.4 52.33
ADC. For curve ADC ana + ADC dig + ADC V ref also
8.2 51.12 the reference voltage was connected together with analog and
8 49.92
digital power supply lines. To obtain the last ADC all+SER
0 5 10 15 20 25 30 35 40
curve not only the ADC power supply lines but also the digital
Sampling frequency (MHz)
ASIC supply (serializer and slow control) line was merged.
Fig. 11. ADC dynamic performance: ENOB and SINAD as a function It is seen that the configuration of power supply lines has
of sampling rate obtained with input signal frequency 1/10th of sampling almost no effect on the ENOB. Only when all supply lines
frequency.
are connected together the effect of the order of 0.05 LSB is
seen.
Figure 12 presents the ENOB and SINAD behavior as a To verify the robustness of the design and to check the
function of input frequency, measured for two channels at possibility of further power saving the sensitivity of ADC
25 MHz sampling frequency. The ENOB is above 9.2 bits and resolution to absolute power supply value was studied. In
Fig. 14 the ENOB and SINAD are presented versus supply
voltage for two exemplary channels at 10 MHz and 25 MHz
9.4 58.35 sampling frequency. Increasing the power supply from nom-
inal 1.2 V to 1.5 V practically does not change the ADC
9.2 57.14

9 55.94
SINAD (dB)
ENOB

8.8 ch3 54.74 9.4 58.35

ch6
8.6 53.53 9.2 57.14

8.4 52.33 9 55.94

SINAD (dB)

8.2 51.12 ch3 (fsmp 10MHz)

ENOB

8.8 ch6 (fsmp 10MHz) 54.74

ch3 (fsmp 25MHz)
8 49.92 ch6 (fsmp 25MHz)
8.6 53.53
0 2 4 6 8 10 12
Input frequency (MHz)
8.4 52.33

Fig. 12. ENOB and SINAD in function of input sine frequency at 25MHz 8.2 51.12
sampling frequency.
8 49.92
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
it is rather flat in the whole range. At Nyquist input frequency Supply (V)

it decreases to 9.1 bits.

Fig. 14. ENOB and SINAD versus supply voltage measured for channels 3
2) Power Supply Dependence: The measurements pre- and 6 at 10 MHz and 25 MHz sampling frequency. During measurements
sented in previous sections were done using separate voltage reference voltage was equal to power supply voltage and common-mode
source for each ASIC supply pad. In realistic system the voltage was kept at half power supply.

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performance. On the other hand, lowering the power supply 8 1

too much deteriorates its metrics, as one could expect. It is 7 ADC (total) 0.875
seen that for 25 MHz sampling frequency the power supply
6 0.75

Power per channel (mW)

may be lowered to 1 V without affecting the ENOB, while
for 10 MHz sampling good resolution is kept even at 0.8 V 5 0.625

Power (mW)
ADC_dig
power supply. In principle, lower power supply may be used 4 0.5
to minimize the power consumption, but this possibility is not 3 0.375
exploited in this work.
2 0.25
ADC_ana
1 0.125
D. Crosstalk Measurements ADC_Vcm
ADC_Vref
0 0
To study the crosstalk effect a sine signal was sent to 0 5 10 15 20 25 30 35 40
Sampling frequency (MHz)
one ADC channel and all channels outputs were measured.
Example results of such measurement are shown in Fig. 15 for Fig. 16. Power consumption of multi-channel ADC.
the cases with and without the signal on channel 2. It is seen
that for nearest neighbors the crosstalk signal is attenuated
more than by 70 dB and its effect is smaller than the noise one can place both the analog front-end and the ADC in each
seen in some other channels. Practically the crosstalk effect channel of readout ASIC, without affecting dramatically the
may be neglected. overall power consumption. Such solution will greatly simplify
further digital processing of experimental data.
60 2) Multi-Channel ADC with Serialization and Data Trans-
50 mission: The power contribution of main blocks of the ASIC
40 performing ADC conversion, serialization, and data transmis-
30 with sine sion, has also been verified. It was not the main objective
20
of this work but it was done to observe general trends and
RMS (dB)

10
draw basic conclusions on various contributions to the total
0
power consumption. In the case when DSP is applied directly
-10
-20
to the ADC data these considerations are less important. But
without sine
-30
even in such case, when the number of channels in readout
-40 ASIC will increase from 8 to 64 or more, the discussion about
-50 serialization scheme and data transmission will again become
0 1 2 3 4 5 6 7
channel
relevant.

Fig. 15. Measurement of crosstalk between ADC channels (sine on channel 2) 100 12.5
and ”raw” noise (all other channels on Vcm ) at 25 MHz sampling frequency.
SLVS at 150uA

10 SLVS at 50uA 1.2

Power per channel (mW)

E. Power Consumption
Power (mW)

To verify the power efficiency the power consumption was

studied first for the multi-channel ADC and in the second SER
step the consumption of the complete ASIC, comprising the 1 125.0m

serialization and data transmission, was measured.

ADC
1) Multi-Channel ADC Block: The ADC power consump-
tion is studied as a function of sampling frequency. The results
100m PLL 12.5m
obtained using separate supply lines for each ADC power
component are shown in Fig. 16 both for eight ADC channels
1 10
(left axis) and per channel (right axis). It is seen that each Sampling frequency (MHz)
power component as well as the total ADC power are directly
proportional to the sampling frequency. This was expected Fig. 17. Power consumption of prototype ASIC.
since one of the design objectives was to eliminate static power
and to scale the power consumption with sampling frequency. The measured power consumption of the ADC, the se-
It is also clearly seen that the dominant power contribution rializer, and the SLVS I/O versus sampling frequency is
comes from the ADC digital part. shown in Fig. 17. The ADC power is the sum of all ADC
Looking at absolute values it is seen that a single chan- components from Fig. 16. The serializer power was divided
nel, even at highest 40 MHz frequency, consumes less than into the automatically synthesized part comprising also slow
900 µW. This is very important result since it shows that in control (SER) and the dedicated custom made PLL. The SLVS
multi-channel implementation a fast ADC may consume less power consumption is shown at typical bias current (150 µA)
than an analog front-end. If so, as a next development step, and at the lowest bias current (50 µA) assuring correct data

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transmission. Since ten SLVS transmitters and one receiver
are needed for correct ASIC functionality the SLVS power
per channel is meant per one ADC channel (total power of 10
SLVS transmitters and one receiver was divided by eight).
For the serializer, the PLL contribution is negligible. The
fact that the automatically synthesized part (SER) saturates at
low frequencies is less relevant because it is due to leakage
current, mainly in the decoupling circuitry. This should be
modified in the next prototype. Important conclusion is that
the serialization power contribution is similar to the ADC
(for high sampling rates where leakage contribution is less
important). There is certainly significant power saving possible
since the serialization circuitry in the present prototype was
not optimized for power consumption, also because of many
serialization modes implemented. For fully power-efficient
serializer a dedicated custom design could be considered.
The dominant power contribution in Fig. 17 comes from
the SLVS I/O. It can be significantly decreased lowering the
SLVS transmitter current (SLVS curve for 50 µA) but even
then it stays dominant. Lowering SLVS transmitter current
may not be always a good solution because its effect will
strongly depend on the transmission media and external SLVS
receiver. In the presented setup the ASIC and FPGA (receiving
SLVS signals from ASIC) were placed on the same board what
was beneficial for the transmission. The main reason for high
power contribution is the number of transmitters (number of
ADC channels plus two). Instead of lowering the transmitter
current, a much more effective solution would be to decrease
the number of transmitters increasing the transmission speed.
Recently a new digital interface standard JESD204B [12] for
communication between data converters, FPGAs and ASICs
has been proposed. The JESD204B standard allows the maxi-
mum data rate up to 12.5 Gbps. With such interface all ADC
channels could be sent by one transmitter. But since it would
require a change of serialization scheme and I/O interface it
is not discussed in this work.
F. Figure of Merit
To estimate the power efficiency of the multi-channel ADC
one can calculate the most commonly used Walden FOM [13]:
P ower
F OM = SIN AD−1.76
2 6.02 · fsample
Originally the SINAD measured at Nyquist input signal fre-
quency was used in the above equation. Nevertheless, various
authors calculate the FOM for different input frequencies, in
particular for input frequencies corresponding to the applica-
tions for which the ADCs are designed. For this reason in
this work the FOM is calculated at one fifth of the Nyquist
frequency. The measured FOM per channel for the developed
multi-channel ADC is shown (ADC curve) in Fig. 18.
For the sampling frequency range 5–40 MHz the FOM is in
the range 35–42 fJ/conv.-step. This is an excellent result for
the design in 130 nm process, similar to the published State-
of-Art single channel ADCs [6], [14] with similar resolution
and sampling frequencies, and often using smaller CMOS
feature size. A small growth of FOM below 5 MHz is most
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600
400
ADC+SER+SLVS(150uA)
200
FOM (fJ/conv)
ADC+SER+SLVS(50uA)
100
80
60
ADC+SER
40 ADC
0 5 10 15 20 25 30 35 40
Sampling frequency (MHz)
Fig. 18. FOM per channel calculated for multi-channel ADC, ADC with se-
rialization, and ADC with serialization and SLVS interface (for two biasings).
probably due to the leakage current in the ADC power supply
decoupling.
In addition to the multi-channel ADC, the FOM was also
calculated adding to the ADC the power used for serialization
and SLVS I/O interface. These results are also presented in
Fig. 18 to give the reader an idea about the overall ASIC
efficiency. Again, it is clearly seen that the SLVS I/O inter-
face is the dominant factor. The optimization of total power
efficiency was not the objective of this work, nevertheless,
the complete ASIC FOM (ADC+SER+SLVS) of the order of
110–200 fJ/conv.-step is still comparable to good published
standalone ADCs.
G. Comparison with Other Multi-Channel ADCs
To the Authors knowledge there are not custom fast ultra-
low power multi-channel 10-bit ADCs working in detector
readouts of particle physics experiments. There are also very
few commercial multi-channel (≥8 channels) 10-bit ADCs
with sampling rates above 10 MS/s. In Table I four existing
commercial 8-channel ADCs (AD9212, ADS5287, MAX1434,
HMCAD1104) and one medium power 8-channel ADC ASIC
developed for LumiCal detector readout [3], with the same
resolution and similar sampling frequencies, are compared to
. (1) the presented work. Since commercial chips specify only the
total power consumption and not the one contributed by the
ADC, in addition to the ADC power consumption and FOM
(available only for 2 designs), the total power consumption
per channel and FOM per channel have been added, to give
the reader an idea about the overall power efficiency.
Except the presented design all compared chips use pipeline
architecture, which has been the most common choice, pro-
viding high speed and high resolution (ENOB, INL, DNL)
at acceptable power consumption. All these features are seen
in the presented pipeline ADCs. The most recent one, the
HMCAD1104 shows also very low power consumption. On
the other hand the SAR architecture has been always known
for its simplicity and very low power consumption. It is well
seen in the presented design. Unfortunately, for the commer-
cial chips the ADC power consumption is not available, but
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Transactions on Nuclear Science
9

TABLE I
C OMPARISON WITH OTHER MULTI - CHANNEL ADC S

Parameter This work [3] AD9212 ADS5287 MAX1434 HMCAD1104

Nr channels 8 8 8 8 8 8
Serialization per channel per channel per channel per channel per channel per channel
or per chipa or per chip
Architecture 10-bit SAR 10-bit pipeline 10-bit pipeline 10-bit pipeline 10-bit pipeline 10-bit pipeline
Technology 130 nm CMOS 0.35 µm CMOS - CMOS BiCMOS -
Power supply 1.2 V 3.3 V 1.8 V 3.3 VA , 1.8 VD 1.8 V 1.8 V
fsample (MS/s) 0.01–40 0.01–25 10–65 10–65 4.8–50 20–65
Input range 2 Vpp 2 Vpp 2 Vpp 2 Vpp 1.4 Vpp 2 Vpp
Area 4.44 mm2 8.2 mm2 9x9 mm2 9x9 mm2 14x14 mm2 9x9 mm2
(package) (package) (package) (package)
INLmax < ±1 LSB ±0.68 LSB ±1 LSB ±1 LSB ±1 LSB -
DNLmax ∼ ±1 LSB ±0.62 LSB ±0.65 LSB ±0.55 LSB ±0.5 LSB -
SINAD ∼57.5 dB ∼60.3 dB ≥60 dB ≥60.4 dB ≥60 dB >60 dB
ENOB ∼9.2@≤30MS/s 9.7 9.8 9.9 9.9 9.9
ADC power 0.87mW@40MS/s ∼20mW@25MS/s - - - -
per channel 0.67mW@30MS/s
F OMADC 35-42@5–40MS/s ∼960@25MS/s
(fJ/conv.-step) for fin = 0.2N yquist
Total power 3.1–4.7mW@40MS/sb ∼35mW@25MS/s 100mW@65MS/s 74mW@65MS/s 96mW@50MS/s 30mW@65MS/s
per channel 2.7-4.2mW@30MS/sb 68mW@40MS/s 46mW@30MS/s 20mW@40MS/s
F OMASIC 113–189@40MS/sb ∼1680@25MS/s ∼1720@65MS/s ∼1190@65MS/s ∼2000@50MS/s ∼480@65MS/s
(fJ/conv.-step) 114–201@30MS/sb ∼1900@40MS/s ∼1600@30MS/s ∼520@40MS/s
Tpower on 5–25 µs (PLL) ≤10 Tclk 375 µs 40–50 µs 100 ms >12 µs
0 (ADC)
Asynchronous operation Yes No No No No No
Internal reference No No Yes Yes Yes Yes
a Serialization per chip is not discussed in this work.
b Two values are obtained for 50 µA and 150 µA SLVS bias current.

comparing the F OMADC from [3] to the presented design,
a huge factor of about 25 is seen. This huge power saving is
the main motivation for using modern SAR architectures for
conversion in high density multi-channel readouts of particle
detectors. For applications with higher bandwidth of input
signal the obtained in this work F OMADC (measured at
0.2 Nyquist) may be underestimated. To estimate this effect
one can calculate F OMADC for 0.2, 0.5, and 1.0 Nyquist
input at 25 MHz sampling frequency from Fig. 12, getting
respectively 36, 38, and 41 fJ/conv.-step. Since in the presented
design the internal reference is not included, some additional
power would need to be added for fair comparison with the
commercial designs. Nevertheless, it was shown, that using
stable external power supply the additional reference is not
necessary.
In addition to power efficiency, the presented multi-channel
ADC ASIC comprises important features which are not or only
partially implemented in other designs:
• scalability of power with sampling rate over 3 orders
of magnitude (with PLL-based serializer the frequency
range is smaller 1–40 MHz);
• possibility of asynchronous operation which comes from
asynchronous SAR ADC architecture (when using the
PLL-based serializer this feature cannot be used);
• various serialization modes;
• very short Tpower on which is practically zero for the
ADC, since it uses fully dynamic circuitry, and 5–25µs
when the PLL-based serializer is used and the PLL is
switched off;
• small 146 µm pitch of ADC core which simplifies the
integration in a dense multi-channel readout system.
IV. C ONCLUSION
The design and measurements of a fast ultra-low power
10-bit multi-channel ADC, for applications in the readout of
particle physics detectors, are presented. The developed pro-
totype of 8-channel SAR ADC is fully functional and works
over a wide sampling frequency range 0.01–40 MHz. Its ultra-
low power consumption is reflected by an excellent FOM of
35–42 fJ/conv.-step/channel in the sampling frequency range
5–40 MHz. The performed measurements confirm good static
(INL<1 LSB, DNL∼1 LSB) and dynamic (SINAD ∼57.5 dB)
performance, which is reflected in a good ENOB of 9.2 bits. In
addition the developed ADC uses asynchronous logic and fully
dynamic circuitry what allows for direct application of power
cycling and asynchronous sampling, if needed. All mentioned
features make the ADC very flexible, allowing its use also as
a general purpose multi-channel ADC.
The developed multi-channel ADC is a key block of a
prototype ASIC comprising also a PLL-based serialization and
a fast SLVS I/O interface for data transmission. All presented
measurement results were obtained using the data serialized
per channel (at tenfold sampling frequency) and transmitted
by SLVS drivers to the FPGA-based acquisition system. It has
been shown that in such multi-channel ADC ASIC, comprising
the serialization and fast data transmission, the dominant
power contribution comes from the power hungry transmitters.
Nevertheless, the developed prototype dissipates per channel

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TNS.2016.2602391, IEEE
Transactions on Nuclear Science
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the least power among the existing multi-channel ADCs with

the same resolution and similar sampling rates.

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