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A 0.3V 0.705fJ/Conversion-step 10-bit SAR

ADC with Shifted Monotonic Switching
Procedure in 90nm CMOS
Sung-En Hsieh and Chih-Cheng Hsieh

 scheme that uses the top-plate sampling and level-shift

Abstract—This paper presents a 0.3V energy efficient 10-bit
successive approximation register (SAR) analog-to-digital
converter (ADC). A shifted monotonic switching (SMS) procedure
is proposed to achieve an average DAC switching energy of
63.75CV2. Two redundant bits are implemented with an error
tolerance of ±12mV for dynamic comparator offset and common-
mode reference (Vcm) sensitivity. The prototype is designed and
fabricated in 90nm CMOS with a core size of 250μm×50μm
(0.0125 mm2). At 250KS/s and Nyquist rate input, it consumes
52.3nW at 0.3V supply with an achieved SNDR of 51.21dB and a
resulting FoM of 0.705fJ/conv.-step.
Index Terms— low power, SAR ADC, switching power
I. INTRODUCTION
I NTERNET-OF-THINGS (IOT) applications demand a high
energy-efficient ADC with moderate resolution and speed.
The ultra-low power consumption and energy harvesting are
inevitable for system’s long-term operation. Recently, SAR
ADC shows a convincing low-power performance with the
advantage of technology evolution. Several SAR ADCs have
been reported with comparatively low FoMs by reducing the
switching energy of the power hungry capacitor array. The MS
[1] procedure uses the top-plate sampling without switching
any capacitor for MSB comparison. With an additional
reference voltage Vcm, the MCS reports a low switching
energy by reducing its reference voltage swing. The MMS [6]
shifts the entire capacitive DAC (CDAC) for MSB-1
comparison to omit the corresponding switching energy and
performs MCS for the rest of conversion. However, the MS and
MMS are vulnerable to the shift of common-mode voltage in
conversion phase because of the induced dynamic comparator
offset. By using the two-step ADC or split CDAC, the sub-
ranging [3], merge and split [4], and charge-average switching
[5] procedures demonstrated a convincing performance with a
low switching energy. However, due to the increased number
of capacitors and switches, these switching schemes need
complicated SAR control logics and consume more digital
power.
This paper proposes a shifted monotonic switching (SMS)
operations of CDAC for MSB and MSB-1 comparisons
respectively without any energy consumption. Moreover, a
combo switching scheme of MS and MCS concept is adopted
for the conversions of the rest bits to reduce the switching swing
and energy as well. As a result, SMS achieves an average
switching energy of 63.75CV2 with a reduction of 75%, 72%,
and 73% compared to the monotonic switching (MS) [1], sub-
ranging (SR) [3], and merge and split (MAS) switching [4]
procedures, respectively. The required CDAC bit size of SMS
is half compared to the conventional top-plate sampling scheme
with a resulting reduced logic implementation and power
consumption. Proper redundancy design is employed to tolerate
the dynamic comparator offset, comparator noise, Vcm
sensitivity, and settling error. Double-boosted sample-and-hold
circuit and body-driven switching are implemented for 0.3V
operation.
The rest of this paper is organized as follows, Section II
introduces the basic operation, noise, and dynamic offset of the
proposed switching procedure. Section III describes the circuit
implementation. The measurement results and comparison with
published works are provided in Section IV. Finally, the
conclusions are drawn in Section V.
II. PROPOSED ADC ARCHITECTURE
Fig. 1 shows the architecture of the proposed 10-bit SAR
ADC. The capacitive DAC is composed of an 8-bit main DAC
and a redundancy DAC (with an additional 40 LSB searching
range). With the proposed SMS and top-plate sampling
technique, 2(N-2)-bit DAC is implemented for N-bit conversion
which is only half compared to the conventional approaches
with 2(N-1)-bit DAC.
A. Shifted Monotonic switching procedure
Fig. 2. shows a 4-bit example of the proposed shifted
monotonic switching (SMS) procedure. It shows only a 2-bit
DAC is required for a 4-bit ADC conversion. In the sampling
phase, top-plate sampling operation is applied with all bottom
plates connected to Vcm. If the first comparison (MSB) result
is “1”, SMS performs a level-shift operation by switching all

The authors are with the Department of Electrical Engineering, National

Tsing-Hua University, Hsinchu 30013, Taiwan (e-mail:
shakesong@hotmail.com; cchsieh@ee.nthu.edu.tw).

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2605139, IEEE
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Fig. 1 Proposed SAR ADC architecture.

Fig. 2. (a) Monotonic Switching procedure. (b) Proposed Shifted Monotonic Switching procedure.

the bottom plates of N-DAC from Vcm to Vdd to create the

necessary -1/2 Vref shift, therefore, omitting the largest
consumed switching energy of MSB-1 comparison. If
comparison result is “0”, all the bottom plates of P-DAC are
then switched from Vcm to Vdd to create a 1/2 Vref shift on the
top plates. In the next comparison, if the comparison result is 1,
the 2C of P-DAC switches down from Vcm to Vss (MSB=1) or
Vdd to Vcm (MSB=0) correspondingly to create the required
voltage shift of -1/4Vref. On the contrary, with the comparison
result = 0, the 2C of N-DAC switches down from Vcm to Vss
(MSB=0) or Vdd to Vcm (MSB=1) for a 1/4Vref shift. The Fig. 3 Switching energy comparison.
same procedure is conducted until the last bit is converted. average switching energy of SMS is around 1/4 of MS due to
Fig. 3 shows the switching energy comparison based on the the reduction by half of the reference voltage swing (from Vdd
same total required capacitance of 10-bit ADC limited by kTC to 0.5Vdd). The average switching energy of SMS is
noise and matching performance. It shows the proposed SMS dramatically reduced compared to MCS since the switching
consumes an average switching energy of 63.75CV2, which is behavior is single ended rather than differential.
only 25%, 28%, 27%, and 75% of that of MS [1], SR [3], MAS
[4], and MMS [6], respectively. B. Dynamic comparator offset
After normalizing the total capacitance of CDAC to 512C, the MS, MMS, and the proposed SMS all have low switching

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2605139, IEEE
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Fig. 4 INL error with dynamic comparator offset.
Fig. 5 INL error with dynamic comparator offset after the insertion of
redundancy.
energy with the drawback of common-mode level shift during
the conversion. This common-mode level shift results in a
dynamic comparator offset and causes missing-code errors in a
binary-weighted SAR ADC operation without any error
tolerance. Assume that the offset is induced from a size
mismatch ΔW, the dynamic comparator offset voltage can be
expressed as [1]
Vgs  Vth W Vicom  Vth W
Voffset     (1)
2 W 2 W
which is related to the overdrive voltage (Vgs–Vth) defined by
the input common-mode level (Vicom=Vgs) and device
dimension mismatch (ΔW) of input pair. Fig. 4 shows the
MATLAB simulated integral non-linearity (INL) results of
SAR ADC with MS, MMS, and SMS procedures. The SMS
procedure shows the smallest INL error since the maximum
common-mode level (Vicom) shift is 1/4 Vref, which is only half
of that of MMS and MS (1/2 Vref).
Fig. 5 shows the simulated INL curves for MS, MMS, and
SMS schemes with corresponding redundancy insertions. In
SAR ADC operation, the common-mode level at the top plate
converges to Vfinal at the end of conversion and induces a
corresponding comparator dynamic offset Voffset=(Vfinal-
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Fig. 6 Differential voltage output of the first stage.
Fig. 7 Input common mode voltage and noise performance of comparator for
different conversion cycle.
Vth)/2×(ΔW/L)/(W/L). Since the Vfinal of MS and SMS schemes
are constant, the dynamic offset only shifts the transfer curve
by a fixed value, and the resulting non-linearity errors can be
solved by the proper redundancy insertion. Fig. 4 and 5 show
the resulting INL error and required redundancy range of SMS
are only half compared to that of MS. For MMS scheme, the
Vfinal is a signal-dependent value, causing a signal-dependent
error (Voffset) which cannot be compensated by the redundancy
insertion. Therefore, the SMS demonstrates a better dynamic-
offset-induced error tolerance property.
C. Noise performance
This work uses a conventional two-stage comparator [3] to
reduce the sensitivity to power supply and temperature. The
simulation results show the implemented comparator can
operate well under 0.3V±10% supply and 0~80oC temperature.
The noise performance of the two-stage comparator is still
sensitive to the input common-mode level (Vicom) during
conversion. Assume that the gain of the first stage is high
enough to dominate the total noise performance, which means
the noise of the second stage can be ignored. The gain of the
first stage can be modeled as
V T  g m C  Vthp  g m 2Vthp 2Vthp
    , (2)
Vin C I C Vgs  Vthn Vicom  Vthn
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Fig. 8 Digital output noise vs different differential input voltage
Fig. 9 INL with 10mV shift on Vcm
Fig. 10 proposed body driven switch
which is inversely proportional to the input common-mode
level (Vicom) as shown in Fig. 6. Therefore, due to the Vicom
shifting property, the comparator noise performance of SMS,
MS, and MMS procedure varies from cycle to cycle during the
conversion. Assume that the comparator noise is 0.5VLSB at
Vicom=0.5Vref, Fig. 7 shows the MATLAB simulated result of
Vicom and corresponding comparator noise in SMS, MS, and
MMS procedures at different conversion cycles. The proposed
SMS reports the most stable and lowest comparator noise with
a smallest Vicom shift during conversion. Fig. 8 shows the
standard deviation (STD) of ADC output code (in LSB) with a
rail-to-rail input and redundancy insertion in SMS, MS, and
MMS procedures. It shows the output STD is primarily
dominated by the input common-mode level at the end of
conversion phase (Vfinal). It shows the STD noise of ADC
output with SMS procedure is dramatically reduced compared
to that of MS and MMS.
D. Redundancy implementation
In SMS operation, the Vicom shifts up to 3/4Vdd after the first
switching and gradually converges down to 1/2Vdd (Vcm). The
induced 3-sigma dynamic offset of comparator is around ±2mV
with Monte-Carlo simulation. To cover a ±10mV on reference
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Fig. 11 Conventional layout implementation of capacitor array.
Fig. 12 Proposed new layout implementation of capacitor array.
Vcm variation and settling error, a redundancy of ± 12mV
searching range is implemented.
As shown in Fig. 1, two redundant bits are inserted on the
weightings of bit_rd[5] (32LSB) and bit_rd[3] (8LSB) to create
the additional searching range of 40LSB which is around
±12mV. Bit_rd[5] performs the split-switching procedure [7]
with two additional 4c to reduce the relative common-mode
shift further. Bit_rd[3] uses the MS procedure [1] with an
additional 2c. The MS and differential split-switching
procedure have 2 times of bottom plate swing compared to
SMS, therefore, the additional 10C achieves a total searching
range of 40LSB. The dynamic comparator offset from the
conversions after Bit_rd[3] is relatively small compared to VLSB
and can be ignored.
Fig. 9 shows the INL performance of the implemented ADC
with an intended 10mV offset of Vcm. The simulated and
measured INL both show an improvement from ±15LSB to be
less than ±0.6LSB by the implemented redundancy design.
III. CIRCUITS IMPLEMENTATION
A. Body driven switches
For 0.3V operation, a double-boosted sample-and-hold
circuit is applied for the linearity requirement. To accomplish
the proper switching of common-mode voltage Vcm, the body-
driven NMOS switches instead of local-boosting switches are
implemented for power reduction as shown in Fig. 10. By
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Fig. 13 Chip micrograph. (a)

connecting the control gate and body bias of NMOS together,
the effective threshold is reduced at “ON” state for a higher
speed and increased at “OFF” state for a lower leakage
adaptively.
B. Layout implementation of CDAC
Fig. 11 shows the conventional layout implementation of
CDAC. The gain loss caused by the top-plate parasitic
capacitance is (C2+C3)/(C1+C2+C3), which is around 13%
from the practices extraction. Fig. 12 shows the proposed
CDAC layout implementation. By using the bottom plates as a (b)
shielding layer, the gain loss from the fringing capacitor C2 is
omitted. The resulting gain loss becomes C3/(C1+C2+C3)
which is reduced to be 3% with a x4 improvement. The
available input swing increases by 11.5% and relaxes the noise
requirement of comparator and S/H (sample and hold) circuit.
The matching performance is also improved in the proposed
CDAC with shielding. As a result, the proposed work achieves (c)
the smallest DNL and INL as shown in the comparison table. Fig. 14 Measured (a) DNL/INL (b) Spectrum (c) SNDR versus input
frequency.
IV. MEASUREMENT RESULT TABLE I Performance summary and comparison
Ref. [3] [4] [8] This work
Fig. 13 shows the chip micrograph of the ADC prototype Tech. 40nm 90nm 90nm 90nm
fabricated in TSMC 90nm CMOS process with a core area of Fs(MS/s) 0.2 0.09 0.25 1 0.25 1
0.0125mm2 (250μm×50μm). Fig. 14(a) shows the measured VDD (V) 0.45 0.3 0.4 0.5 0.3 0.5
DNL and INL at 250KS/s and 0.3V supply, which are +0.198/- INL(LSB) 0.45 0.66 0.67 0.32 0.31
0.143 LSB and +0.320/-0.314 LSB, respectively. Fig. 14(b) DNL(LSB) 0.44 0.38 0.43 0.20 0.19
shows the measured FFT spectrum with an achieved SNDR of Area(mm2) 0.0065 0.031 0.0408 0.0125
51.21dB at 0.3V supply and 250KS/s sampling rate. Fig. 14(c) ENOB 8.95 8.38 8.63 8.75 8.21 8.65
shows a stable SNDR performance versus input frequency with Power(nW) 84 35 200 1200 52 475
supply voltages of 0.3V and 0.5V. At 250KS/s and Nyquist rate FoM(fJ/c-s) 0.85 1.17 2.02 2.77 0.705 1.18
input, the prototype consumes 52.3nW at 0.3V supply with a Taiwan under contract number MOST 104-2220-E-007-009
distribution of 3% for S/H, 20% for comparator, 35% for DAC, and 104-2221-E-007-103-MY3.
and 42% for digital control. The achieved ENOB is 8.21 and
resulting FoM is 0.705fJ/ conv.-step. At 1MS/s and 0.5V REFERENCES
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