IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO.
7, JULY 2011 407
A 400-nW 19.5-fJ/Conversion-Step 8-ENOB
80-kS/s SAR ADC in 0.18-μm CMOS
Jia Hao Cheong, Kok Lim Chan, Pradeep Basappa Khannur, Senior Member, IEEE,
Kei Tee Tiew, and Minkyu Je, Member, IEEE
Abstract—As the low-power-consumption requirement of inte-
grated circuits for biomedical applications (e.g., wearable sen-
sor nodes operating with and without batteries, and implantable
medical devices powered by batteries and wireless charging)
becomes more stringent, the data converter design evolves to-
ward mircrowatt and submircrowatt power consumption. In this
brief, a 400-nW successive approximation analog-to-digital con-
verter (SAR ADC) is presented. A trilevel switching scheme
with common-mode reset, redundant algorithm, and a time-
domain comparator is proposed and implemented to achieve ul-
tralow power consumption. The redundant algorithm mitigates
the offset error caused by the level mismatch of the trilevel
switching scheme, whereas the trilevel switching scheme simplifies
the switching logic of the redundant algorithm. Fabricated in
a 0.18-μm CMOS process, the proposed SAR ADC achieves a
signal-to-noise-and-distortion ratio of 50 dB, which is equivalent
to an 8-bit effective number of bits, at an 80-kS/s conversion rate.
The figure of merit is 19.5 fJ/conversion step.
Index Terms—Common-mode reset, redundant algorithm, suc-
cessive approximation analog-to-digital converter (SAR ADC),
time-domain comparator, trilevel switching, ultralow power.
I. I NTRODUCTION
T HE RECENT rapid advancement in medical science and
its application to actual patients’ life has urged the devel-
opment of advanced electronic medical devices and has driven
their power consumption to micropower level. Low-power
medical devices including wearable devices with battery oper-
ation usually consume power in the order of 100 μW to 1 mW,
whereas the micropower medical devices including implantable
medical devices with battery operation and wearable devices
with batteryless operation consume power in the order of 1 to
10 μW [1]. For micropower medical devices, it is necessary
to have data converters operate with a power consumption less
than 1 μW while providing a moderate performance adequate
for applications (e.g., sub-100-kS/s conversion rate and sub-
10-bit resolution typically), which will prolong the lifetime
Manuscript received November 16, 2010; revised February 21, 2011;
accepted April 10, 2011. Date of publication June 27, 2011; date of current
version July 20, 2011. This work was supported by Agency for Science,
Technology and Research, Science and Engineering Research Council
(A*STAR SERC) Grant Program under Grant 0921480069. This paper was
recommended by Associate Editor P. Mak.
J. H. Cheong, P. B. Khannur, K. T. Tiew, and M. Je are with the Institute of
Microelectronics, Singapore 117685 (e-mail: cheongjh@ime.a-star.edu.sg).
K. L. Chan was with the Institute of Microelectronics, Singapore 117685. He
is now with the Institute for Infocomm Research, Singapore 138632 (e-mail:
klchan@i2r.a-star.edu.sg).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2011.2158255
1549-7747/$26.00 © 2011 IEEE
of the implantable devices operating with batteries and enable
batteryless devices that acquire energy from the environment
using energy harvesting techniques. The successive approxi-
mation analog-to-digital converter (SAR ADC) is a suitable
solution for micropower medical devices due to its high energy
efficiency.
An energy-efficient 8-bit SAR ADC was reported in [2].
The ADC utilizes a single-ended structure with only one boot-
strapped switch to save power. It consumes 2.47 μW at a
200-kS/s conversion rate. Elzakker et al. developed a SAR
ADC with a 65-nm process that charges the capacitor array
in multiple steps [3]. The ADC achieves 10-bit resolution at a
1-MS/s conversion rate with a figure of merit (FOM) of only
4.4 fJ/conversion step while consuming 1.9 μW. Lee et al.
presented a SAR ADC that utilizes a time-domain comparator
to achieve low power consumption [4]. The ADC achieves
an 8.7-bit effective number of bits (ENOB) at a 100-kS/s
conversion rate while consuming 1.3-μW power. Several SAR
ADC designs have successfully reduced the ADC power to the
microwatt level. However, there is a need to reduce the power
further down to the submicrowatt level, which is essential for
micropower medical devices.
Chen et al. described a trilevel switching scheme that reduces
the power consumption by precharging the capacitors with a
third voltage level before decision making [5]. There are two
ways to precharge the capacitor arrays. One is by generating a
third voltage level, and it would necessitate a high-power low-
impedance buffer. The other way is by balancing the charge
between the two differential capacitor arrays. The third voltage
level generated in this way is subject to variation under long-
term operation when the charge from the previous conversion
is not completely discharged. Any inaccuracies in the third
voltage level can cause a level mismatch and an offset of the
SAR ADC.
In this brief, a SAR ADC that utilizes a common-mode re-
setting trilevel switching scheme with redundant algorithm and
a time-domain comparator is presented. The common-mode re-
setting trilevel switching scheme reduces the switching activity,
as well as the power consumed by each switching operation. A
generalized redundant algorithm is applied to accommodate the
conversion error and relax the settling requirement for the time-
domain comparator. Nonbinary SAR ADCs introduce redun-
dancy so that errors in the first few steps of the SAR algorithm
can be corrected at the later steps. Thus, with the nonbinary
redundant algorithm, the effect of the offset caused by the level
mismatch in trilevel switching scheme can be mitigated, and the
power consumption can be further reduced by allowing a slower
408 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 7, JULY 2011
Fig. 1. Architecture of the proposed SAR ADC with a trilevel switching scheme, a generalized nonbinary redundant algorithm, and a time-domain comparator.
Fig. 2. Common-mode resetting trilevel switching scheme.
settling. Typically, the capacitance weights of the capacitor
digital-to-analog converter (DAC) are chosen with a radix of
less than two [6]–[8]. However, using a generalized nonbinary
redundant algorithm, the radix restriction can be avoided, and
the circuit settling time can be further relaxed than those
using the radix-based nonbinary algorithm [9]. To implement
the generalized nonbinary redundant algorithm, the DAC must
be able to add or subtract in nonbinary steps. Although this
can be achieved by using digital adder and subtractor circuits
and read-only memory as in [6] and [7], such an approach is
not power efficient. In this work, the generalized nonbinary
redundant algorithm is optimally implemented by using the
trilevel switching scheme without any power penalty.
II. ADC A RCHITECTURE AND B UILDING B LOCKS
The proposed SAR ADC architecture is shown in Fig. 1. It
consists of a capacitor array, a switching array, a time-domain
comparator, and a switching logic.
A. Common-Mode Resetting Trilevel Switching Array
A common-mode resetting trilevel switching scheme is ap-
plied to the SAR ADC. During the sampling period, the pro-
posed scheme samples the input signal onto the top plates of the
Fig. 3. Trilevel switching scheme without using a third voltage level.
capacitor array, while the bottom plates are reset to Vcm , which
is equal to Vref /2, as shown in Fig. 2. By doing so, the first most
significant bit (MSB) can be determined during the sampling
period without an extra cycle for the MSB decision. As a
result, it saves one conversion cycle. Based on the previous bit
decision, the bottom plates of the following capacitor pairs will
be switched to either Vref _hi or Vref _lo , whereas the rest of the
differential capacitor pairs are connected to each other, creating
a virtual common-mode voltage Vcm (= Vref /2). Applying the
proposed trilevel switching scheme, an N -bit SAR ADC with
M redundant bits needs N + M capacitors, and it takes only
N + M cycles to complete the conversion. Although top-plate
sampling may be subject to charge injection, a fully differential
structure and complementary switches can be utilized to reduce
the effect.
In the ADC design, an additional voltage level would mean
an additional buffer in the system. The need of a low-impedance
buffer will significantly increase the overall ADC power con-
sumption. In order to avoid using a third voltage level, the
reference voltage can be designed in such a way that Vref _lo
is 0 V and Vref _hi is set to Vref , which is selected to be equal to
the input common-mode voltage Vin_cm , as shown in Fig. 3.
When the bottom plates of the capacitor arrays are connected
to Vref while the top plates sample the input voltage, the
CHEONG et al.: 400-nW 19.5-fJ/CONVERSION-STEP 8-ENOB 80-kS/s SAR ADC IN 0.18-μm CMOS 409

Fig. 4. Correction of the offset error using the redundant code algorithm. Fig. 5. Schematic of the time-domain comparator.

voltage stored on the capacitor array contains common-mode

and differential terms. As Vin_cm is equal to Vref , the common-
mode voltage stored on the capacitor arrays is zero. Only the
differential input voltage is stored.
After making the first MSB decision, the bottom plate of the
first pair of capacitors is switched to either Vref or 0 V. As
both capacitor arrays are identical, the charge redistribution will
create a virtual Vref /2 at the bottom plates of the rest of the
capacitors. The rest of the capacitors will switch from Vref /2
to Vref or 0 V at the bottom plate. Hence, there is no need to
generate a third voltage level.
Compared with the trilevel switching scheme used in [5],
the proposed method avoids the usage of an additional third
voltage level by resetting the bottom plate to Vref , which is
equal to Vin_cm , whereas in [5], the bottom plates are reset
by connecting them with their differential pair so that charge
sharing achieves voltage averaging. The trilevel switching
mechanism in [5] is also subject to voltage variation in the
Fig. 6. Block diagram of the switching logic.
long run if the charge stored in the capacitor array is not
completely discharged before resetting. On the other hand, by of the SAR ADC [6]–[9]. The redundant algorithm introduces
literally applying a voltage at the bottom plate during reset, the extra bits to correct the conversion error that occurs during the
proposed trilevel switching mechanism can avoid voltage vari- first few bits. It utilizes different step sizes instead of a standard
ation during a long-term circuit operation, which is particularly step size for each bit conversion. Thus, with the nonbinary
important for bio-implantable devices. With a full-range ramp redundant algorithm, the effect of the offset caused by the level
input, the trilevel based DAC is expected to have switching mismatch in the trilevel switching scheme can be overcome.
power that is five times smaller than the conventional DAC [5]. An example of a 5-bit six-step redundant algorithm is shown
in Fig. 4. When an offset error occurs, as shown in the figure,
wrong decision is made at the second stage. However, due to
B. Capacitor Array and Redundant Code
the redundant stage, the SAR ADC can correct the error and
Any inaccuracy in the resetting voltage of the trilevel switch- achieve the correct result at the final output.
ing mechanism will translate into an offset voltage. Hence, a Moreover, the application of the redundant algorithm can
nonbinary redundant algorithm is applied to the capacitor array relax the settling time requirement of the ADC. If the reduction
410 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 58, NO. 7, JULY 2011

Fig. 7. Die micrograph.

in the settling time is in greater effect than the increase in the

conversion steps and capacitors, the overall power consumption
of the SAR ADC can be reduced. The settling time of the
redundant SAR ADC per conversion step can be expressed as
 
p
Settling Time = τ × ln (1)
q

where p is the step size of the reference voltage change from the
previous bit, q is the redundancy in the corresponding step, and
τ is the time constant of the capacitor array [9]. By properly
selecting the redundant algorithm, the settling time of the
SAR ADC is optimized. In this implementation, one redundant
bit is utilized for the 10-bit ADC design. Through iterative
simulations, the optimum redundant code pattern was obtained
as Xi ∈ {238, 125, 68, 37, 20, 11, 5, 4, 2, 1}, where i = 10 : 1,
which gives the best settling time of 2.2τ for each conversion
step. One practical issue with the implementation of the capac-
itor array is the large area it occupies. To mitigate this problem,
two subarrays are used with an attenuating capacitor connecting
them. The attenuating capacitor can be calculated as [11]

(LSB-side subarray capacitances)
Catt = ×C (2)
CMSB_least − 1
where C is the unit capacitance and CMSB_least is the smallest
capacitor at the MSB side before conversion, which is 20C in
this case.
C. Time-Domain Comparator
A time-domain comparator developed in [4] is used to further
reduce the power consumption. As shown in Fig. 5, the time-
domain comparator is composed of five stages of voltage-
controlled delay circuits, which convert the voltage level to the
delay of the clock signal, and also a phase detector circuit,
which decides the logic according to the phase of the clock
signals. The sizing of the transistors in the delay circuits de-
termines the driving capability and the delay resolution of each
of the delay cell. It was shown that five-stage delay cells can
achieve a differential-mode sensitivity of 2 ns/mV with negligi-
Fig. 8. (a) Output spectrum, (b) DNL, and (c) INL plots of the SAR ADC
measured at a 80-kS/s conversion rate.
ble common-mode sensitivity [4]. The time-domain comparator
does not consume static power and is able to operate under low
supply voltage, which is very attractive for low-power designs.
D. Switching Logic
A switching logic design presented in [12] is used. As shown
in Fig. 6, the switching logic consists of a sequencer and a code
register. The sequencer is a shift register that shifts the set signal
through a series of D flip-flops. The set signal is then used to
activate the D flip-flops in the code register. When the last flip-
flop in the sequencer is turned on, it will reset the sequencer and
start a new conversion cycle.
III. M EASURED R ESULTS
A 10-bit redundant SAR ADC using the proposed common-
mode resetting trilevel switching scheme and time-domain
comparator was fabricated with a 0.18-μm CMOS process.
Fig. 7 shows the die micrograph. The SAR ADC occupies an
active area of 300 μm × 400 μm.
Fig. 8 shows the output spectrum and the differential and
integral nonlinearities (DNL/INL) of the ADC at an 80-kS/s
conversion rate. The ADC has DNL and INL that are less
than 0.7 and 1.5 least significant bits, respectively, at 10-bit
resolution.
Fig. 9 shows the signal-to-noise-and-distortion ratio
(SNDR), the spurious-free dynamic range (SFDR), and the
CHEONG et al.: 400-nW 19.5-fJ/CONVERSION-STEP 8-ENOB 80-kS/s SAR ADC IN 0.18-μm CMOS
Fig. 9. (a) SNDR/SFDR and (b) ENOB plots of the SAR ADC as a function
of input signal frequency measured at a 80-kS/s conversion rate.
TABLE I
P ERFORMANCE S UMMARY
ENOB of the ADC as a function of input frequency varied from
the direct current to the Nyquist frequency. At a 5-kHz input,
the ADC achieves an SNDR of 53.28 dB, which is equivalent
to an 8.6 ENOB, and an SFDR of 61.1 dB. The resolution
of the ADC drops to 7.1 bits at high frequencies, which is
due to the harmonics caused by the bonding wire inductance
to the package. The ENOB is larger than 8 bits up to the
20-kHz input signal frequency.
The SAR ADC consumes 400 nW at a 1-V supply, whereas
the time-domain comparator consumes 52% of the power,
the SAR logic consumes 23%, the capacitor array consumes
25.6%, and the rest is consumed by clock buffer. With such
low power consumption, an FOM of 19.5 fJ/conversion step
is achieved with input frequencies up to 20 kHz. Table I
summarizes the ADC performance.
411
TABLE II
C OMPARISON W ITH OTHER SAR ADC D ESIGNS
IV. C ONCLUSION
A 10-bit 80-kS/s SAR ADC has been designed and fabri-
cated with a 0.18-μm CMOS process. The ADC achieves an
ENOB of 8 bits up to the 20-kHz input while consuming only
400 nW. The ADC occupies 0.12 mm2 of the active area. The
ADC achieves an FOM of 19.5 fJ/conversion step up to the
20-kHz input frequency. Table II shows the comparison with
the recently published SAR ADCs.
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