15th international conference on Sciences and Techniques of Automatic control
& computer engineering - STA'2014, Hammamet, Tunisia, December 21-23, 2014
High-Performance 8-bit Modulator used for
Sigma-Delta Analog to Digital Converter
Radhouane LAAJIMI & Mohamed MASMOUDI
Abstract— Modulator is one of the most significant building-
blocks of analog Very Large Scale Integration (VLSI) used for
Sigma-Delta Analog to Digital Converter (ADC). For high-
performance analog circuit applications area and power
consumption are the most important parameters to determine
the performance of the modulator. Our design consumes only
1.16 mW of power at a supply voltage of 3V. Eventually the core
chip size of the modulator without bonding pads is 76 µm x 110
µm by using the AMS 0.35 µm CMOS technology.
Keywords— Analog-to-Digital conversion; Delta-Sigma
modulation; CMOS technology; low voltage; analog Design
I. INTRODUCTION
Mixed signal systems are systems that possess both analog
and digital subsystems. Such systems are prevalent in test and
measurement platforms, data acquisition systems, and
communications devices [1]. Thus, these mixed signal
systems are often central to hardware applications ranging
from common consumer products such as cellular telephones
to highly specialized real-time data collection systems used in
mission critical applications such as space flight [2].
In mixed signal systems, the conversion from analog to digital
is performed by an analog-to-digital converter (ADC).
Conversely, the conversion from digital to analog is
performed by a digital-to-analog converter (DAC). These
devices are mixed signal devices that allow for the ebb and
flow of information between the analog world and digital or
discrete-time systems which are now prevalent throughout
electrical applications. Because the performance of digital
systems can usually be improved by simple hardware or
software changes, the performance of a mixed signal system
is often limited by the performance of its data converters. As
a result, the performance of many mixed signal systems can
be improved by improving the system’s data converter
performance.
Department of Electrical Engineering
Electronics, Micro-technology and Communication (EMC) research group
Sfax (ENIS), BP W, 3038 Sfax Tunisia
(e-mail: radwene_fac@hotmail.fr)
978-1-4799-5907-5/14/$31.00 ©2014 IEEE
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STA'2014-PID3391-CEM
Many different ADC architectures exist and each architecture
has its own benefits and limitations. SIGMA-DELTA
modulators [3] are an ADC architecture that uses relatively
simple analog circuitry including a low order quantizer and a
feedback loop to sample analog signals with high signal to
noise ratios (SNRs) and large dynamic ranges (DRs). Because
of the simplicity of the architecture, SIGMA-DELTA
modulators [4] lend themselves to being implemented in
CMOS process technologies which offer mixed signal
electronics, low-power performance and high levels of
integration [5].
The paper is organized as follows. Section II presents
different architectures of SIGMA-DELTA modulators
composed of Nyquist rate converter and Oversampling
converter. In section III, we show Behavior analysis using
MATLAB/Simulink in order to describe the structure ΔΣ
modulator in our application. Then A complete design of
SIGMA-DELTA modulator with function schematic layout
and simulations are described using Cadence. Conclusions
with comparison table of most popular designs with current
work (Table IV) are drawn in Section IV.
II. ARCHITECTURE
Many different types of ADC architectures exist. Selecting
the.appropriate architecture for a given.application is often a
trade-off.between.size, power.consumption, .operational
bandwidth, conversion.latency, resolution, and sampling.rate.
For example, a Nyquist.rate converter’s resolution is.often
limited by its.inherent technology. However, system.design
methods which incorporate.signal processing techniques
such as.oversampling can increase.the effective resolution
of.a Nyquist rate converter by.reducing its operational
bandwidth. Pipelined ADCs.use subranging techniques
to.parse the sample conversion over.several iterations
thereby.improving conversion accuracy.
Typically, such architectures offer high resolutions over
reasonable operational bandwidths often without the need for
additional post-processing. However, the iterative conversion
process requires additional time thereby increasing
conversion latency. For moderate bandwidth applications,
specialized architectures such as SIGMA-DELTA
modulators are available [6]. Such architectures use feedback
and oversampling to achieve high resolution from relatively
simple, low power hardware.
A. Nyquist rate converter
Recall that Nyquist rate.converters are ADCs which.sample
the input at.or near its Nyquist rate (2.fb). .As such, the
sampling frequency. (fs) must be at.least twice the input.
signal’s Nyquist bandwidth. ( fb ). According to figure 1, in
order to minimize.out of band signal.energy from aliasing
into.the operational bandwidth of the.Nyquist rate converter,
the.input signal is typically.band limited to fs/2 by.an anti-
aliasing filter.prior to being sampled. .However, due to
practical.limitations of this anti-aliasing.filter, Nyquist
converters often sample.the input signal at.a frequency that is
slightly.higher than the Nyquist rate [7].
Nyquist converter bandwidths are.typically limited by the
electrical.properties of the fabrication.process in which they
are implemented. With current fabrication processes.capable
of supporting signal bandwidths.in the GHz range, Nyquist
converters.are capable of processing.band limited signals
with bandwidths.well in excess of 500 MHz [8]. As a result,
Nyquist converters.offer the widest range.of usable
bandwidth when compared.to other ADC architectures [9].
However, the effective resolution.of Nyquist converters is
typically.limited by achievable device density.and electronic
component matching. As device geometries decrease, the
inherent.mismatch of components increases.which limits the
converter’s.achievable resolution.

Spectral Density

Quantization noise
Figure 2. Flash ADC System Block Diagram Continuous

-fs/2 fs /2 Frequency B. Oversampling Converter

Figure 1. Spectral density for Nyquist Rate Converters
To illustrate, consider the B-bit Flash ADC in figure 2. Such
implementations require 2B - 1 comparators and 2B resistors.
Because the total area.required in an IC.to implement a
design.is proportional to the.overall device count
and.because the device count.of a B-bit Flash.ADC increases
exponentially with B, Flash ADCs with practical.dimensions
are limited to.a resolution of 8-bit.for current process
technologies. Also, Flash ADCs require components to be
matched perfectly to maintain uniform.quantization step
sizes. Because nominal components do.not match well over
large.device geometries, the effective.resolution of Flash
based.ADCs are typically less.than the ideal.
Oversampling ADCs are ADCs.which increase their
effective resolution.by sampling their input.signals at much
higher rates.than its Nyquist rate.and then band limiting.the
quantization noise to.the Nyquist bandwidth of.the input
signal. The ratio of the.sampling frequency (fs) to.the input
signal’s Nyquist.rate (2 × f0) is referred.to as the
oversampling-rate. (OSR) and it is.denoted as M.that
expressed as:
fs (eq 1)
M =
2 × f0
To illustrate, consider a Nyquist.ADC with a sampling
frequency. (fs) and an input.signal with a Nyquist.bandwidth
(f0 ). According to figure 3.the quantization noise is.spread
over a larger.frequency range in order.to reduce the spectral
density.of the quantization noise.

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 Spectral Density E

Qin
X Σ H(z) Σ

Quantization noise DAC

Figure 5. Linear model of conventional first order SIGMA-DELTA

Modulator

-fs/2 fs /2 Frequency According to figure 5, the linear model of conventional first

Figure 3. Spectral density for Oversampling Converters
order Sigma-Delta is presented [14]. This modulator has two
inputs: E(z) ,X(z) and only one output Y(z) which can be
Sigma-Delta ADC is a mixed signal.circuit block, which is expressed as :
suitable.for homodyne architecture. It comprise of an analog
block.of first order modulator.and digital block of.second Y ( z) = STF( z).X ( z) + NTF( z).E( z) (eq 4)
order decimator. Sigma-Delta modulation is widely.used in
the field.of analog to digital.conversion [7]. Sigma-Delta Where STF (z) is the signal transfer function and NTF (z) is
converters.combine an analog Sigma-Delta.modulator with a the noise transfer functions, which are given by:
more.complex digital filter.as shown in figure 4.
Y ( z) H ( z)
STF ( z ) = = (eq 5)
Digital X ( z) 1 + H ( z)
Analog Sigma
Signal Y ( z) 1
Signal Delta Decimator NTF ( z) = = (eq 6)
E ( z ) 1 + H ( z)
input Modulator output -1 -1
If we choose STF(z) equal to z and NTF(z) equal to 1-z
we obtain:
Figure 4. Block diagram of the Sigma-Delta ADC z −1
H ( z) = (eq 7)
1 − z −1
III. SIGMA-DELTA MODULATOR Note that loop-filter is simply an integrator which can be
In literature, many types of Sigma-Delta modulators [10] easily implemented with switched-capacitor techniques. For
second order SIGMA-DELTA modulator, the transfer
exist such as: continuous time, discrete time, multi-bit…
functions become:
The two most specifications to characterize the performance
[11] of Sigma-Delta Analogue to digital conversion (ADC)
are: Dynamic Range and Signal to Noise Ratio. STF( z) = z −2 (eq 8)
According to the design theory, the DR of a Sigma-Delta
modulator can be given by this formula: NTF ( z ) = (1 − z −1 ) 2 (eq 9)

⎡ 3 (2L +1) ⎤ In this case, the output signal for the ideal linear model can
DR(dB) =10log10⎢ 2L
OSR2L+1(2B −1)2 ⎥ (eq 2)
be written as:
⎣2 Π ⎦

The theoretical Dynamic Range (DR) is a function of the Y ( z ) = X ( z ). z − 2 + E ( z ).(1 − z − 1 ) 2 (eq 10)
Over Sampling Ratio (OSR), the number of bits and the
modulator order L. The characteristics of the proposed Sigma-Delta modulator
The maximum Signal to Noise Ratio (SNRp) is known by are shown in Table I. An 8-bit Sigma-Delta ADC for a signal
peak SNR. The SNRP of the Lth order SIGMA-DELTA [12, bandwidth of 80 KHz is designed with the decimation filter,
13] modulator can be calculated as : using MATLAB Simulink and then implemented using
Cadence.
3Π B OSR 2 L+1
SNRP = (2 − 1) 2 (2 L + 1)( ) (eq 3)
2 Π

TABLE I. THE CHARACTERISTICS OF SIGMA-DELTA ADC

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 Parameters Value From the frequency spectrum.of the output that Spurious.Free
Signal bandwidth (BW) 80 KHz Dynamic Range (SFDR) .which is the ratio.of the RMS value
Sampling Frequency (Fs) 10.24 MHz of.the input sine wave.for an ADC to.the RMS value of.the
Over sampling Ratio(OSR) 64 peak observed in.the frequency domain being 55.15 dB. It can
Modulator order 1 be concluded.from figure 7 that the resolution.of the
Number of bits in modulator 8-bit modulator was calculated from this expression:
Supply voltage 3V
SFDR − 1.76 (eq 11)
Technology AMS 0.35µm nb = = 8.86 bits
6.02
A. Behavior analysis using MATLAB/Simulink
In this paper, we built a first order Sigma-Delta modulator. 0

The most striking feature.of a SIGMA-DELTA.modulator -20

which is the main.component of Sigma-Delta.ADCs, is that

-40
these modulators use a.very high sampling rate. The Output X: 8e+004

S p e c tr e d e s o r tie ( d B )
Y: -55.15

sampling rate used.is very high frequency (~MHz) which.is Power -60
spectrum
much higher than.the Nyquist rate. Hence, the oversampling (dB) -80
ratio is very.high because of which.these are
sometimes.referred to as oversampling ADCs [15] [16]. The -100

advantage of using.this very high sampling.ratio is high -120

resolution.of the digital output.and better noise shaping.

-140
The Sigma-Delta modulation.was developed basing.upon
the well-established.delta modulation [10]. It consists of an -160
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Frequence (Hz) 5
integrator.and a comparator in the forward path.and a 1-bit Frequency (Hz) x 10

digital-to-analog converter (DAC) .in the feedback loop. In
this work, the functional diagram.of the first order modulator
was.simulated using MATLAB as shown in figure 6.
Figure 6. Block diagram of Sigma-Delta modulator using MATLAB
Figure 7. Output power spectrum using MATLAB/Simulink
B. Design of First order Sigma-Delta modulator using
Cadence
As shown in figure 8, by using CADENCE, the main
components.of a SIGMA-DELTA modulator are: an
integrator, Switchers, a D flip-flop , a comparator, a clock
generator and a source voltage of 1.5V. The difference of the
analog input.and the output of.the modulator, fed back to the
input through.a DAC is fed.to the integrator. The integrator
ramps up.or down depending.upon whether the difference
being.fed is positive or negative.

DAC
(Clock
Generator)

Switchers Integrator

Comparator

Source
Voltage 1.5V

Figure 8. Block diagram of Sigma-Delta modulator using CADENCE

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The output of the integrator.goes into a comparator. The
50
comparator produces.3V or 0V depending on.whether the
output of.the integrator is above.or below the threshold

P h a s e (d e g ), G a in (d B )
voltage.being compared by the comparator. The comparator’s
0
output is fed.to a D Flip-flop.which operates at a.very high
frequency (~MHz), which in turn.connects to a DAC.
The cores of the design of Sigma-Delta modulator are
-50
integrator and comparator, which are based on Operational
Transconductance Amplifier (OTA), as shown in figure 9 due
to its high open loop gain, high slew rate, large bandwidth,
-100
low power and small area.

100 1k 10k 100k 1M 10M 100M

Frequency (Hz)
Figure 10. Simulated output frequency response

All aspects of the Two-Stage OTA are indicated in table II.

TABLE II. DIFFERENTS PARAMETERS OF THE TWO-STAGE OTA

Parameters Value
Slew rate (SR) 0.2 V/µs
DC Offset 0.5 mV
Gain 60 dB
Gain bandwidth (GBW) 80 MHz
Cut-off frequency (fb) 95 KHz
Figure 9. Two-stage Miller OTA Phase margin (PM) 62 °
Supply voltage 3V
Settling time (St) 25 ns
The simulated output frequency response of Operational
Transconductance Amplifier (OTA) is shown in figure 10.
The bode diagram gives.a high open loop.gain of 60 dB.with
a large GBW.of 80 MHz, a 90 KHz of cut-off.frequency and
a phase margin of 62°.
Clock generator

Voltage
Source of 1,5V

Switchers Integrator Comparator

Figure 11. A layout of complete Sigma-Delta modulator

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Figure 11 shows a layout of a complete first order SIGMA- IV. CONCLUSION
DELTA modulator. It is made up of only one integrator, a From the simulations results and numerical analysis, it can
comparator, a source voltage 1.5V and a clock generator. be seen that the first order SIGMA-DELTA modulator can
These include switchers for.applying one of two.references work in a proper condition at a resolution of 8 bits and
node voltages.Vrefp and Vrefm, depending on comparator implement basic function as a converter. This device also
output.polarity. It is indicated that.the integrator and.the inherits the merits of the SIGMA-DELTA modulator. The
comparator are.based on the same amplifier. first-order modulator is designed at higher speed of 10.24
Here in this design, it is important to ensure.that the Spurious MHz, a signal band width of 80 KHz, an over sampling ratio
Free.Dynamic Range (SFDR) given.in (eq 11) is the same as of 64 and a maximum input signal 1V pulse to pulse. On the
shown in figure 12. other hand, the first-order modulator has many advantages
0
especially in stability and consummation. It is designed to
consume only 1.16 mW. According to table III, all main
-10
parameter are described.
-20

-30 TABLE III. DESIGNED MODULATOR PARAMETERS

Spectre de sortie (dB )

Output
Power -40 Parameters Value
spectrum
(dB) -50
Technology 0.35 µm AMS Technology
-60 Sampling Frequency (clock) 10.24 MHz
-70 Signal Band width 80 KHz
-80 Maximum Input 1 Vpp
-90 Supply voltage 3V
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Fréquence (X 10E7) Hz
Frequency Resolution 8-bit
(X10E7) Hz
Signal to Noise Ratio (SNR) 49.25 dB
Figure 12. Post-Layout output power spectrum of Sigma-Delta modulator Power consumption 1.162 mW
Area 76µm X 110µm = 8360µm²
According to figure 13, the SFDR is equal to 49.79 dB in
order to give a number of 8-bit which was calculated and
confirmed from this expression:

SFDR − 1.76 In order to give value of this work, we make a

nb = = 7.98 bits (eq 13) comparison between the current work with the most popular
6.02 published works as shown in table IV. It is indicated that this
0 work consumes less power than others works, and then it has
-10
small area. By using AMS 0.35µm at a supply voltage of 3V,
the resolution of first order Sigma-Delta modulator is not
-20
higher (8 bits). Moreover our design is characterised by
-30 higher speed and at the same time occupies a small area of
S p e c tre d e so rtie (d B )

Output
Power -40 0.008 mm2.
spectrum
(dB) -50

-60

-70

-80

-90
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
Fréquence (X 10E7) Hz
Frequency
(X10E7) Hz

Figure 13. Zoom of Post-Layout output power spectrum of Sigma-Delta

modulator

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 TABLE IV. COMPARISON TABLE OF MOST POPULAR DESIGNS WITH CURRENT WORK (*)
Resolution OSR SNR Speed Area Power Process Signal Order Ref.
(dB) (MHz) (mm2) (mW) (CMOS) Band width No.
14-bit 24 85 2.2 - 200 0.35µm 100 KHz 6 17
14-bit 96 85 53 - 15 0.18µm 300 KHz 2 18
8-bit 64 49.7 1.024 - 6.6 0.6µm 8 KHz 1 19
15-bit 128 - 1.024 1.68 3 0.35µm 4 4 20
14-bit 256 - 1 1.8 89.6 0.18µm 3.9 2 21
8-bit * 64 49.25 10.24 0.008 1.162 0.35µm 80 KHz 1 This Work

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