2020
International
Conference
on
Computational
Performance
Evaluation
(ComPE),

North-Eastern
Hill
University,
Shillong,
Meghalaya,
India.
July
2–4,
2020

A
Reconfigurable
Time
Multiplexed
Multichannel

ADC
.odel
for
&fficient
Data
Acquisition
Udeshna Hazarika Monalisa Das Kandarpa Kumar Sarma
Department of Electronics and Department of Electronics and Department of Electronics and
Communication Engineering, Communication Engineering, Communication Engineering,
Gauhati University Gauhati University Gauhati University
Guwahati, India Guwahati, India Guwahati, India
e-mail: uhazarika12@gmail.com e-mail: monalisadasece@gmail.com e-mail: kandarpaks@gauhati.ac.in

Abstract—Present days witnessed extensive use of Analog to
Digital Converters (ADC) in different fields of applications, as
an interface between the analog world and the digital world.
However, in most cases, external ADCs are employed to meet
the purpose. This eventually makes the system bulky, power-
consuming, complex, and costly. Implementation of reconfig-
urable ADC programmed inside Field-Programmable Gate Ar-
ray (FPGA) could reduce the system cost and power consumption
substantially. Furthermore, this will make the system simple as
it does not require any external circuitry for the conversion
of analog input data into digital form for processing. Thus,
in this paper, a multichannel reconfigurable ADC is designed,
with an additional feature of time multiplexing for efficient data
acquisition. The design is being implemented using 100MHz
FPGA clock frequency thus can achieve a sampling rate of 100
MS/s with a resolution of 10bit for 0-2.5V signal range. The
FPGA resource utilization for the complete ADC model consists
of 341 FFs and 265 LUTs, with total on-chip power consumption
of 14.428 W. The proposed system can also be implemented
for different analog signal from transducers, depending upon
the demand and requirement of sensing parameters the data
collection time can be varied for transducer to transducer.
Index Terms—reconfigurable, ADC, LVDS, TDC, FPGA, HDL
I. I NTRODUCTION
Analog to digital converter (ADC) is the linker between
real world parameters and the digital world. All natural phe-
nomenon/ parameters such as light, sound, etc. are analog.
Sensors that sense pressure, temperature, sound, etc. generate
output in analog form either in voltage or current. Dealing with
analog data for analysis, synthesis, transmission is complex,
power-consuming, expensive, and also noise can affect more,
which leads to data loss during transmission. In contrast to
the analog world, the modern digital world is easy to use, less
power requirement, easy to analysis and synthesis of data, also
cost-effective. Therefore, conversion of analog data into digital
form is much-needed practice for processing the real world
data required for different applications. ADCs are extensively
used in different fields such as safety and security, healthcare,
different sensory systems, industrial control systems, higher
energy physics experiments, etc. Devices used in such appli-
cations mainly comprises of two parts- analog part used to
collects the sensing parameters and digital part that analyzes
the data and reacts accordingly. ADC thus plays a prime role
in today’s data acquisition systems [1]. The traditional way of
dealing with analog and digital systems is to use an external
device to convert the signal from analog to digital form, which
eventually leads to system bulkiness and cost ineffectiveness,
with the increase in the number of analog input channels.
Presently, mixed signal components (ADCs) are commonly
modeled and designed using analog approach. Based on the
applications and requirements, generally, ADCs can be mod-
eled into Flash-type, Sigma-Delta, Successive Approximation
Register (SAR) type, and Pipelined-SAR type. Such compo-
nents are then designed into chips of particular specifications
as required. Such ADC chips are connected off-chip with the
processing block (Microprocessor or FPGA) for further appli-
cations, thereby increasing system bulkiness and cost of the
entire system. In contrast to this, there is another novel digital
ADC design model [2] that facilitates the implementation of
such mixed signal components inside the FPGA itself. Digital
integration and synthesis of such mixed signal components
acquire every benefit of digital design than its analog counter-
parts, such as noise reduction, power consumption, and area.
Apart from this, it also produces an efficient system in terms of
scalability, flexibility, and compactness. Integration of an ADC
in FPGA, either ASIC ADC on-chip or a reconfigurable ADC,
is a promising approach. This would provide advantages such
as having the analog data directly inside the FPGAs, leading
to faster processing of digitized data, without the requirement
of extra power supply, and extra off-chip circuitry.
In this paper, we propose a multichannel digital ADC design
model for integration inside the FPGA that can be reconfigured
as per specification requirement. The proposed system can take
multiple data from multiple sources. Depending upon data
rate and requirement, the time allocation for different input
channels can be programmed, making the model an efficient
block for data acquisition.
The rest of the paper is organized as follows. In section II,
a brief survey on the related works is presented, followed by
a detailed explanation of the proposed model in Section III.
The results and discussions are presented in Section IV, and
finally, Section IV concludes the paper.

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 II. L ITERATURE R EVIEW
ADCs are used in numerous applications, and each ap-
plication demands their own sets of requirements. However,
designing an ADC for reconfigurable devices though it has
own benefits; its design is itself a tedious task. Different
researchers have implemented different models to accomplish
the challenge. In general design of fully digital ADC involves
the use of an LVDS (Low-Voltage Differential Signaling) pin
pair for receiving analog inputs, passive components such as
few resistors and few capacitors, and the associated conversion
logic block implemented using different logics. Besides these,
a technical article [3] gives a brief description of the existing
methods and implementation of such ADC designed in FPGA
or CPLD (Complex programmable logic device) platform. Im-
plementing a time to digital converter (TDC) in reconfigurable
devices is another method to design an efficient ADC. Various
TDC architectures are employed to meet the requirement. Favi
et al. [4] have proposed an architecture that uses the traditional
concept of combination of counters fed by successive buffered
delay lines at each level. Another approach is proposed by
Chao et al. [5], using ring oscillators to design a TDC. A
combination of both buffered delay line and ring oscillators
architecture is being implemented by Van et al. [6].
Using this TDC concept ADCs are designed for reconfig-
urable devices. In the paper [7] wen et al. demonstrated the
technique of integration of DAC and ADC chips into FPGA.
Without interfacing special DAC or ADC chips into FPGA, the
conversion of analog to digital signal and vice versa was done
using PWM principle in the FPGA itself. In the paper [8], Hooi
et al. proposed a configurable 2 bit per cycle SAR-ADC for
FPGA implementation to improve speed and reduce size and
cost. Three comparators are used to design the ADC so that
2 bits can be converted at a time. This reduces the conversion
time to half. Homulle et al. [9] proposed a reconfigurable ADC
architecture design implemented in FPGA. In order to achieve
the sampling rate higher than the clock frequency time-to-
digital converters (TDCs) and phase interpolation techniques
have been utilized. Out of these architectures, TDC imple-
mentation in FPGA using delay line generation at each level
provides far better conversion results, with better efficiency.
Nevertheless, for multichannel ADC implementation, paper
[10] proposes an architecture that requires ‘n’ number of
TDC blocks, ‘n’ number of clock management blocks, and
‘n’ passive components; for ‘n’ channel analog input. This
ultimately increases the overall area overhead of the entire
data acquisition system.
Thus in this paper, an approach is being made to optimize
the area utilization, with an additional advantage of saving the
channel bandwidth with a simple multiplexing technique.
III. P ROPOSED W ORK
The block diagram of the proposed multichannel time-
multiplexed ADC design is shown in Fig.1. The essential
functional blocks of the proposed ADC model consist of an
LVDS buffer, TDC, MUX, and a clock. The LVDS is acting
as a comparator.
These blocks are designed as a module and implemented
inside the FPGA. However, externally a resistor ‘R’ of 100
Ω is connected to the clock signal to generate a ramp signal
as input ‘Vref’ to the non-inverting terminal of the LVDS
blocks. The inverting input is fed with the analog signal that
may come from any real time signals or sensor outputs. In
this paper, a multichannel ADC is proposed using two sensors
data as input (presently using LM35 temperature sensor). The
output of the LVDS comparator is fed to the MUX block that
sends the required analog input to the TDC block, depending
upon the select line logic.
Fig. 1: Block diagram representation of proposed multichannel
ADC
The TDC block is the main building block that contains the
conversion logic for the ADC. It is fed with the ‘stop’ and
‘start’ signal, coming from the clock buffer and MUX output,
respectively. This finally generates the digital output of the
proposed ADC model. The CLK signal used is the system
clock of the FPGA board, which is 100 MHz. Thus, having a
conversion speed of 100 MS/s with a resolution of 10 bit for
an input signal range 0 - 2.5 V.
The description of each block is detailed below:
A. Comparator (using LVDS signalling)
LVDS compares the input analog voltage and the reference
voltage. When the reference voltage is higher than the input
voltage, the LVDS generates logic ‘1’. When the reference
voltage is lower than the input voltage, then the LVDS pro-
duces logic ‘0’ as output. The time interval between ‘0’→’1’
or ‘1’→’0’ caused by LVDS and next rising edge of the clock
is measured by the TDC for conversion, which is followed by
the MUX block [Fig. 1].
An important to note here is that the main intention behind
using LVDS comparator for feeding analog signals is that,
FPGA being a digital device, does not support direct analog
input signals. So, to solve this issue, a differential signaling
voltage is used as input to the FPGA, which supports a good
range of differential inputs.
B. Clock Buffer
The clock buffer is a simple block used for generating a
reference ramp signal (Vref) for comparison with the analog

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input signal. The ramp signal is generated using the inverted
clock input passed through an external resistor (R). The input
clock signal used here is the 100 MHz system clock input of
the FPGA.
Fig. 2: Reference input to the LVDS depending upon clock
signal
C. Multiplexer (MUX)
The output of the LVDS comparator is fed to the MUX
block that sends the required analog input to the TDC block,
depending upon the select line logic. In this paper, a 2:1 MUX
is implemented to obtain the logic. However, for ‘n’ number
of analog sensors connected, n:1 MUX can be implemented
to obtain the logic. This saves channel bandwidth and also
reduces the area overhead of the entire data acquisition system.
D. Time to Digital Converters(TDC)
The TDC block is the main building block that contains the
conversion logic for the ADC. It is fed with the ‘stop’ and
‘start’ signal, coming from the clock buffer and MUX output,
respectively.Though there are number of different architecture
to implement the TDC logic, using the buffered delay line
concept is the most simple and easy to implement. The TDC
model implemented in this paper, and its timing diagram is
shown in Fig. 3.
The start signal is generated by the LVDS comparator
selected by the MUX block, while the stop signal is nothing
but the 100 MHz clock signal itself. The start signal indicates
the starting of the count and stops when a stop signal is
received. The TDC measures the time (in seconds) from the
start signal’s rising edge to stop signal’s rising edge. This is
clearly shown in Fig. 3(b)
A counter is also utilized in the TDC block, using series
connected buffered delay line sampled at each level, to control
the start and stop signal logic. This is then again connected
to a basic 10 bit binary counter. The 10 bit binary counter
is realized using series connected flip-flops arrangement. Its
work is to count the time the output remained HIGH, and
accordingly generate its digital output. The final digital output
can be expressed mathematically as given in Eq. 1,
Digital output = tstart + tcounter − tstop
For simultaneous multichannel output of all the sensor
inputs, a memory buffer is also implemented inside this block
that has the ability to store all the converted digital output and
display simultaneously when required.
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Fig. 3: (a)Architecture of proposed TDC, (b)Timing diagram
of proposed TDC
IV. R ESULTS AND D ISCUSSION
The hardware implementation of the proposed fully digital
ADC design is implemented in a 100 MHz, Zedboard ZC702
FPGA board using Hardware Description Language (HDL).
The software platform used is Vivado 2015.3.
A. ADC Parameters
The ADC parameters of the proposed design are:
1) Conversion Rate: It defines the number of repetitive
conversions per unit time for full-scale change. It is basically
the fastest sampling ability of the ADC. For a system clock
frequency of 100 MHz, the Conversion Rate of the proposed
design is 100 MS/s.
2) Analog Resolution: It determines the ability of how
small an analog input can be resolved. The formula for analog
resolution can be expressed as given Eq.2.
Analog Resolution = Analog Span / (2n − 1) (2)
Where, Analog Span is the range of the analog input
voltage, and ‘n’ is the number of output binary bits ‘word.’ The
calculated value of analog resolution for the proposed design
is obtained to be 2.44 mV.
(1)
B. Power Utilization
The total on-chip power consumption of the entire ADC
architecture consumes 14.428 W. Power consumption details
each of static and dynamic logic are shown in Fig. 4.
811
 100MS/s with an analog resolution of 2.44mV. The simulta-
neous use of two sensors has been demonstrated successfully.
However, the number of sensor inputs can be increased as
per the requirement for different sensing applications. As the
proposed ADC is reconfigurable, use it for different sensing
applications with different data rate would be easy. It is
envisioned that the proposed technique would emerge as a
promising technique for modern data acquisition system in
the field of Biomedical, Bioelectronics, and different sensing
platforms.
Fig. 4: Power utilization of the designed system
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Fig. 6: Image of the hardware prototype

V. C ONCLUSION
Herein a simple, reconfigurable multichannel ADC has been
proposed. The designed ADC has data conversion rate of

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