PVT-Invariant Single-to-Differential Data Converter
with Minimum Skew and Duty-Ratio Distortion
Youn-Sik Park1,2, Sung-Wook Lee1, Bai-Sun Kong1
1 2
School of Information and Communication Engineering,
Sungkyunkwan University,
Suwon, Korea
E-mail: parkave@samsung.com
Abstract— This paper proposes PVT-invariant single-to-
differential signal converter (SDC) applicable to the output
circuitry of high-speed DDR SDRAM. The proposed SDC
generates PVT-invariant differential-output sampling clock
using a phase interpolation technique and a symmetric
structure, and improves the aperture window of output data in
source synchronous DDR SDRAM. The proposed SDC was
simulated using 1.8-V 80-nm DRAM technology. The
comparison result indicates that the differential clocks
generated by the proposed SDC achieve 80.6% reduction of
skew, 76.6% reduction of duty-cycle distortion, 61.7% of
reduction of delay variation, and 8.5% reduction of maximum
current for a given process, voltage, and temperature (PVT)
variations, as compared to conventional SDCs. The I/O interface
of a source-synchronous DDR SDRAM designed using the
proposed SDC, which is operating at 1.0-Gbps/pin data rate has
aperture window increased by 15.3% and ISI improved by
67.7% in comparison to conventional I/O interface.
I. INTRODUCTION
Source-synchronous DDR SDRAMs usually have a
conversion scheme to convert its internal parallel data into
serial output data by sampling the internal data at both the
rising and falling edges of a synchronization signal [1]. In an
I/O interface for source-synchronous DDR SDRAM operating
at more than 1.0 Gbps data rate, the timing margin for fetching
the data from SDRAM becomes narrow since the output has a
narrow aperture window. This narrowing is usually due to the
skew and duty cycle distortion of the differential clock used
by the interface. For solving this problem, the quality of
differential sampling clock affecting the duty cycle of data
output is very important. However, the operation of
conventional single input-to-differential output converters is
very sensitive to variations on process, voltage, temperature
(PVT) [2], [3]. This paper proposes a novel single input-to-
differential data converter (SDC) that is configured as a
symmetric structure and employs a phase interpolation
technique for providing PVT variation-insensitive operation.
Youn-Sik Park studies on a scholarship from Samsung electronics Co., LTD.
This work was supported by Samsung electronics Co., LTD.
978-1-4244-1684-4/08/$25.00 ©2008 IEEE
Kwang-Il Park2, Jeong-Don Ihm2, Joo-Sun Choi2,
Young-Hyun Jun2
DRAM Design Team, Semiconductor Business,
Samsung Electronics Co., Ltd.,
Hwasung, Korea
II. SINGLE -TO-DIFFERENTIAL DATA CONVERTERS
A. Conventional SDCs
Figure 1 shows the conventional single-to-differential
signal converters (SDCs) that are used to generate fully
differential clocks (CKO and CKOB) from a single-phase
clock (CKI). The inverter-typed SDC is shown in Figure 1-(a),
in which two inverter stages are arranged along the in-phase
path and three inverter stages are arranged along the out-of-
phase path [2]. To minimize the difference of the propagation
delays of two paths, different structures of inverters with
different sizes were used, as shown in the figure. But, the
inverter-typed SDC was not suitable for high-speed operation
because of slow transitions of middle node (X) in the in-phase
path, a large amount of short-circuit current in output driver
stage, and a large sensitivity to PVT variations.
G
G
(a) (b)
Figure 1. Conventional single-to-differential signal converters (SDCs) : (a)
inverter-typed SDC, (b) transmission gate-typed SDC.
To compensate these shortcomings, a transmission gate-
typed SDC was proposed [3]. As shown in Figure 1-(b), to
provide the same number of MOS gates on each path,
transmission gate was inserted on the in-phase path. To
compensate slow transitions of middle node (X) caused by the
insertion of transmission gate, a buffer that uses NMOS
transistor for pull-up and PMOS transistor for pull-down was
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added. But, asymmetric structure here also resulted in signal skew and duty cycle distortion on the output. In case of the
skew and duty cycle distortion due to PVT variations. simulated waveforms of the proposed SDC shown Figure 3-
(c), middle nodes (X, Y) have full swing, reducing the signal
B. Proposed SDC skew and duty cycle distortion on output node.
The proposed single-to-differential signal converter (SDC)
shown in Figure 2 is configured as a fully symmetrical
structure and employs phase interpolation technique. The
proposed SDC receives single-phase input clock (CKI), and
generates in-phase and out-of-phase output clocks (CKO,
CKOB). The in-phase and out-of-phase paths of the proposed
SDC have the same structure to each other since the outputs of (a)
single-stage inverter and two-stage inverter in each path are
interpolated together.

(b)

(c)
Figure 3. Waveforms of SDCs: (a) conventional inverter-typed SDC, (b)
G conventional transmission gate-typed SDC, (c) the proposed SDC.
Figure 2. Proposed SDC.

When CKI transitions high, node X begins a pull-up

transition toward VDD-VTN by the NMOS transistor of buffer B.
After the input inverter delay, CKIB transitions low, and then,
the PMOS transistor of buffer A helps X to be pulled up to full
VDD. So, the waveform on X is the result of the interpolation
between waveforms of buffer A and B. At the same time, node
Y begins a pull-down transition toward VSS by the NMOS (a)
transistor of buffer C. After CKIB transitions low, the PMOS
transistor of buffer D helps Y to be pulled down to VSS+|VTP|.
So, the waveform on Y is the result of interpolation between
waveforms of buffer C and D. The same phase interpolation
occurs when CKI transitions low. During these transitions, the
signal slopes of X and Y are made to be symmetrical by the
cross-coupled inverters connected between these nodes [4].
Therefore, the proposed SDC can minimize the skew between (b)
differential clocks and duty-cycle distortion of each output
clock caused by PVT variation, resulting in improved
electrical characteristics.

C. Comparison Results
To verify the performance, the proposed SDC was
designed using 1.8-V 80-nm DRAM technology. HSPICE
simulation for the proposed and conventional SDCs was done (c)
with clock cycle time of 2.0ns at 35 process corners reflecting
the variations of voltage, process, temperature and input
clock slope. Figure 3 shows that the simulated waveforms of
middle node (X, Y) and output node (CKO, CKOB) of each
SDCs for the worst simulation corner (operating
voltage=1,1V, process parameter=slow, temperature= −10°C,
input clock slope=500ps). Figure 3-(a) and (b) show the
simulated waveforms of the conventional inverter-typed SDC (d)
and transmission gate-typed SDC, which shows partial swing Figure 4. Comparison of SDC characteristics: (a) signal skew, (b) signal
at middle nodes (X, Y). This behavior can increase signal duty, (c) propagetion delay, (d) average currnet consumption.

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 Figure 4 shows the performance comparison of SDCs in
terms of signal skew, duty variation, delay variation, and the
variation of average current for all possible conditions on
voltage, process, temperature, and input clock slope. The
simulation results indicate that the proposed SDC provides a
reduced amount of skew and duty-cycle variation, and it has
smaller propagation delay and average current consumption
than conventional SDCs. That is, the amount of skew was
reduced from 139ps to 27ps (80.6%), the duty variation was
decreased from 470ps to 110ps (76.6%), the variation of the
propagation delay was decreased from 379ps to 145ps
(61.7%), and the maximum average current consumption was
decreased from 0.47mA to 0.43mA (8.5%) in comparison to
the conventional SDCs.
III. APPLICATION
In general, a source-synchronous DDR SDRAM has its
internal data transferred in parallel, while they are transmitted
and received in series for external communication. So, a
parallel-to-serial data converter is required as I/O interface of
a DDR SDRAM.
G
Figure 5. Block diagram of the DDR SDRAM output circuitry using the
proposed SDC.
(a)
O‰PG
Figure 6. Simplified schematic diagram of the parallel-to-serial data
converter: (a) conversion from 4 parallel data to serial split data, (b)
conversion from 4 parallel data to serial spit-and-shifted data.
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Figure 5 shows the block diagram for the output interface
of a DDR SDRAM. It consists of a parallel-to-serial data
converter to converter parallel data into serial data, a set of
latches to capture the serial data coming from the data
converter, and the proposed SDC to define the timing point of
the latches. Figure 6 shows a simplified schematic diagram for
the parallel-to-serial data converter. It has two data converters:
one for converting from 4 parallel LSB data to serial split data
(Figure 6-(a)), and the other for converting from 4 parallel
MSB data to serial split-and-shifted data (Figure 6-(b)).
Internal 8-bit parallel data are converted into these two groups
of serial data by the sampling, hold, and shifting circuits
controlled by four local pulsed clocks (QCLK0~QCLK3), as
shown in the figure.
G
Figure 7. Timing diagram of DDR SDRAM output circuitry using the
proposed SDC.
Figure 7 shows the timing diagram for 8-bit parallel-to-
serial data conversion. In this conversion, 8 parallel data are
sampled by four local pulsed clocks (QCLK0~QCLK3), and
are divided into the split data and the split-and-shifted data.
Then, they are converted into 8 serial data triggered at the
rising edges of differential clock generated by the proposed
SDC [5]. During the conversion, split data is transferred to
latch-A controlled by CKO that is generated by the proposed
SDC, and split-and-shifted data is transferred to latch-B
controlled by CKOB that is also generated by the proposed
SDC. The outputs of the latches are merged to generate 8-bit
of serial data having 1/2-clock pulse width by alternating
operations between latch-A and latch-B, and fed into the
output driver for driving DQ lines.
Layout picture of the I/O interface using the proposed
SDC for a source-synchronous DDR SDRAM is shown in
Figure 8. The parallel-to-serial data converters for generating
split data and split-and-shifted data are located symmetrically
at the top and bottom sides of the layout. The proposed SDC,
data output driver and other control logic are located in the
middle of the layout picture.
 Figure 9 shows the simulated eye diagrams of the I/O
interface designed using the conventional and proposed SDCs.
The figure represents the amount of aperture window and
inter-symbol interference (ISI) due to PVT variations. The
aperture window was increased from 744ps to 858ps (15.3%)
and the ISI was decreased from 167ps to 54ps (67.7%) for
data rate of 1.0 Gbps/pin in comparison to the conventional
G SDCs.
Figure 8. Layout picture of I/O interface for a source-synchronous DDR
SDRAM using the proposed SDC.
IV. CONCLUSION
In this paper, single-to-differential signal converter (SDC)
using a phase interpolation technique and a symmetric
structure is proposed and implemented for source-synchronous
DDR SDRAM output circuitry. It is shown that the proposed
SDC minimizes the skew and duty-cycle distortion of
differential clock, and overcomes the narrowing phenomenon
of output data aperture window of source-synchronous DDR
SDRAM so as to be suitable to high-speed operation.
According to the simulation result with 1.8-V 80-nm DRAM
technology, the signal skew on the PVT variation of
(a) differential-output sampling clock was reduced from 139ps to
27ps, and the output data aperture window was improved from
744ps to 856ps for data rate of 1.0Gbps/pin.

REFERENCES
[1] Changsik Yoo. et al., “A 1.8-V 700-Mb/s/pin 512-Mb DDR-II SDRAM
With On-Die Termination and Off-Chip Driver Calibration”, 2004
IEEE Journal of Solid-State Circuits, vol.39, pp.941-951, June 2004.
(b) [2] Seung-Jun Bae, “A 3Gb/s 8b Single-Ended Transceiver for 4-Drop
DRAM Interface with Digital Calibration of Equalization Skew and
Offset Coefficients”, 2005 IEEE International Solid-State Circuits
Conference, pp.520-521, February 2005.
[3] Bradley K. Davis, “Low-Skew Single-Ended to Differential
Converter”, 2006 US Patennt 7,119,602 B2, September 30, 2004 Filed.
[4] Bruno W. Garlepp. et al., “A Portable Digital DLL for High-Speed
CMOS Interface Circuits”, 1999 IEEE Journal of Solid-State Circuits,
vol.34, pp.632-644, May 1999.
[5] Meng-Tzer Wong. et al., “A 2.5Gbps CMOS Data Serializer”, 2002
IEEE Asia-Pacific Conference on ASIC, pp.73-76, August 2002.
[6] Jan M. Rabaey, “Digital Integrated Circuits”, Prentice Hall, 2003.
(c)
[7] William J. Dally, “Digital Systems Engineerings”, Cambridge, 1998.
Figure 9. Comparison of I/O chnnel characteristics by SDCs: (a) using the
inverter-typed SDC, (b) using the transmission gate-typed SDC, (c) using the
proposed SDC.

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