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• Introduction
• Combinational logic
• Sequential logic
• Custom single-purpose processor design
• RT-level custom single-purpose processor design
processor may be
– Fast, small, low power Memory controller ISA bus interface UART LCD ctrl
gate
IC package IC oxide
source channel drain
Silicon substrate
nMOS pMOS
– Typically 0 is 0V, 1 is 5V
• Two basic CMOS types
– nMOS conducts if gate=1 1 1 1
– pMOS conducts if gate=0 x y x
x F = x'
F = (xy)' y
– Hence “complementary” x F = (x+y)'
• Basic gates 0 y x y
x F x F x x y F x x y F x x y F
F y F F
0 0 y 0 0 0 0 0 0 y 0 0 0
1 1 0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 1
F=x F=xy F=x+y F=xy
AND 1 1 1 OR 1 1 1 XOR 1 1 0
Driver
x F x F x x y F x x y F x x y F
F F F
0 1 y 0 0 1 y 0 0 1 y 0 0 1
1 0 0 1 1 0 1 0 0 1 0
F = x’ F = (x y)’ 1 0 1 F = (x+y)’ 1 0 0 F=x y 1 0 0
Inverter NAND 1 1 0 NOR 1 1 0 XNOR 1 1 1
z = ab + b’c + bc’
I(log n -1) I0 A A B
B A B
I(m-1) I1 I0 n n
… n n n
n …
log n x n n-bit n bit,
S0 n-bit, m x 1 n-bit
Decoder Adder m function S0
… Multiplexor Comparator
ALU …
… n
S(log S(log
n n
m) m)
O(n-1) O1 O0 carry sum less equal greater
O O
With enable input e With carry-in input Ci May have status outputs
all O’s are 0 if e=0 carry, zero, etc.
sum = A + B + Ci
I
n
load n-bit shift n-bit
n-bit
Register Shift register Counter
clear I Q
n n
Q Q
Q= Q = lsb Q=
0 if clear=1, - Content shifted 0 if clear=1,
I if load=1 and clock=1, - I stored in msb Q(prev)+1 if count=1 and clock=1.
Q(previous) otherwise.
a=1 a=1
a=0
1
a=1
2
a=0
• Given this implementation model
x=0 x=0
– Sequential logic design quickly reduces to
combinational logic design
I0 Q1Q0 I1
00 01 11 10
a
0 0 1 1 0 I0 = Q0a’ + Q0’a
1 1 0 0 1
x Q1Q0 I0
a
00 01 11 10
0 0 0 1 0 x = Q1Q0
Q1 Q0
1 0 0 1 0
external external
control data controller datapath
inputs inputs
… …
datapath next-state registers
control and
controller inputs datapath control
logic
datapath
control state functional
outputs register units
… …
external external
control data
outputs outputs
… …
8: x = x - y; 9: d_o = x
}
9: d_o = x; 1-J:
}
!cond
a=b C: C:
cond c1 !c1*c2 !c1*!c2
next loop-body-
c1 stmts c2 stmts others
statement statements
J: J:
next next
statement statement
declared variable
1 !(!go_i)
2:
x_i y_i
!go_i
• Create a functional unit for 2-J:
Datapath
x_sel
each arithmetic operation 3: x = x_i
y_sel
n-bit 2x1 n-bit 2x1
x_ld
• Connect the ports, registers 4: y = y_i
y_ld
0: x 0: y
x<y !(x<y)
– Use multiplexors for y = y -x
x_lt_y 9: d
7: 8: x = x - y d_ld
multiple sources 6-J:
d_o
4: y = y_i
y_sel = 0 x_i y_i
0100 4: y_ld = 1
!(x!=y)
Datapath
5: !x_neq_y
0101 5: x_sel
x!=y n-bit 2x1 n-bit 2x1
x_neq_y y_sel
6: 0110 6:
x_ld
x<y !(x<y) x_lt_y !x_lt_y 0: x 0: y
y_ld
7: y = y -x 8: x = x - y 7: y_sel = 1 8: x_sel =1
y_ld = 1 x_ld = 1
1010 5-J:
1011 9: d_ld = 1
1100 1-J:
Problem Specification
machine Sende
r rdy_in
Bridge
A single-purpose processor that rdy_out
Rece
iver
converts two 4-bit inputs, arriving one
– Rather than algorithm clock at a time over data_in along with a
rdy_in pulse, into one 8-bit output on
– Cycle timing often too central data_in(4)
data_out along with a rdy_out pulse.
data_out(8)
to functionality
• Example rdy_in=0 Bridge rdy_in=1
rdy_in=1
– Bus bridge that converts 4-bit WaitFirst4 RecFirst4Start
data_lo=data_in
RecFirst4End
Send8Start Send8End
data_out_ld=1 rdy_out=0
rdy_out=1
rdy_in rdy_ou
t
clk
data_in(4) data_out
data_lo_ld
data_out_ld
data_hi_ld
registers
data_hi data_lo
to all
data_out
(b) Datapath
2-J: x = x_i
3: y = y_i
merge state 2 and state 2J – no loop operation in
3: x = x_i between them
5:
x!=y
9: d_o = x
6: merge state 5 and state 6 – transitions from state 6 can
x<y !(x<y) be done in state 5
y = y -x 8: x = x - y
7:
eliminate state 5J and 6J – transitions from each state
6-J: can be done from state 7 and state 8, respectively
5-J:
eliminate state 1-J – transition from state 1-J can be
d_o = x done directly from state 9
9:
1-J:
• State encoding
– task of assigning a unique bit pattern to each state in an FSM
– size of state register and combinational logic vary
– can be treated as an ordering problem
• State minimization
– task of merging equivalent states into a single state
• state equivalent if for all possible input combinations the two states
generate the same outputs and transitions to the next same state