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Engineering tools and

design flow

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
 Design flow of mixed signal LSI
Design of specification

Decomposition and design of sub-system Mixed signal

simulation
Analog Functional simulation (MATLAB) Digital

Behavior modeling (Verilog-A) HDL coding and simulation

（Verilog-HDL, VHDL）
Analog circuits design (manually)
Logic Synthesis (Design Compiler)
Circuit and electromagnetic simulation
(ADS, Spectre, HSPICE) Timing simulation (Verilog-XL)

Layout design (Virtuoso) Place & route (SoC Encounter)

DRC, LVS (Calibre) Words in parentheses:

example of CAD
software
Chip implementation, DRC and stream out 2
Specification sheet of analog circuits
Specification of Operational amplifier
Parameter Target Simulation Measured value Unit Comment
value
min. typ. max. min. typ. max.
VDD 1.8 V
Bias current 312 uA No input
Open loop gain 82 dB
GBP 320M Hz Load=100fF
SR 244 V/us Load=100fF
Settling time 24n us Error 1%
CMRR -185 dB
PSRR -150 dB
Noise level 50 nV/Hz0.5 @1MHz
Common- upper -0.5 V
mode input
lower 0.9 V
range

Estimated from the host system of the circuit 3

Circuit schematic vs. Behavior model
• Circuit schematic description (e.g. SPICE, Spectre netlist)
– Description using the interconnections between MOSFET and passive
elements
– High accuracy based on the physical MOSFET model
– Taking long time for the simulation (several days ~ several week)
• Behavior model description (e.g. Verilog-AMS)
– Description using the mathematical expression of the function or electrical
characteristics of the circuits
– Expressive ability on the ideal characteristic of the circuits
– Simulation ability on the deviation between the ideal and non-ideal
characteristic
– Taking short simulation time for the simulation (several minute ~ several hour)

Design flow of analog circuit block

Circuit design of Behavior Circuit
Specification ideal behavior simulation based simulation based Layout
model on the behavior on the schematic design
model diagram
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 Expressive form of circuits
Signal form Level of description Standard language
Digital Behavioral (Resister Transfer Verilog-HDL (Verilog-D)
level) VHDL
Structural (Output from logic Verilog-HDL
synthesizer) VHDL
Transistor circuit (provided SPICE Netlist
by a semiconductor company)
Physical layout GDS-II (or stream)
Analog Behavioral Verilog-A
Verilog-AMS (Upper compatible to Verilog-A)
VHDL-AMS

Transistor circuit SPICE Netlist

Physical layout GDS-II (or stream) 5
 Purpose of HDL
Logic synthesis Logic design

Functional verification System verification

Formal verification Logic simulation
Digital HDL Timing analysis
available for the logic synthesis
Test generation Test vector design for
LSI tester
Functional verification AMS system
Analog HDL Circuit analysis verification

not available for the circuit synthesis Device modeling Emerging device model
Advanced device model

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 Purpose of circuit schematic
• Circuit schematic
– SPICE Netlist (generated by the netlister from schematic diagram)
– SPICE device model (provided by each semiconductor company)
NOTE: The analog HDL can descript the circuit in the transistor level,
but the simulation time is not shorten in compare with the circuit
simulator.

Circuit simulation

Waveform description for circuit simulation

SPICE netlist
LVS (Layout to Schematic)
The automatic layout tool
is still in development. Mixed language simulation
with Verilog-A, Verilog-D

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Mixed signal description language
• Verilog-HDL (Digital behavior description)
• Verilog-A (Analog behavior and electrical characteristic
description)
• SPICE（Transistor circuit schematic description）

Verilog-AMS Mixed language simulators:

・ Cadence: Spectre-Verilog
Analog Digital ・ Silvaco: Harmony (free for evaluation)
・ Dolphin: SMASH (free for evaluation)
Verilog-A Verilog-HDL
(OVI-96) (IEEE-1364) NOTE: Digital modules are
should be separately described
Mixed-signal extension from analog modules, because the
analog HDL usually can not be
OVI: Open Verilog International recognized by a logic synthesizer.
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Example of Mixed language description
2nd order LPF(Low pass filter)
Manually designed
Verilog-AMS SPICE
R3
R4
C C
start
Direct Digital R1 R2
freq Vin+ - + - + Vout+
clk Synthesizer (DDS) Vin- + - + - Vout-
R1 R2

C C

R4
R3
Stimuli Verilog-HDL
(Verilog-HDL (Behavioral description) using SPICE or Verilog-AMS
test bench) Synthesis
Verilog-HDL Whole circuit can be also describe using Verilog-AMS.
(Structural description) 9
 Mixed language simulation
• HDL is useful to analyze and verify the whole system and the sub-
module including the analog and digital sub-system.
• If you need to analyze with the accurate simulation with the
physical MOFET model, you can carry out the mixed
language simulation with HDL and schematic using the
mixed language simulator.
Logic simulator (HDL simulator)
AMS simulator (Mixed language simulator)

Analog HDL Digital HDL

Manually design Logic synthesis

Circuit simulator Transistor circuit Logic circuit(HDL)

NOTE: The categorization of the circuit simulator depends on the CAD software vender.
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[Appendix] SPICE behavior model
• Equivalent circuit with controlled voltage/current source
– Voltage controlled voltage source (VCVS) (SPICE-reserved char: E)
– Voltage controlled current source (VCCS) (SPICE-reserved char: G)
– Current controlled voltage source (VCVS) (SPICE-reserved char: F)
– Current controlled current source (VCCS) (SPICE-reserved char: H)

E G
+ iout
vin vout vin

Voltage gain = vout/vin Trans-conductance= iout/vin

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 Simulation tools in Kanazawa
University VDEC design room
setlic 1（for analog design） setlic 2（for digital design）

Cadence ADE-XL SimVision

GUI (Integrated Development Environment) (Waveform viewer)

Spectre Verilog-XL
Simulator （Circuit/Verilog- （Verilog-D
A simulator） simulator）

MOFET model Cell library

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 Lab.１
Build a design tool environment using your computer
account.

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