SIMPLE BOOLEAN

FUNCTION
IMPLEMENTATION

2021
EE222 DIGITAL LOGIC DESIGN
LAB 4
RONIT PRASAD – S11181729
JAKOB NAND - S11185916
JEREMAIA ELO - S11120253
Objective
The objectives of the experiment were:
I. to design, connect and test a 3-bit Majority Logic Circuit.

INTRODUCTION
The Majority Gates are logic gates which return true or high only if more than fifty percent of the

inputs are true or high, hence the name majority gate. For this lab the NAND logic gates were utilized

to implement this 3 bit majority gate. The 4 input NAND chip was utilized with the 2 input NAND

chip to obtain the majority circuit .Utilizing the universal NAND gates simplified our circuitry

compared to that of individual gates such as AND and NOT. “The NAND is commercially available in

several sizes, typically two-, three-, four-, and eight-input varieties. The NAND is more convenient to

implement than the AND. The most important reason is that with either NAND or NOR, only one type

of gate is required. On the other hand, both AND and OR gates are required; and, often, NOT gates

are needed, as well.” [1]. The use of Sum of Products (SOM) and Karnaugh Maps (K-maps) aids the

conceptualization of large logic gates and reduces the Boolean expression of a circuit.

SIMPLE BOOLEAN FUNCTION IMPLEMENTATION 2

PROCEDURES
Materials
 Breadboard.
 Chip (74LS00) Quad 2-input NAND gates.
 Chip (74LS20) Dual 4-input NAND gates.
 Resistors (~100 OHMS).
 LEDs.
 5 Volts Power Supply

The following description and steps were followed to do this lab:

1. The truth table were filled according to the input bits A,B and C with outpiut F in the outline
given below.

2. The sum-of-minterm and maxterms notations for output F were written.

3. The k-map for F was filled and the simplified SOP expression for F was obtained.
4. The logic diagrams to implement F were drawn in the form using 2-level AND-OR and 2-level
NAND circuit.
5. The wiring diagram was illustrated.
6. The circuit was constructed on breadboard and shown to lab TA.
7. The number of NAND gates was determined to turn the circuit inti a 3-bit minority logic
circuit.
8. The logic diagram was illustrated.

SIMPLE BOOLEAN FUNCTION IMPLEMENTATION 3

RESULTS & DISCUSSION
1. Truth-Table

Table 1: Truth table for a 3 input logic.

A B C F
0 0 0 0 A’ B’ C’
0 0 1 0 A’ B’ C
0 1 0 0 A’ B C’
0 1 1 1 A’ B C
1 0 0 0 A B’ C’
1 0 1 1 A B’ C
1 1 0 1 A B C’
1 1 1 1 ABC

2. Sum-of-minterms expression
F=∑m (3, 5, 6, 7)

3. Product-of-maxterm
F=∏M (0, 1, 2, 4)

SIMPLE BOOLEAN FUNCTION IMPLEMENTATION 4

 4. K-map for F

AB
C 00 01 11 10

0 0 0 1 0

1 0 1 1 1

5. Simplified SOP expression for F

F= AB +BC +AC

6. Logic diagrams
 2-level AND-OR circuit

Figure 1: 2 level AND OR circuit

SIMPLE BOOLEAN FUNCTION IMPLEMENTATION 5

  2-level NAND circuit

Figure 2: 2 level NAND gate

7. wiring plan

Figure 3: wiring diagram for 2 level NAND circuit

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 8. Circuit on the breadboard

Figure 4: 2-level NAND circuit

9. 3-bit minority logic circuit.

Table 2: minority logic truth table

A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

SIMPLE BOOLEAN FUNCTION IMPLEMENTATION 7

APPENDIX

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SIMPLE BOOLEAN FUNCTION IMPLEMENTATION 10