SCHOOL OF PHYSICS – LEVEL 200 PHYSICS LABORATORY REPORT SLIP

FOR ZCT 293/2 AND ZCT 294/2

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PARTICULARS

Name: NG WEI CHIUN

Matric no.: 154705

Group: W17

Expt. Code: 2EL11

Expt. Title: Adder and Flip-Flop Circuits

Lecturer in charge: ASSOCIATE PROFESSOR DR. WONG CHOW JENG

Report due date: 24 November, 2021

Experiment (√) Grade (√)

1 ☐ 2 √ 3 ☐ A ☐ A- ☐ B+ ☐ B ☐
4 ☐ 5 ☐ 6 ☐ B- ☐ C+ ☐ C ☐ C- ☐
D+ ☐ D ☐ D- ☐ F ☐

Date Received (Stamp) Comments

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Lab 200 Management Submission Form (ver.2) 17 April 2021

 Adder and Flip-Flop Circuits

Abstract
In this experiment, we aimed to learn about adder and flip-flop circuits. In Part 1 of
this experiment, we explored the process of addition of binary numbers through constructing
half adder and full adder circuit. We used only NAND gates and NOR gates to construct 2
separate half adders. To construct full adder, we used XOR, AND and OR gates as the
components of the circuit. Table 3, 4 and 5 were built to record the outcomes of the circuit
given certain inputs, the outcomes match that of theoretical result. Part 2 of this experiment,
we constructed R-S latch and R-S flip-flop and their functions and operations were
investigated. The R-S latch is built using 2 coupled NOR gates, while two R-S flip-flops were
built, first using only NAND gate and second one using the combination of AND and NOR
gates. Truth tables of the circuits were also built and compared to the theoretical result, the
experimental outcomes match that of theoretical result.

Theory

Adder circuit
An adder is a digital circuit that performs basic arithmetic of numbers. Adders are used
in arithmetic logic units (ALU) of most of the computers and processors. They are also used in
other parts of the processor, where they are used to calculate addresses, table indices,
increment and decrement operators and similar operations. By constructing suitable type
adders, it can perform arithmetic on different types of number representations. The most
common adders operate on binary numbers. An ALU circuit is basically a combination of many
full adders.
An adder that adds two single-bit binary digits A and B is known as half adder. It has
two outputs, sum(S) and carry (C). The carry signal represents an overflow into the next digit
of a multi-digit addition. As there are two single-bit binary digits, we have 4 different outputs,
which is shown in the truth table below.

Input
A B
0 0
0 1
1 0
1 1
Output
Carry Sum
0 0
0 1
0 1
1 0

Table 1: Truth table of a half adder circuit.

The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an
AND gate for C. The Boolean logic for the sum (in this case S) will be A′B + AB′ whereas for the
carry (C) will be AB.
 Figure 1: Half adder logic diagram.
By further modifying the half adder, we can combine two half adders to make a full adder. A
full adder is capable of adding three single-bit binary. The Boolean logic for the
implementation of full adder is S = A ⊕ B ⊕ Cin and Cout = (A ⋅ B) + (Cin ⋅ (A ⊕ B)). There are a
few types of full adder, one of example is shown below.

Figure 2: Full-adder using AND, XOR and OR gate.

Input Output
A B Cin Carry, Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Table 2: Truth table of a full adder circuit.

By using 2 full adder, we can perform addition of two 2-bit binary numbers A1A2 and
B1B2, as illustrated below. For example, with this configuration we can add two strings of 10
and 11, which corresponds to A1A2 and B1B2 respectively, the result is a 3-bit binary numbers.
 Figure 3: Operation of 2 full adders.

A + B + Cin = 1 + 1 + 1 = 1 : 1 (carry : total) Details as follow:

1 (A)
+ 1 (B)
1 : 0 (Carry : Sum) --first half adder
+ 1 (Cin)
1 : 1 (Carry : Sum) --second half adder

Similarly, by increasing the number of full adders we can add longer string of binary number.

Figure: 4 Full adders, for adding two 4-bit binary number.

Flip-flop Circuit
Flip-flop or latch is a circuit that has two stable states, this property allows them to be
used to store state information. The circuit can be made to change state by signals applied to
one or more control inputs and will have one or two outputs. R-S flip-flip flop can be either
asynchronous or synchronous (clocked). R-S flip-flop with the clock signal is also known as
clocked-R-S flip-flop. In the absence of clock signal, the output of the clocked-R-S flip-flop
remains the same despite there is any changes on the inputs. The other types of flip-flops are
D flip-flop, toggle(T) flip-flop and J-K flip-flop. J-K flip-flop is able to eliminate the invalid result
problem encounter by R-S flip-flop when both the inputs are high. While other type of flip-
flop has its own strength and application. The inputs of R-S latch are SET(S) and RESET(R). The
outputs are 𝑄𝑄� and Q, when the latch is set, Q = 1 and 𝑄𝑄� = 0. While reset is, Q = 0 and 𝑄𝑄� = 1.
 Figure 5: R-S latch using coupled NOR gates.

Table 3: Truth table and operations of R-S latch.

A clocked R-S flip-flop can be made by adding a second level NAND gates to the inverted R-S
latch. The extra NAND gates further invert the inputs so SR latch becomes a gated SR latch.
The enable, E input makes the latch to be transparent or opaque, by toggling the E input high,
changes on the R and S input will take effect, if E input is low, no changes will occur despite
input on R and S has been changed. When the enable signal input is a clock signal, the latch is
said to be clocked as discussed earlier.

Figure 6: Nand Gated Flip-flop

 Figure 7: AND and NOR Gated Flip-flop

En S R Q Q'

0 0 0 0

0 1 0 0
0
1 0 0 0

1 1 0 0

0 0 Memory Memory

0 1 0 1
1
1 0 1 0

1 1 Invalid Invalid

Table 4: Truth table of clocked R-S flip-flop.

Objective
The purpose of this experiment is to help us to understand the process of addition of binary
numbers through the functions of half adder and full adder circuits. Secondly, this experiment
involves constructing the R-S latch and R-S flip-flop using either NAND or NOR gates, which
allows us to study the functions and operations of the R-S latch and R-S flip flops from the
circuits constructed.
Methodology
For first part of this experiment, a half adder circuit is constructed by using only NAND
gates, as shown in figure 8. The truth table is then verified and completed as shown in Table
1.

Figure 8: NAND gates half adder.

Then, a half adder circuit is designed by using only NOR gates, and the truth table is confirmed.
A full adder circuit is designed using XOR, AND and OR gates and its truth table is verified.

For the second part of this experiment, a R-S latch circuit is first constructed using
NOR gates (7402). The power supply is turned on, then Q and Q’ is connected to LED 1 and
LED 2 respectively. Logic 0 is set on inputs R and S, the corresponding result is recorded by
observing any changes on the LED. The results are recorded in table 6. Logic 0 and 1 is then
applied at inputs R and S respectively, the output is observed and compared with the table 3.
Truth table 6 is built and comparison is made with the table 3.

R-S flip-flop is then constructed using NAND gates as shown in Figure 6. Inputs S and
R is connected to the switches and Q and Q’ to the LEDs. The power supply is turned on and
the output is set, so that Q = 1 and Q’ = 0 and the inputs is set as S = 0 and R= 0. The clocked
is then switched on and the output is recorded into the truth table 7. By maintaining the
circuit, the output is kept such that Q = 0 and Q’ = 0, step 2 is repeated by setting the inputs
S-R set to logic 0-1, 1-0 and 1-1. Then the output is set such that Q = 0 and Q’ = 1 and the
previous combinations of input is used to obtain the rest of the results.

Then another R-S flip-flop is constructed using AND(7408) and NOR(7402) gates as
shown in Figure 7. Same procedures as that of NAND gate R-S flip-flop are carried out. From
the observations, truth table 8 is built.
Results and Analysis
Part 1
1) Nand gate half adder

Figure 9: Nand gate half adder

(Results of the diagram are attached in the Appendix)

The switch controls the input to be 1 or 0, by toggling the switch to connect the common to
the ground (black wire), an input of 0 is feed into the chip. Conversely, by toggling the switch
to connect the common of the switch to positive terminal (red), an input of 1 is feed into the
IC.

Input Output
A B Carry, Cout Voltage, v Sum Voltage, v
0 0 0 0.00 0 0.00
0 1 0 0.00 1 5.00
1 0 0 0.00 1 5.00
1 1 1 5.00 0 0.00
Table 3: Truth table of a Nand gate half adder circuit.

The reading on the multimeter indicates the state of the output, that is, reading of 0V
implies an output of 0, while reading of 5.00V implies an output of 1.
2) NOR gate half adder
To design a half adder, there are two conditions needs to be fulfilled. First, the sum of
the binary digit, S must be 1(high) if both of the inputs are different, while S must be
0(low) if the both of the inputs are the same. Second, the carry out, C must be 1 if both
of the inputs are 1, otherwise C is 0.
These conditions can be expressed using 2 equations using Boolean algebra and De
Morgan’s Theorem.

𝑆𝑆 = 𝐴𝐴 ⊕ 𝐵𝐵
= (𝐴𝐴 ⋅ 𝐵𝐵)′ (𝐴𝐴 + 𝐵𝐵)
= (𝐴𝐴′ 𝐵𝐵 ′ )′ ⋅ (𝐴𝐴𝐴𝐴)′
= (𝐴𝐴′ 𝐵𝐵 ′ + 𝐴𝐴𝐴𝐴)′ (1)

𝐶𝐶 = 𝐴𝐴 ⋅ 𝐵𝐵
= (𝐴𝐴′ + 𝐵𝐵 ′ ) (2)

where ⊕ is XOR.
Notice that NOR gate is the complement of OR gate, thus its function can be
expressed as (A + B)’ = A′ 𝐵𝐵′

Figure 10.0: Circuit diagram of NOR gate half adder

Figure 10: NOR gate half adder

 Input Output
A B Carry, Cout Voltage, v Sum Voltage, v
0 0 0 0 0 0
0 1 0 0 1 5.0
1 0 0 0 1 5.0
1 1 1 5.0 0 0

Table 4: Truth table of a NOR gate half adder circuit.

3) Full adder (XOR, AND, OR gates)

Figure 11: Full adder (XOR, AND, OR gates)

Input Output
A B Cin Carry, Cout Voltage, v Sum Voltage, v
0 0 0 0 0 0 0
0 0 1 0 0 1 5.0
0 1 0 0 0 1 5.0
0 1 1 1 5.0 0 0
1 0 0 0 0 1 5.0
1 0 1 1 5.0 0 0
1 1 0 1 5.0 0 0
1 1 1 1 5.0 1 5.0
Table 5: Truth table of a Full Adder Circuit
Part 2
1) R-S latch

Figure 12: R-S latch using NOR gate.

R S LED 1 Q LED 2 Q’ Result

On to On On to On Hold
0 0 Q Q
Off to Off Off to Off state
0 1 On 1 Off 0 Set
1 0 Off 0 On 1 Reset
1 1 Invalid * Invalid * Racing
Table 6: Truth table of R-S latch.
2) NAND gate R-S Flip-flop

Figure 13: NAND gate R-S Flip-flop.

Input Output before clock signal Output after clock signal

R S Q Q’ Q Q’
0 0 1 0 1 0
0 1 1 0 1 0
1 0 1 0 0 1
1 1 1 0 0,1 (invalid) 0,1 (invalid)
0 0 0 1 0 1
0 1 0 1 1 0
1 0 0 1 0 1
1 1 0 1 0,1 (invalid) 0,1 (invalid)

Table 7: Truth table of NAND gate R-S Flip-flop

3) AND, NOR gate R-S Flip-flop

Figure 14: AND, NOR gate R-S Flip-flop

(Note that R and S switch has been flipped)

Input Output before clock signal Output after clock signal

R S Q Q’ Q Q'
0 0 1 0 1 0
0 1 1 0 1 0
1 0 1 0 0 1
1 1 1 0 0,1(invalid) 0,1(invalid)
0 0 0 1 0 1
0 1 0 1 1 0
1 0 0 1 0 1
1 1 0 1 0,1 (invalid) 0,1 (invalid)
Table 8: Truth table of AND and NOR gate R-S Flip-flop.
The results of truth table 7 and 8 can be summarised as in this table below
En S R Q Q'

0 0 0 0

0 1 0 0
0
1 0 0 0

1 1 0 0

0 0 Memory Memory

0 1 0 1
1
1 0 1 0

1 1 Invalid Invalid

Table 9: Summarization of truth table 7 and 8.

Discussion
The experimental outcomes match that of the theoretical results, this is
reflected by all the truth tables 3 to 8 shows the same result as that of theoretical one. In part
2 of this experiment, from the truth table we see that the R-S latch does appear to have a
feedback path and it is able to retain information that is feed into it. Therefore, it can act as a
memory device. As for the R-S flip-flop, there is an additional Enable, E input compared to R-
S latch. According to table 7 and 8 ,the E inputs stops any input signal from changing the
output. The E-input can also be replaced by clock signal generator, so that the output will
synchronize with the clock signal.
As this experiment is conducted using computer simulation program, the
problems arise from the software itself. During the experiment, the software might not give
the accurate result, for instance when certain variable is applied to the input, the output
might not react promptly. Moreover, certain results of this experiment are very hard to obtain,
especially during the Part 2 of this experiment. The program is unable to render the
simulations smoothly when the clocked R-S flip-flop is being tested. As a result, the website
crashes frequently or produce inaccurate result due to latency.

Figure 15: Problem encountered during the experiment.

In order to mitigate these problems, alternative software might need to be used
or real physical components is needed to perform part of this experiment. Nevertheless, after
many attempts, the results are able to be confirmed and verified and the results match
completely with the theoretical result.
If this experiment is conducted in lab, several precautions need to be taken to
ensure the experiment can run smoothly. For instance, experimenter must refer to data sheet
of the components before using it, this is done so to avoid the component experience break
down due to excessive current or voltage applied through it. In this experiment, additional
resistors are used to act as voltage divider to protect the IC. Before doing the experiment, the
individual component also needs to be checked to make sure none of them is malfunction.
The signal usually arrives in pulses for the IC, so if the input is being feed continuously into
the IC, the IC will overheat easily. To prevent this, experimenter should not hold on to the
input button for too long.
Conclusion
In Part 1 of this experiment, we explored the process of addition of binary
numbers through constructing half adder and full adder circuit, the adders were constructed
using different combination of logic gates and the results are identical. Part 2 of this
experiment, we constructed R-S latch and R-S flip-flop and their functions and operations
were investigated. Truth tables of the circuits, table 3, 4, 5, 7 and 8 were built and compared
to the theoretical result table 1 ,2 ,3 and 4, the tables show the same result, therefore the
experimental outcomes match that of theoretical result.

Reference
1) Ong.L.H (2012), Adder and flip-flop Practical II 2EL11 USM Lab manual
2) Wikipedia Flip-flop and latch, retrieved from https://en.wikipedia.org/wiki/Flip-
flop_(electronics) on 12 Nov 2021.
3) Electronic coach (2017), Half adder, retrieved from
https://electronicscoach.com/half-adder.htm on 12 Nov 2021.
Appendix
74HC (HCMOS family)

Symbols Definition Max. Min. Typical Unit

Vsupply Supply Voltage 6.0 2.0 5.0 V
VIH High level input voltage 6.0 1.5 5.0 V
VIL Low level input voltage 1.8 0 2.1 V
VOH High level output voltage 5.9 1.9 4.4 V
VOL Low level output voltage 0.1 0 0 V

Figure 16.0 to 16.2: Demonstration of operations of Nand gate half-adder

Figure 17.0 to 17.3: Demonstration of operations NOR gate half-adder

Figure 18.0 to 18.4: Demonstrations of operation of full adder.

Boolean algebra

De Morgan’s Theorem