MOSFET types:

Depletion Type: The transistor requires the Gate-Source voltage (VGS) to switch the device “OFF”.
The depletion mode MOSFET is equivalent to a “Normally Closed” switch. Enhancement Type: The
transistor requires a Gate-Source voltage(VGS) to switch the device “ON”.

What are the future research trends in VLSI domain?

About NIELIT:

National Institute of Electronics and Information Technology (NIELIT), Calicut, is an autonomous

body of Ministry of Electronics and Information Technology, Govt. of India. The Centre is a premier
organisation for education, training, R&D and consultancy in IT and electronics.

The objective was to bridge the gap between the academic institutions and industries. A decade
after the successful running of CEDT, Bangalore, the then Department of Electronics (DoE), initiated
a programme to set up similar centres in other parts of the country with a wider objective to
develop human resources at different levels and in different specialised areas of Electronics Design.

Q003 Both being universal gates, which one will be preferred more, NAND gate or NOR gate? and
Why?

Ans Nmos - carriers of electrons

Pmos - carriers of holes

Mobility of holes is slower than electrons

Gate leakage power is low in NAND gate

NOR gate - pmos gates are connected in series so it increases the resistance to overcome this need
to increase the size of Pmos, it occupies more area power but in

NMOS - PMOS are in parallel

NAND, Reason mobility of pmos and nmos, in NAND pmos are in parallel with low mobility so less
delay while in NOR pmos are in series with low mobility so higher delay

Nand gate because it consumes low power compared to nor

Q004

With the potential difference between the source and the drain kept small (VDS is small), the
MOSFET behaves as a resistance whose value varies ______ with the overdrive voltage

A. Linear

B. Exponential

C. Logarithmic

D. Inverse

Choose appropriate option.

D?
Q005

What is the relation between threshold voltage and temperature for MOSFET?

Q005 Ans

As the temperature increases the threshold voltage Decreases as lower the threshold voltage means
more the drain current & device will faster

Q006

Assume an inverter in the generic 0.25 mm CMOS technology designed with a PMOS/NMOS ratio of
3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L = 1.5). Compute
the gain at VM (= 1.25 V).

A. -27.5

B. -37.5

C. -47.5

D. -57.5

Choose an appropriate option.

Q007

Calculate the power dissipation in a CMOS inverter. Consider a CMOS inverter with a load
capacitance of CL = 2 pF biased at VDD = 5 V. The inverter switches at a frequency of f = 100 kHz.

A. 4uW

B. 3uW

C. 2uW

D. 5uW

Choose appropriate option.

Q008

Calculate the gain of a pseudo –NMOS inverter at the threshold voltage without ignoring the
transistor output impedances. Assume ʎn=0.060 and ʎp=0.065.

A. -32

B. -33

C. -34

D. -31
Choose appropriate option.

Q009

Find the threshold voltage of the inverter. Assume µn=545 cm2/V.S and µp=130 cm2/V.S Vtn=0.8 V
and Vtp=-0.9 V and Vdd=3.3 V.

Max, [12-02-2020 09:53 PM]

Knowledge:

If you want threshold of inverter to be Vdd/2, maintain the PMOS width should be r (2 to 3 times)
NMOS size.
Why first case have more delay(69) than second (62)

What means FinFET ?

a) Finfet is device with a multiple gates & it is more efficient than MOSFET As we know MOSFET
has only one gate terminal.

We called it as a finfet because of it's fin like structure

If u design the ckts using mosfet during scaling there exist short channel effects which is overcome
by finfets

FinFETs will create other kind of challenges too.

What's the benefits of having multiple gates

a) Advantage of finfet is to having excellent control of short channel effect in submicron regime
and making transistor more scalable Very low off-state current
Any one can convert this rtl into cmos and pass transistors implementation level?

Pass transistors implementation is low power or cmos?

Question 1. Why Metal Density Rules Are Important?

Answer :

Metal Density rules take care of metal over-etching and metal lift off issues encountered durinf
manufacturing process.

Question 2. Why Power Stripes Routed In The Top Metal Layers?

Answer :

Power routes generally conduct a lot of current. In order to reduce effect of IR drop, we need to
make these routes less resistive. Top metal layers are thicker and offer lesser resistance. This helps
to reduce IR drop.
Question 3. Types Of Checks That Can Be Done In Prime Time ?

Answer :

Timing (setup, hold, transition), design constraints, nets, noise, clock skew and analysis coverage.

Question 4. How Do You Validate Your Floorplan And What Analysis You Do During Floorplan?

Answer :

Overlapping of macros.

Global route congestion -> in order to finalize Min. Channel spacing.

Allowable IR drop.

Physical information of the design (report_design_physical)

Question 5. How Many Clocks You Had In Your Designs? How Did You Do Cts For The Same?

Answer :

I had 5 clocks in my designs, sys_clk, sys_rclk, uart_clk, g_clk and scan_clk, where sys_clk, g_clk and
uart_clk logically exclusive to scan_clk.

Question 6. Did You Get Antenna Problem In Your Project For All The Metal Layers? How Did You Fix
Them?

Answer :

Metal Jumper and Antenna diode are two methods to resolve Antenna violations. But Metal Jumper
is preferred approach as it does not need change to the Netlist and placement. This methodology
works for antenna violations on all metal layers except for the top most layer. In this methodology,
we will switch the small portion of routing to higher level metal close to the location of failing gate.
This will make sure that accumulated charges on metal layer does not affect the gate as gate will not
be connected to the charge carrying metal route until higher level metal is manufactured.

For example, lets say antenna violation is in M2. This means that M2 has enough area to accumulate
large charge that induces high electron voltage to destroy the gate. To solve this problem, we cut a
portion of M2 close to failing gate and move the routing to M3. This makes sure that when M2 is
being manufactured, it does not get connected to gate. Connection happens only when M3 gets
manufactured which is much later in time. By then charges on Metal M2 would have leaked away.

When metal jumper is not possible to implement (probably due to routing congestion or violation
happening in top most layer) we try to fix it by inserting antenna diode closed to gate failing
antenna. Antenna diode provide electrical path for safe conduction of accumulated charges to the
substrate. Antenna diode is a reversed biased diode but acts like resistor during manufactured
process (CMP) due to high temperature environment.
Question 7. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your Design?

Answer :

Use HVT cells for timing paths having +ve slacks.

Use LVT cells for timing paths having -ve slacks.

HVT cells have a larger delay but less leakage. +ve slack in a design is not useful as having only some
paths working faster will not help overall design. We are good if the slack is 0. In such cases give up
the slack by using HVT cells but gain on power dissipation.

LVT cells are very fast but very leaky. Limit the use of LVT cells to only those paths that have
difficulty in closing time.

Question 8. What Is Electromigration And How To Fix It?

Answer :

Electromigration (EM) refer to the phenomenon of movement of metal atoms due to momentum
transfer from conducting electrons to metal atoms. Current conduction over a period of time in a
metal route causes opens or shorts due to EM effect. EM effect cannot be avoided.

In order to minimize its effect, we use wider wires so that even with EM effect wire stays wide
enough to conduct over the lifetime of the IC.

Question 9. What Are The Various Statistics Available In Ir Drop Reports?

Answer :

IR drop info for VDD/ VSS.

Maximum current through VDD/VSS.

Number of current sources for VDD/VSS.

Utilization of metal layers used.

EM information for signal and via.

Q Do You Know About Input Vector Controlled Method Of Leakage Reduction?

Answer :

Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives
least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the
leakage current of the circuit when it is in the standby mode. This method is known as input vector
controlled method of leakage reduction.

Q How Can You Reduce Dynamic Power?

Answer :

Reduce switching activity by designing good RTL

Clock gating

Architectural improvements

Reduce supply voltage

Use multiple voltage domains-Multi vdd

Q How Will You Synthesize Clock Tree?

Answer :

Single clock-normal synthesis and optimization

Multiple clocks-Synthesis each clock seperately

Multiple clocks with domain crossing-Synthesis each clock seperately and balance the skew

Q Why Buffers Are Used In Clock Tree?

Answer :

To balance skew (i.e. flop to flop delay)

What are the differences between DFM and DRC?

MBCFET
Q010

Can anyone write the smallest possible Verilog code for 16 to 1 mux?

module mux16_1(i,s,f);

input [15:0] i;

input [3:0] s;

out f;

assign f=i[s];

endmodule

Find d state table of d given logic design???

Q011

Can anybody draw the state diagram of D flip-flop?

Mealy and Moore both?

MosFET Short Channel Effects

---------------------------------------------------

The motive behind reducing the size of the transistors, and their channel lengths, results in increased
speed and reduced cost. When we make circuits smaller, capacitance reduces, thus operating speed
increases. Also, smaller circuits allow more of them in the same wafer, dividing the total cost of a
wafer and per transistor cost.

Each such benefit gets some new issues and challenges with technology.

The list of problems arises with this reduced size of channel.

Those are called Short Channel Effects. Our discussion will be around feature size reduction, trends
and problems arising called short channel effects.
Q011 Master slave flip flop(Master slave configuration is latch not a flip flop ,But it is named as a flip
flop ,Don't confuse(Master slave configuration of two latches works as a flip flop.is it(Both are
connected using not gate at the triggering))) configuration is same as, (A) Latch (B) Level triggered
Flip Flop (C) Edge triggered Flip Flop (D) None of above

Explanation: Latch is level triggered . Outputs change immediately after inputs change.
Asynchronous And...

Flip-flop is edge triggered. Synchronous w.r.t a clock.

There is no level triggered flip-flop. If at all it is.. it is a latch.

(In simple language

If latch has clock then it is flip flop otherwise it is latch

Another difference is

If clock is level triggered-latch,

If clock is edge triggered-flip flop.)

Edge triggered flip flop

I think all the flip flops are edge triggered. Only n only latches are level triggered.

q) how to convert flip flop to latch?

RTL to CMOS conversion is not that simple. As per my understanding.

q) How to convert a latch into flip flop? a) By applying pulse triggering circuit(edge triggering
clock( Pulse means edge. )) into latch input. Master slave configuration of latch works.as a flip-flop

Even if we make inputs of the latch change w.r.t edge of a clock that is making inputs synchronised
w.r.t a clock, the behaviour of the flip-flop that is output getting delayed by 1 clock w.r.t to input
changes is not achieved
Cant agree with above pic cuz , Master slave flip-flop core concept is inverted clock. If I give first
latch , inverted clock than it will be same as positive edge triggered flip-flop. So better call it, edge
triggered flip flop or actually just flip flop... As flip-flops are bound to be sensitive to one of the
edges. Bcz there is not gate ...means square wave...means pulse ( clock)

Q012

Draw the Mealy FSM state diagram for the circuit giving output 1, if last three received bits are 101.

Mealy of 101 overlapping case , above

Q013

Draw the Moore FSM state diagram for the circuit giving output 1, if last three received bits are 101.
Moore machine of 101 non-overlapping, above

Moore machine of 101 overlapping , above

What is asynchronous circuit? A) Synchronous circuit output changes with clock and asynchronous
circuit output change does not depend on clock

If in a design there are.mkre than one clock.then the design is said to be synchronous or
asynchronous

In synchronous ckt clock is synchronised but in asynchronous ckl is different in each block ie clk is not
synchronised
See the frequency of each clk if each clk having same freq than it is synchronous ckt otherwise it is
asyn. Ckt

Ohk.if one call frequency is twice of second clock frequency,with no phase difference then?
Asynchronous (It depends on application too.. the max speed of asynchronous counter is limited as
compared to synchronous counter for large counter size...)

Which one is better to use real time (synchronous or asynchronous)

It depends on the output i mean what do u want from the ckt. These ckts are randomly made not
for any special purpose . Random circuit you made are top three bit SISO shift register and three bit
asynchronous down counter.

For interview purpose if asked without any extra conditions like phase relationship all those:

Synchronous circuit : single clock domain circuit

Asynchronous circuit : can be purely combinatorial logic circuit or multiple clock domain circuit.
q) booths_multiplier 8 bit

q) How to convert the generated rtl into cmos level

q) How can we make clock generator with gates only ?

module lab3b_booths_multiplier_anna(

input [3:0]a1,

input [3:0]b1,

input clock,

output wire [7:0]p

);

reg [2:0] counter;

reg q_1;

reg [3:0] a;

reg [3:0] q;

reg [3:0] m;

reg flag;

initial

begin

flag=0;

q_1 = 0;

a = 0;

end

always@(posedge clock)

begin

if (flag==0)

begin

q = b1;

m = a1;

counter=0;

flag = ~flag;

end

if (counter<4)

begin

if(q_1 == q[0])

begin
a[2]<=a[3]; //RIGHT SHIFTING

a[1]<=a[2];

a[0]<=a[1];

q[3]<=a[0];

q[2]<=q[3];

q[1]<=q[2];

q[0]<=q[1];

q_1<=q[0];

counter = counter +1;

end

else

begin

if(q[0] == 1 && q_1 == 0)

begin

a = a + (~m + 1);

a[2]<=a[3];

a[1]<=a[2];

a[0]<=a[1];

q[3]<=a[0];

q[2]<=q[3];

q[1]<=q[2];

q[0]<=q[1];

//RIGHT SHIFTING

q_1<=q[0];

counter = counter +1;

end

if(q[0] == 0 && q_1 == 1)

begin

a = a + m;

a[2]<=a[3];

a[1]<=a[2];
a[0]<=a[1];

q[3]<=a[0];

q[2]<=q[3];

q[1]<=q[2];

q[0]<=q[1];

q_1<=q[0];

//RIGHT SHIFTING

counter = counter +1;

end

end

end

end

assign p[0]=q[0];

assign p[1]=q[1];

assign p[2]=q[2];

assign p[3]=q[3];

assign p[4]=a[0];

assign p[5]=a[1];

assign p[6]=a[2];

assign p[7]=a[3];

endmodule