Single Electron Transistor

Project guide : Mr.K Manjunath,

M.Tech.,
Assistant Professor,
E.C.E Dept. Presented by
P.Kiran Kumar ,
M.Tech VLSI-System
Design ,
Roll No. : 09751D5709.
outline
 Introduction
 What is a SET
 Operation of SETs
 Advantages & disadvantages of SET
 Hybrid CMOS-SET
 Application of SETs
 Conclusion
 INTRODUCTION
 In VLSI a measure of progress is determined by
number of devices per chip ,chip size & process technology used
within.

 The continued trends have been to produce smaller ,faster and

less expensive systems which consumes less power.
TECHNOLOGY ROAD MAP
YEAR TECHNOLOGY YEAR TECHNOLOGY

1971 10 µm 1999 180 nm

1974 6 µm 2000 130 nm

1975 3 µm 2002 90 nm

1982 1.5 µm 2006 65 nm

1985 1 µm 2008 45 nm
1989 800 nm
2010 32 nm
1994 600 nm

1995 350 nm

1998 250 nm
CROSSING THE 10 nm WALL
 Technology scaling has pushed the MOSFET dimesions
towards towards 10 nm channel length.
 Performace limiting factors at 10 nm.
 1 . Electrostatic limitations
 2. source to drain tunneling
 3. Carrier mobility
 4. Process variations and
 5. Static leakage
WHAT IS SET ?
The single electron transistor is a new type of
switching device that uses controlled electron
tunneling to amplify current .

Figure1. Schematic of a single electron

OPERATION
 SET operation is based on Coulomb blockade
effect.
 COULOMB BLOCKADE :
 In nano structures current flow can be blocked
by electrostatic charging of single electron.
 Criteria
 The biasing voltage |Vb | >e/C
 The charging energy E >>kT
 The tunneling resistance Rt > h/2∏e2
 TUNNELING OF ELECTRONS FROM ONE LEAD TO
ANOTHER THROUGH A METAL ISLAND

Figure 2.The small metal island is sufficiently small that addition of single electron
to the island will change it’s energy state significantly by E=q 2 /2C ,q is charge &
C is total capacitance of the metal island .
 ENERGY BAND STRUCTURE FOR A TUNNEL
JUNCTION

Figure3. The electron can only tunnel on to the island if it has the energy of
q2/ 2C greater than fermi energy level in the metal leads
I-V characteristics of double tunnel junction
I-V characteristics of double tunnel junction
and charge built up with bias voltage
FIGURATIVE SKETCH OF THE SET MOSFET
STRUTURE & CROSS-SECTIONAL SKTECH OF
QUANTUM WIRE MOSFET
One dimensional electron gas forms at the top GaAs-AlGaAs
interface with a density controlled by substrate voltage Vg
A top view showing the typical dimension of the top metal
gate structure which defines the narrow channel with two
constrictions
Application of positive bias to the top gate while the bottom gate
is grounded or negatively biased results in inverting the surface
only in the thin region between two portions of the lower gate
(marked as quantum wire in figure).therefore electrons can flow
from source to drain through this wire.

 An interesting feature of the gated MOSFET device is that an

additional Control exists i.e., the gate voltage Vg

The electrostatic energy of the charge q within the inversion

layer of the transistor is given by

E = qVg + q2 / 2C…………..equation 2
CONDUCTANCE OF THE QUANTUM WIRE
MOSFET
 The conductance of the quantum wire exhibits periodic
peaks as a fucntion of applied bias .
 The periodic peaks are the usual signature of the
quantized phenomenon of charge itself.
 The origin of the oscillations behavior arises from the
temperature dependence of the impurity charge
distribution at the si-sio2 interface.
 the period of oscillation corresponds to charging of the
inversion layer ;a single period corresponds to addition
of a single electron to the channel.
POTENTIAL AND SPATIAL LOCATION OF THE
INTERFACE STATE CHARGES WITHIN QUANTUM WIRE
CHANNEL OF MOSFET DEVICE
 ENERGY BAND STRUCTURE OF THE TUNNEL
JUNCTION INCLUDING THE SPATIAL
QUANTIZATION EFFECTS

The small spatial size of the isolated island results in spatial quantization effects
ADVANTAGES & DISADVANTAGES

 Advantages :
 Good scalability – nano feature size.
 Low power.
 High speed.
 Disadvantages :
 Operation at room temperature.
 Fabrication .
 Charge offset – one electron at a time.
HYBRID CMOS -SET
 SET key advantages :
 Ultra-small (nm)
 Ultra-low power consumption(10-8-10-10 W )

(~5decades better than CMOS )

o New functionality
Could be combined with CMOS
CMOS and SET are complimentary
+ high driving capability - low driving capability
+ high input impedance - high output impedance
+ high voltage gain - small VDS
APPLICATIONS

 Important applications of single-electron transistors is

in memory cells .
 SET as a photon detector.
 SET as a mixer.
 Quantum computers – 1000 x faster.
 High sensitivity electrometer-radio frequency SET
DRAM MEMORY CELL USING SET
CONCLUSION
 Researchers may someday assemble these
transistors into molecular versions of silicon
chips , but there are still formidable hurdles to
cross.
 SETs could be used for memory device, but
even the latest SETs suffer from “offset
charges”, which means that the gate voltage
needed to achieve maximum current varies
randomly from device to device. Such
fluctuations make it impossible to build
complex circuits.
 The future does look bright for these devices.
THANK YOU !!
QUERIES ? ?