Submitted by:- Submitted to:-

Dheeraj Gupta Dr.Tarun Varma

(2019PEV5462) Associate Professor
Dept. of ECE
 TOPIC 1-CMOS INVERTER
1. A Technique to Improve the Drive Current of High-Voltage I/O
Transistors in Digital CMOS Technologies
INTRODUCTION-
AS MOS transistors are scaled to operate at higher speed, the operating voltage and gate
oxide thickness are also scaled down. To provide the capability to maintain compatibility to
the systems using circuits fabricated in older generations of technologies, high voltage I/O
transistors became part of a standard technology offering. For instance, in 1.2-V 0.13- m
CMOS processes, 3.3-V 0.34- m I/O transistors are available. The 1.2-V logic levels are
translated to the 3.3-V logic levels using an interface circuit formed with 3.3-V transistors. A
problem with this circuit is that the gates of 3.3-V drive transistors (M3 and M4) with higher
threshold voltage are driven by a circuit whose output switches between 0 and 1.2 V. Because
of this, the gate overdrive, thus the drive current is limited. These in turn limit the switching
speed of I/O circuits. In this letter, a composite MOS transistor structure with similar drain-
to-source and drain-to-gate breakdown voltages as that of the 3.3-V thick-oxide I/O
transistors, and with the same threshold voltage as that of the 1.2-V thin-oxide transistors is
proposed. The composite structure consists of a series combination of a 0.12- m-long thin-
oxide transistor and a 0.22- m long thick-oxide transistor.
LEARNING-
The channel formation was mainly determined by the TN sub transistor, while the
breakdown characteristics are mainly determined by the TK sub transistor. The measurements
show that the composite transistor has the same threshold voltage as a 1.2-V transistor, more
than two times that of the saturation drain current of a 3.3-V transistor at V and V, and high
breakdown voltages as a 3.3-V transistor. Using the composite MOS structure, it should be
possible to improve the speed performance of digital I/O circuits.
PROJECT PRPOSAL
A composite NMOS transistor, combining a TN sub transistor with the 1.2-V gate oxide and
a TK sub transistor with the 3.3-Vgate oxide, was proposed. Our proposal is A composite
NMOS transistor, combining a TN sub transistor with the 1.2 gate oxide and a TK sub
transistor with the 1.8-V gate oxide.
TOOL REQUIRED- Cadence or Hspice

REFERENCES
[1] K. K. O and J. Yasaitis, “Integration of two different gate oxide thicknesses in A 0.6-um
dual voltage mixed signal CMOS process,” IEEE Trans. Electron Devices, vol. 42, no. 1, pp.
190–192, Jan. 1995.
[2] W.-T. Wang, M.-D. Ker, M.-C. Chiang, and C.-H. Chen, “Level shifters for high-speed
1-V to 3.3-V interfaces in a 0.13-um Cu-interconnection/low-K CMOS technology,” in
Symp. VLSI Tech. Dig., Apr. 18–20, 2001.
2. Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on
an Active Leakage-Current Reduction Technique
INTRODUCTION-
This brief has described a subthreshold-supply bootstrapped CMOS inverter with an active
leakage current reduction technique. Based on 4500 times of Monte Carlo simulations, the
average delay time of the proposed design with 200-fF CL is 6.9 ns with a standard deviation
of 6.3 ns, which achieves a reduction of 76% from the conventional inverter. Measured
results verify that the test chip can achieve a clock rate of 10 MHz at 200 mV VDD. Due to
the negative VGS suppression, the measured leakage power is more than 50% improvement
over the previously reported bootstrapped drivers. The power consumption is 1.01 μW, and
the leakage power is 107 nW, and the energy efficiency is 0.1 pJ/ cycle. This brief presents a
bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to
improving the driving ability, a large gate voltage swing from −VDD to 2VDD suppresses
the subthreshold leakage current. As compared with other reported works, the proposed
bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore,
our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of
delay time is only 6.3 ns under the process and temperature variations with 200-mV
operation.
LEARNING
This brief has described a subthreshold-supply bootstrapped CMOS inverter with an active
leakage current reduction technique. Based on 4500 times of Monte Carlo simulations, the
average delay time of the proposed design with 200-fF CL is 6.9 ns with a standard deviation
of 6.3 ns, which achieves a reduction of 76% from the conventional inverter. Measured
results verify that the test chip can achieve a clock rate of 10 MHz at 200 mV VDD. Due to
the negative VGS suppression, the measured leakage power is more than 50% improvement
over the previously reported bootstrapped drivers. The power consumption is 1.01 μW, and
the leakage power is 107 nW, and the energy efficiency is 0.1 pJ/cycle.
PROJECT PRPOSAL
Above paper has described a subthreshold-supply bootstrapped CMOS inverter with an active
leakage current reduction technique. Our proposal is to Design of a Subthreshold-Supply
Bootstrapped CMOS Inverter Based on dynamic power reduction technique.
TOOL REQUIRED- Cadence or Hspice

REFERENCES
[1] J. Kil, J. Gu, and C. H. Kim, “A high-speed variation-tolerant interconnect technique for
sub-threshold circuits using capacitive boosting,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 16, no. 4, pp. 456–465, Apr. 2008.
[2] J. W. Kim and B. S. Kong, “Low-voltage bootstrapped CMOS drivers with efficient
conditional bootstrapping,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 556–
560, Jun. 2008.
 3. Analysis and Design of the Classical CMOS Schmitt Trigger in
Subthreshold Operation
INTRODUCTION
ULTRA-low-voltage circuits have gained considerable attention in voltage-constrained
applications. Small supply voltages generally force the MOS transistors to operate in the
subthreshold region. One of the most useful circuits for both analog and digital applications is
the standard CMOS Schmitt trigger. In contrast to the bipolar and OP-AMP based ST
circuits, which have been analysed in detail in the literature, there are few in-depth studies on
the CMOS ST. Even though some authors have claimed that the pile-up of four transistors
between power and ground rails means that the classical CMOS ST is not appropriate for
low-voltage applications, it has been employed as the key element in several ultralow-voltage
(ULV) circuits. In ST-based logic gates, designed for the maximization of the on-to-off
current ratio, were able to operate from a supply voltage as low as 62 mV. This remarkable
result motivated us to carry out an in-depth study of the Schmitt-trigger in the subthreshold
region.
LEARNING
In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold region is
analysed. The complete DC voltage transfer characteristic of the CMOS ST is determined.
The metastable segment of the characteristic is explained in terms of the negative resistance
of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to
determine the minimum supply voltage at which the hysteresis appears and to obtain a rough
estimation of the hysteresis width. It is shown that the theoretical minimum supply voltage
required to obtain hysteresis is 75 mV at room temperature. A test chip with CMOS Schmitt
triggers was designed and fabricated in a 180 nm technology in order to study their operation
at supply voltages between 50 mV and 1000 mV.
PROJECT PRPOSAL
Above paper proposed that A test chip with CMOS Schmitt triggers was designed and
fabricated in a 180 nm technology in order to study their operation at supply voltages
between 50 mV and 1000 mV. our proposal is A test chip with CMOS Schmitt triggers is
design and fabricate in a 135nm technology in order to study their operation at supply
voltages between 50mv to 500mv.
TOOL REQUIRED -Hspice or Cadence

REFERENCES
[1] L. A. P. Melek, M. C. Schneider, and C. Galup-Montoro, “Ultra-low voltage CMOS logic
circuits,” in Proc. Argentine Conf. Microelectron., Technol. Appl., 2014.
[2] N. Lotze and Y. Manoli, “A 62 mV 0.13 μm CMOS standard-cellbased design technique
using Schmitt-trigger logic,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 47–60, Jan. 2012
 4. An Analytical Model for the Effective Drive Current in CMOS Circuits
INTRODUCTION
FOR predicting CMOS circuit speed, a simple metrics based on device dc current is widely
used. In this metrics, the circuit delay is expressed as CVdd/I, where C is the load
capacitance, Vdd is the supply voltage, and I is the transistor current of a CMOS logic circuit.
An effective drive current Ieff, instead of ION or Idsat, is used for specifying transistor
charging and discharging capability that determines circuit speed. The Ieff definition is based
on the accurate approximation of transistor behaviour during inverter switching The reason
for the widespread application of CVdd/Ieff delay model is its ease of use: the model contains
no fitting parameters and, except for the conventional current measurements, does not require
elaborate procedures for parameter extraction. In addition, Ieff definition is technology
independent and is widely used in studies of technology fundamentals and for explaining
advanced device concepts. The Ieff expression is based on analysis of the switching trajectory
of MOS transistors. It is developed by approximating the inverter switching trajectory using
two current points
LEARNING
Inverter delay is often evaluated as CVdd/Ieff, where C is the load capacitance, Vdd is the
supply voltage, and Ieff is the effective drive current derived by approximating the inverter
switching trajectory with a linear model. The Ieff model utilizes high and low drain currents
conventionally measured in wafer acceptance tests and does not require extraction of any
parameters. Ease of use combined with reasonable accuracy (∼15%) is the main reason for
wide application of CVdd/Ieff delay metrics. However, CVdd/Ieff expression produces large
errors when applied to another two important basic circuits: nand and nor. This is because
nand and nor circuits contain transistor series connections not accounted for in the inverter
model. In this paper, an analytical solution for the transistor series connection influence on
the discharge/charge operation in nand/nor circuits is provided. The model for nand/nor
effective drive current (denoted as Istack) developed in this paper maintains simplicity of the
original Ieff expression.
PROJECT PROPOSAL
In above proposed paper Comparison results show that CVdd/Istack equation provides ∼15%
accuracy for nand/nor circuits in line with CVdd/Ieff accuracy for inverter and our proposal is
to improve the accuracy and effective drive current of proposed CMOS circuit.
TOOL REQUIRED- Cadence or Hspice
REFERENCES
[1] H. Zhang, M. Gupta, J. Watt, and L. Wei, “Effective drive current for pass-gate
transistors,” IEEE Trans. Electron Devices, vol. ED-63, no. 8, pp. 2999–3004, Aug. 2016.
[1] A. Razavieh et al., “Effective drive current in scaled FinFET and NSFET CMOS
inverters,” in Proc. 76th Device Res. Conf. (DRC), Jun. 2018.
 TOPIC-2
Operational transconductance amplifier

1. A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-m CMOS

INTRODUCTION
Operational transconductance amplifiers (OTAs) are important building blocks for various
analog circuits and systems. Depending on system needs, an OTA must satisfy many design
requirements. As CMOS technologies evolves well into the ultra-deep-sub sub micrometre
regime, the supply voltage decreases and device characteristics deteriorate. These conditions
pose severe challenges in amplifier designs. For example, the transistor intrinsic gain in deep-
sub micrometre processes is typically low due to inferior device output impedance.
Cascoding transistors can raise the circuit impedance and thereby boost the gain.
LEARNING
A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near
rail-to-rail output swing is presented in this brief. The proposed circuit is based on the
current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance
the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB
dc gain and a gain–bandwidth product of 160 MHz while driving a 2-pF load. The OTA is
designed in a 0.18- m CMOS process. The power consumption is 0.25 mW including the
common-mode feedback circuit.
A low-voltage low-power CMOS OTA is introduced in this brief. The proposed circuit is
based on the current-mirror topology. To circumvent the low-gain problem of a CMOTA,
several design techniques are employed.
PROJECT PRPOSAL
The above proposed circuit was based on the current mirror topology and simulated on
0.18um CMOS Technology and our proposal is to implement the above proposed circuit on a
135nm Technolgy.
The dc gain of the above proposed OTA was 62dB and our proposal is to improve the dc gain
TOOL REQUIRED- Cadence or Hspice

REFERNCES
[1] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, “Low-voltage
super class-AB CMOS OTA cells with very high slew rate and power efficiency,” IEEE J.
Solid-State Circuits, vol. 40, no. 5, pp. 1068–1077, May 2005.
2. Frequency-Dependent Harmonic-Distortion Analysis of a Linearized
Cross-Coupled CMOS OTA and its Application to OTA-C Filters
INTRODUCTION
Recent progress of wide-band communication systems demands high-frequency circuits.
Conventionally, the linearity of the operational transconductance amplifier and capacitor
(OTA-C) has been analyzed using Taylor series expansion. Unfortunately, this approach
does not predict the frequency-dependent linearity degradation. Thus, to properly design
linearized OTAs, the frequency dependence of these coefficients must be determined. In
this paper, we present a frequency-dependent harmonic-distortion analytical method
applied to a linear-enhanced OTA. This OTA, which is suitable for high-frequency
operation, uses three linearization techniques simultaneously: 1) attenuation through
floating-gate MOS transistors; 2) source degeneration; and 3) polynomial cancellation
techniques. By using the harmonic-distortion analysis, some properties on the
performance of OTA are used to improve the performance of OTA-C based circuits at
high frequencies. A 0.5- m CMOS OTA simulation and experimental results are shown to
verify the harmonic-distortion analytical method.
LEARNING
A high-frequency harmonic-distortion analysis of weakly nonlinear OTAs is presented.
From this analysis, it has been shown that the high-frequency linearity degradation of the
linearized OTA topologies discussed is proportional to the OTA’s operation frequency,
which is verified by both simulations and experimental results. A third-order filter
employing the linearized OTA is also demonstrated to achieve good linearity at high
frequencies. Highlights of this paper are as follows.
1) A frequency-dependent harmonic-distortion method has been employed and verified
for two different OTAs; the results of the analytical expression provide a fundamental
prediction and design criteria for this type of OTA.
2) It is shown that the FGMOS OTA improves linearity up to 10 dB at 20 MHz in
comparison with an equivalent OTA without FGMOS.
3) It is demonstrated that the FGMOS OTA can achieve high linearity at high
frequencies with modest power consumption
PROJECT PRPOSAL
In above paper It is shown that the FGMOS OTA improves linearity up to 10 dB at 20
MHz and proposal is to improve the linearity at higher frequencies
REFERENCES
[1] J. Silva-Martínez, J. Adut, J. M. Rocha-Perez, M. Robinson, and S. Rokhsaz, “A 60-
mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic
tuning system,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 216–225, Feb. 2003.
[2] A. Veeravalli, E. Sánchez-Sinencio, and J. Silva-Martínez, “A CMOS
transconductance amplifier architecture with wide tuning range for very low frequency
applications,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 776–781, Jun. 2002
 3. 0.9-V Class-AB Miller OTA in 0.35-μm CMOS With Threshold-
Lowered Non-Tailed Differential Pair
INTRODUCTION
THE widespread diffusion of portable electronics demanding for low-voltage low-power
capability has led to a prolonged research effort towards circuit solutions and design
techniques under more and more stringent requirements. In the field of analog circuits,
the most basic yet challenging building block is the operational amplifier. Due to the
reduction of the supply voltage and/or the standby current budget, operational amplifiers
mainly suffer from limited dynamic range, bandwidth and settling time, especially when
low-cost high-threshold-voltage CMOS technologies have to be used. 1-V or even less
CMOS operational transconductance amplifiers (OTAs) have been designed using several
techniques.
LEARNING
This paper presents a CMOS operational transconductance amplifier (OTA), suitable for
sub-1-V supply applications, whose (input) common-mode voltage can be set to (VDD +
VSS)/2 thanks to two combined techniques applied to the differential pair, namely,
threshold voltage lowering and elimination of the tail current generator. Both techniques
are implemented through a single common-mode feedback loop, which embeds the
shared bulk terminal of the pair. In contrast to other low-voltage approaches employing
bulk driving, the proposed OTA is driven from the gate terminals and exploits only MOS
transistors in strong inversion. Therefore, effective values of dc gain, gain bandwidth, and
noise are found, suitable for high-accuracy switched-capacitor applications. Using a
standard 0.35-µm technology with nominal MOS transistors threshold around 0.7 V.
PROJECT PRPOSAL
The above proposed 0.9V class AB Miler Operational transconductance amplifier was designed
0.35um CMOS technology With Threshold-Lowered Non-Tailed Differential Pair. our
proposal is to simulate 0.9v class Operational transconductance amplifier on 180nm CMOS
technology

The gain of the of the above 0.9V class AB Miler Operational transconductance amplifier is 65db
our proposal is to increase the gain upto 90dB.

REFERENCE
[1] E. Cabrera-Bernal, S. Pennisi, A. D. Grasso, A. Torralba, and R. G. Carvajal, “0.7-V
three-stage class-AB CMOS operational transconductance amplifier,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 63, no. 11, pp. 1807–1815, Nov. 2016.
[2] O. Abdelfattah, G. W. Roberts, I. Shih, and Y.-C. Shih, “An ultralow-voltage CMOS
process-insensitive self-biased OTA with rail-to-rail input range,” IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 62, no. 10, pp. 2380–2390, Oct. 2015.
 4. High-Performance Four-Stage CMOS OTA Suitable for Large
Capacitive Loads
INTRODUCTION
With The degradation of the transistor's intrinsic gain in scaled-down CMOS
technologies, multistage amplifiers have become increasingly exploited in recent years,
since they provide very high DC gains without sacrificing output swing. Indeed, many
modern applications require high-gain and fast-settling operational transconductance
amplifiers (OTAs) driving off-chip loads in the order of hundreds (or even thousands)
picofarads, such as high accuracy modulators, analog-to-digital converters, low-dropout
regulators, LCD display drivers and headphone drivers. Battery-operated portable
systems integrate most of these blocks and, in addition, they work under tight power and
area budgets. In this context the design of high-gain OTAs driving heavy capacitive loads
is a challenging task, especially when nanometers technologies are adopted, as they suffer
from a drastic reduction of the intrinsic gain that can be only partially mitigated by the
adoption of non-minimum channel length transistors. In principle, stacked-device (i.e.,
cascoded) topologies provide high DC gains but they reduce the output swing and have
been progressively abandoned for this reason viable solution to get DC gains in excess of
80 dB in scaled technologies is the adoption of multistage architectures, where simple
gain stages are exploited.
LEARNING
Designing four-stage operational transconductance amplifiers (OTAs) is often considered
a challenging task mainly because of the required non trivial frequency compensation
procedure. In this study, starting from the simplest architecture (a differential stage
cascaded by three common source stages) a high-performance OTA is demonstrated,
outperforming all the (few) previous implementations. Thanks to the frequency
compensation scheme and to the adoption of a slew-rate enhancer section, the solution is
able to drive large capacitive loads as high as 1 nF, rivaling in terms of bandwidth and
speed even with three-stage counterparts, traditionally credited to be better because of the
less number of high-impedance nodes. The solution, fabricated in a 0.35- technology,
occupies 0.014- with DC consumption of 170. It also achieves nearly 3-MHz gain
bandwidth product while driving the 1-nF load with less than 0.5- 1% settling time
PROJECT PRPOSAL
The above proposed circuit was designed in 0.36um technology and our proposal is to
design the proposed circuit in 180nm technology.
REFERENCE
[1] Z. Yan, P.-I. Mak, M.-K. Lau, and R. P. Martins, “A 0.016-mm 144- Three-stage
amplifier capable of driving 1-to-15 nF capacitive load with 0.95-MHz GBW,” IEEE J.
Solid-State Circuits, vol. 48, no. 2, pp. 527–540, Feb. 2013.
[2] M. Tan and W.-H. Ki, “A cascode Miller-compensated three-stage amplifier with
local impedance attenuation for optimized complex-pole control,” IEEE J. Solid-State
Circuits, vol. 50, no. 2, pp. 440–449, 2015.
 5. 0.7-V Three-Stage Class-AB CMOS Operational Transconductance
Amplifier
INTRODUCTION
ONE of the main trends of modern consumer electronics industry is towards the extension
of portable devices autonomy through the adoption of low power design technique. This
has reinforced the interest in the development of low-voltage design approaches and
techniques for the limitation of power consumption. Considering the CMOS technology,
the most straightforward methodologies to enable operation below 1-V supplies are
subthreshold biasing and bulk driving (or body driving) and even a combination of both
Subthreshold transistors can be biased with currents in the range of a few nanoamperes,
but this also implies low unity gain frequency and low achievable slew rate values.
Therefore, subthreshold operation is particularly suitable in wireless sensor networks,
biomedical applications and in all those applications where speed is not a concern, e.g.,
for bandwidth specifications in the range of a few kilohertz
LEARNING
A simple high-performance architecture for bulk driven operational transconductance
amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single
supply, is made up of three gain stages and, as an additional feature, provides inherent
class-AB behaviour with accurate and robust standby current control. The OTA is
fabricated in a 180-nm standard CMOS technology, occupies an area of 19.8 · 10−3 mm2
and is powered from 0.7 V with a standby current consumption of around 36 μA. DC gain
and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of
20 pF. Overall good large-signal and small-signal performances are achieved, making the
solution extremely competitive in comparison to the state of the art.
PROJECT PROPOSAL
The above proposed of 0.7-V Three-Stage Class-AB CMOS Operation Transconductance
Amplifier circuit is design on standard 180nm CMOS Technology and our proposal is to
simulate the proposed circuit on standard 135nm technology.
TOOL REQUIRED- Cadence or Hspice

REFERENCE
[1] T. M. Hollis, D. J. Comer, and D. T. Comer, “Optimization of MOS amplifier
performance through channel length and inversion level selection,” IEEE Trans. Circuits
Syst. II, Express Briefs, vol. 52, no. 9, pp. 545–549, Sep. 2005.
[2] T. Kulej, “0.5-V bulk-driven CMOS operational amplifier,” IET Circuits Dev. Syst.,
vol. 7, no. 6, pp. 352–360, 2013
6. Comparison of the Frequency Compensation Techniques for CMOS
Two-Stage Miller OTAs
INTRODUCTION
IN Order To achieve stability in closed-loop conditions, Miller compensation techniques
are usually adopted both in CMOS and bipolar technologies. Unfortunately, the adoption
of a pure Miller compensation approach is responsible for a right-half-plane zero in the
open-loop gain due to the forward path through the compensation capacitor to the output.
Thus, improved solutions that avoid the right-half-plane zero have been proposed both for
two-stage and three stage CMOS amplifiers. In particular, there are many compensation
approaches for three-stage amplifiers available for the designer. These can be generally
seen as variants of two basic ones termed the nested Miller and reversed nested Miller.
However, only recently an in-depth analysis was carried out to compare them analytically
and outline the conditions in which one particular technique is better suited than another
one. Surprisingly, a similar analysis and theoretical comparison of the Miller
compensation topologies for two-stage amplifiers is still lacking.
LEARNING
Several design options are nowadays available for the frequency compensation of CMOS
two-stage transconductance operational amplifiers, from the traditional Miller approach
employing a nulling resistor or a voltage buffer, to a current buffer or the more modern
current amplifier. However, designers have no results on the frequency performance
achievable that allow to consciously choose the best approach to meet the prescribed
specifications efficiently. In this paper, a comparison among the possible Miller
approaches is carried out by exploiting an analytical figure of merit that expresses a
tradeoff between gain--bandwidth product, load capacitance, and total transconductance
for a given value of phase margin. Interesting and useful results, even unexpected, are
found. The accuracy of the comparison is also validated through simulations.
PROJECT PROPOSAL
Our proposal for the above paper is to minimize the drawback of reducing the amplifier output
swing incurred by the voltage buffer.

REFERENCES
A. D. Grasso, G. Palumbo, and S. Pennisi, “Analytical comparison of frequency
compensation techniques in three-stage amplifiers,” J. Circuit Theory. Appl., vol. 36, no.
1, pp. 53–80, Jan. 2008.
[19] W. Aloisi, G. Giustolisi, and G. Palumbo, “Design and comparison of very low-
voltage CMOS output stages,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8,
pp. 1545–1556, Aug. 2005
 TOPIC-3
TWO STAGE OP AMP
1. A New Two-Stage Op-Amp Using Gate-Driven, and Positive
Feedback Techniques
INTRODUCTION
Since Op-Amps play important role in analog circuits, nowadays researchers focus on
designing highly efficient Op-Amps. High-gain and high-speed Op-Amps are needed for
different applications such as high resolution ADCs and DACs, voltage references, and
sample-and-hold circuits. In new submicron technologies because of low supply and
overdrive voltages, designing high-gain circuits has become difficult. Different
architectures have been proposed during the last few decades. Telescopic amplifiers have
high-gain and are very fast but they need large voltage headroom. Folded cascode
structures provide large output swing while on the other hand they suffer from high power
dissipation and low phase margin also their stability is complicated. Two-stage Op-Amps
have good gain and large swing in small voltage headroom. However because of their
extra zeroes and poles this family of Op-Amps needs internal compensation. If they do
not compensate properly, they can easily become unstable.
LEARNING
This paper describes the design and simulation of a new high-gain, low-power two-stage
Op-Amp in a O.18um CMOS technology. Using both the gate-driven transistor and
positive feedback concepts, the DC-gain of the conventional two-stage Op Amp is
increased about 20dB while power dissipation is approximately unchanged. Both the
analytical and simulation results show that although the DC-gain will increase about
20dB but no significant change will be made in the unity-gain bandwidth of the circuit.
Besides, the settling behavior of the proposed circuit is verified by employing the Op-
Amp in a flip-around sample-and hold. It is shown that the proposed Op-Amp has better
settling behavior than its conventional counterpart.
PROJECT PROPOSAL
I will try to increase gain of the above proposed op amp greater than the 20dB while
power dissipation is approximately unchanged by scaling and changing aspect ratio. In
above proposed op amp are simulated in 0.18um CMOS technology. and I will try to
simulate above proposed op amp on 90nm CMOS technology.
Tool required- Cadence or HSPICE
REFERENCES
M. Yavari " Hybrid Cascode Compensation for Two Stage CMOS Op-Amps" IEICE
trans. Electronics, voI.E88-C,No.6,pp 1161,1165 2005.
 2. Positive feedback technique and split-length transistors for DC-gain
enhancement of two stage op-amps
INTRODUCTION
Op-amps are an essential component in the modern mixed-signal systems. High-gain and
high-speed op-amps can be used in the various applications such as high-resolution
analogue-to-digital converters and digital-to-analogue converters, bandgap voltage
references and sample-and-hold amplifiers. Designing a complementary metal–oxide–
semiconductor (CMOS) op-amp that combines both high DC gain and high unity-gain
bandwidth (UGBW) has proven to be a difficult task, especially in low-voltage circuits.
Cascoding of transistors with long channel devices biased at low current levels is needed
to achieve high DC gain. On the other hand, single-stage design with short channel
devices biased at high bias current levels is required to obtain high UGBW
LEARNING
This study presents the design and simulation of a fully differential two-stage op-amp in a
0.18 μm complementary metal–oxide–semiconductor process with a 1.8 V supply
voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs)
are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the
unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of
the conventional two-stage op-amp. A comprehensive analysis is provided for
differential-mode gain, common-mode gain, power supply rejection ratio, input-referred
noise, input offset, frequency response and the effect of using SLTs on DC-gain
sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier
(SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%.
The post-layout and Monte Carlo simulation results show that the proposed op-amp has
better performance than the state-of the-art design.
PROJECT PROPOSAL
In the above proposed two stage op amp I will try to increase the DC gain of the op-amp
greater than the 22dB without affecting the unity gain bandwidth product, stability, power
dissipation and output voltage swing of the conventional two stage op amp the above
proposed op amp are simulated on 0.18um CMOS technology and I will try to simuate the
above proposed two stage op amp on 90nm or 65nm CMOS Technology.
Tool Required- Cadence or HSPICE
REFERENCES
[1] Asloni, M., Hadidi, K., Khoei, A.: ‘Design of a new folded cascode op-amp using
positive feedback and bulk amplification’, IEICE Trans. Electron., 2007.
 3.A Low-Power, High-Speed, Current-Feedback Op-Amp with a Novel
Class AB High Current Output Stage
INTRODUCTION
AN increasing number of video and communication applications require line or cable
driver circuits that can provide high peak output current with large bandwidth and low
distortion while operating on low quiescent current and low supply voltage of 5 V or 5 V.
This requirement is well served by complementary bipolar amplifier circuits. An excellent
review of modern complementary bipolar high-speed monolithic operational amplifiers,
including current-feedback op-amps. A simplified circuit schematic of a typical modern
complementary bipolar high-speed current feedback op-amp. The basic elements of the
architecture are unity gain input buffer, current mirror gain stage, and unity gain output
buffer. Complementary emitter followers Q1–Q4 form the input buffer. The collector
signal currents of transistors Q3 and Q4 are turned around and summed through Wilson
current mirrors formed by Q5–Q7 and Q8–Q10, respectively. This signal current injected
into the high impedance node sets the open-loop gain of the amplifier. The output buffer
(Q13–Q16) provides near unity voltage gain and isolates the high impedance current
summing node from the amplifier load. The single gain stage architecture provides high
bandwidth at the expense of open-loop transimpedance. The loss of dc accuracy is usually
acceptable in the high-speed applications in which these amplifiers are employed.
LEARNING
A complementary bipolar low-power, high-speed, current-feedback operational amplifier
is described. The amplifier incorporates a new Class AB output stage that enables high
output current drive of 100 mA and large voltage swing within 1 V of the supply rails
while operating at low quiescent current of 1.5 mA. The amplifier was fabricated in a
junction-isolated complementary bipolar process with NPN/PNP ft of 4.5/3.8 GHz. The
amplifier, configured for noninverting gain of two and 100- load, provides 3-dB
bandwidth of 110 MHz and 2-V pulse rise time of 7 ns.
PROJECT PROPOSAL
Above paper is proposed that A simplified circuit schematic of a typical modern
complementary bipolar high-speed current feedback op-amp I will try to improve the
speed and gain of the propose circuit.
TOOL REQUIRED – Cadence or Hspice
REFERENCES
D. Smith, M. Koen, and A. F. Witulski, “Evolution of high-speed operational amplifier
architectures,” IEEE J. Solid-State Circuits, vol. 29, no. 10, Oct. 1994.
 4. Distortion in Single-, Two- and Three-Stage Amplifier
INTRODUCTION
CMOS technology moves steadily toward finer geometries, which offer higher capacity
for digital circuits and higher level of system integration. However, the analog part of
such systems suffers from the low supply voltage required by these technologies. To
maintain the signal-to-noise-ratio (SNR) it is important that the signal swing is as large as
possible and thus occupies a large portion of the supply voltage. The voltage left to bias
the circuit becomes smaller, which makes the design for low nonlinear distortion
especially challenging. Further, integrated radio systems, such as wireless LAN and
Bluetooth, demand high linearity in a rather large bandwidth. Thus, the nonlinear
behavior of analog building blocks has to be analyzed and described not only at dc and
low frequency but also at frequencies above poles and zeros caused by the analog circuit
LEARNING
Nonlinear distortion in single-, two-, and three-stage operational amplifiers (opamps) is
the main scope of this paper. For each opamp, distortion contributions from different
groups of transistors are identified and plotted versus frequency. This makes it possible to
find the strongest sources of distortion in the various frequency regions. Further,
equations that describe the third harmonic as a function of circuit parameters and input
frequency are presented. Despite the simplifications, these equations describe the third
harmonic accurately. Further, they provide insight and understanding by connecting
distortion to circuit parameters such as transconductances, capacitances, poles, and zeros.
The comparison of the opamps shows that each opamp has a frequency region where the
distortion is lower than for the other two. The three-stage opamp has far lower distortion
at low frequencies, the single-stage opamp is better at high frequency and the two-stage
opamp is best for the mid frequency range.
PROJECT PROPOSAL
In above paper, the nonlinear distortion for single-, two, and three-stage opamps has been
investigated and discussed. I will try to simulate the circuit on low power consumption by
scaling.
TOOL REQUIRED- Cadence or Hspice

REFERENCES
C. Beainy, R. A. Baki, and M. N. El-Gamal, “Distortion analysis of high frequency log-
domain filters using volterra series,” in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, 2001,
pp. 472–475.