MARKET SURVEY RELATED TO CMOS’IC

Abstract

The research works provides with guidelines about why to invest their time in field of VLSI & ULSI technology and
enlighten them about various parameters of Scaling of CMOS technology which is the most used IC technology in the
world. This work also studies the range of scaling of MOSFET and its limits. Performance of a device relies highly on the
performance of IC and Transistors used in its circuit hardware.
CMOS which is abbreviation of Complementary Metal Oxide Semiconductor is a technology used to design Integrated
Circuits. The Complementary prefix to MOS that refers to MOSFET signifies the use of complementary semiconductors
that is NMOS and PMOS. These two MOS technologies work together to form wide array of gates and Integrated
Circuits.
This research work provides various results on unreliability of Student Version Simulation software in designing new
generation hardware and how power dynamics of highly scaled technology cannot be verified using such tools.

1. Introduction

The idea of CMOS Technology came into existence in 1963 in a Conference paper published by C. T. Sah and
Frank Wanlass of the Fairchild R & D Laboratory. Paper claimed that when a P channel MOSFET and a N
channel MOSFET are placed as pull up and pull-down position there is no static power dissipation and only
dynamic power dissipation during switching. This makes CMOS technology far more superior to others such
as NMOS, PMOS, and TTL technologies.

1.1. Advancement of Tech Industry

Advancement of Tech industry was driven by improvements made in performance of CMOS technology
which led to boom in tech industry due to decreased size and high efficiency of these IC’s fitting in more and
more transistors on smaller scale resulting to birth of VLSI, ULSI, etc. As stated by Moore’s law that number
of transistors on a chip will double every couple year [1]. As fundamental of our technology gets smaller,
faster and uses much less power.

1.2. End of Moore’s Law

 Figure 1. Moore’s Law Curve representing [1]

This leaves with a question to what extent can we trim the size and voltage levels of our IC’s so that they don’t
start to malfunction [2]. At present companies like Intel are trying manufacturing FinFET transistors at 14nm
size only 70 times wider than the diameter of silicon. The limit for CMOS Technology is at 20nm Technology
because of Quantum Effects, because properties of materials such as silicon cannot be predicted at a quantum
level. This could halt the future development of Tech industry.

1.3. Advantage of CMOS

CMOS technology has a major advantage over other technologies (such as TTL, RTL, NMOS etc.) that are
given below as it has: -
• High Noise Margin
• Low Static Power Dissipation
• Fast Switching Speed
• Thermal Efficiency

Performance Analysis of CMOS Technology 3

Power Consumption in CMOS logic is very low due to lack of direct path between V dd and Ground. This leads
to negligible Static and Dynamic Power Dissipation, because at a time only one MOSFET is active. This

is due to the presence of MOSFET for both pull up and pull-down mechanism which acts as a switch while
output varies from high to low and low to high.

1.4. Technology of CMOS

When we talk about terms like 75nm technology or 14nm we are considering the Gate Length of the
Transistor. Different Technologies in VLSI are based on their minimum Gate Length of transistor and defines
much of its parameters. But in current generation size technology refers to minimum feature size of DRAM.
2. Literature Survey

Scaling refers to reduction in size of Transistor to meets demand of high density and economical chips for an
IC. Scaling of transistor depends on a Scaling Factor ‘S’. ‘S’ is introduced expecting a change in properties of
Transistor.

2.1.Types of Scaling

In [1], the author studies about the type Device scaling i.e.:
1. Constant Field Scaling
2. Constant Voltage Scaling

To maintain the power performance and a high speed of the device, the power supply as well as the threshold
voltage must be scale down in proportion to the channel length; this is called Constant Field Scaling.

Voltage Parameters such as Supply and Threshold Voltage are not changed and hence it is geometrical process;
this is called Constant Voltage Scaling.
Due to high power loss and higher fields Constant Voltage Scaling is not preferred in VLSI.

Fig 2 Scaling Parameters

2.2.Power Dissipation in CMOS

Before scaling our transistors, we must know about different power losses in CMOS due to change in
dimensions and other parameters of MOSFETS. In [3], it is described Power Consumption in CMOS logic is
very low due to lack of direct path between Vdd and Ground. This leads to negligible Static Power

Dissipation and Dynamic Power Dissipation, because at a time only one MOSFET is active.

2.3.Static Power Dissipation

Static Power losses in CMOS arise due to reverse leakage current through supply which is very minimal
because in Static MOSFET’s are either ON or OFF as they are not switching. There is a negative leakage
current between Drain and Source of two transistors[3].

Pstatic= Vdd x Ileak (1)

This Leak of current is due to Sub Threshold Current in MOSFET’s as shown in below in the graph of Ids
Vs Vgs of NMOS whose threshold voltage is set to 0.8v, that there is flow of current before V th (0.8V). It is
called Sub threshold Current. In Fig we can see a s mall amount of leakage current. This current is called Ioff
as it flows when MOSFET is in OFF state. This Ioff leads to Static Power Dissipation in MOSFET. To minimize
this Static Power Dissipation Ioff. To decrease this Ioff threshold voltage Vth has to be increased or W/L ratio has
to be decreased as:

Ioff= 100* W/L* e (-qVt/KT) (2)

Here; K= Boltzmann’s Constant & T= Temperature

Fig 3 Leakage Current in MOSFET

2.4.Dynamic Power Dissipation

Dynamic Power Dissipation occurs when MOSFET’s are switching from On to Off state or OFF to ON state.
This switching speed depends upon the frequency of the input signal. Dynamic Power Dissipation is directly
proportional to voltage of power supply and Load Capacitance at output of CMOS.

Pdynamic=CL×Vdd2×F (3)
It depends on number of times Output Capacitor is charged and discharged in a CMOS circuit. Hence
Dynamic power dissipation can be curbed by reducing parasitic output load capacitance and by decreasing
voltage of power supply.
In [3], author describes limits to the Constant Field Scaling. As though seen in table 1, power dissipation is
reduced by a factor of ‘S’ along with other parameters but when size of MOSFET reach a Nanometer range
there are certain effects such as Short Channel Effect, Impact Ionization, etc. To maintain the power
performance and a high speed of the device, the power supply as well as the threshold voltage must be scale
down in proportion to the channel length [8]. However, a decrease in threshold voltage increases the leakage
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current i.e. Ioff that leads to increases in static power dissipation of the device[9]. Below given figure is Visual
representation of Dynamic Power Dissipation when CMOS is switching from high to low.

Fig 4 Dynamic Power Loss in CMOS

2.5.Noise Margin
[5] Cites that Noise Margin is a parameter which controls the speed of switching of a CMOS circuit. Noise
margin is the amount of noise that a digital circuit could tolerate without compromising its function. Higher
Noise Margin of a system means it switching is more rapid when between stages and results to less Dynamic
Power Dissipation [6].

Fig 5 Noise Margin Parameters

NMH =VOH − VIH Noise Margin High

NML =VIL − VOL Noise Margin Low
The striped region in the above figure is described as Noise Margin of CMOS as it is region of tolerance of
Noise. VOH, VOL, VIH, VIL are output high voltage, output low voltage, input high voltage and input low
voltage, respectively.

Fig 6 Noise Margin on a VTC

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Noise Margin of a Transistor depends on following values: - •

Threshold Voltage (Vt)
• Supply Voltage (Vdd)
• Switching Threshold Voltage (Vm)

3. Research Findings

With scaling CMOS technology to smaller scales and Moore’s Law failure, the bid to keeping up with
shrinking of sizes of our circuits depends upon other means such as Machine Learning, Quantum Computing,
and other MOS technologies. But we cannot rely on Simulation Software such as Virtuoso and VHDL on
Spice for upcoming technology as they do not account for effects on quantum level of transistors which
disrupts the functioning of current technology [8]. Such as Hot Electron Effect, Impact Ionization, Short
Channel Effect. When the dimensions of a MOSFET are scaled down both Voltage and Oxide Thickness must
be reduced as well which brings operational voltage to the range of thermal voltage which leads to Leakage
Current.
Power dissipation at switching in 75nm technology is higher than at 2nm technology. But 2nm technology is
not feasible due to Short Channel Effects. Thus, creates variations in simulations and real-life operations of
CMOS. Thus, deeming software’s which are for students (open source) less usable for studying upcoming
technologies.

3.1.Switching Threshold

Switching Threshold Voltage is a point on VTC curve where Vin= Vout. Formula for Switching Threshold: -
At Vin = Vout, for both NMOS and PMOS

VM= VTn + r(VDD-VTp)/(1+r) (4)

Here: -
r= (Kp/Kn)½ (5)

For a smooth operation, high switching speed and High Noise Margin: -

VM= VDD/2 (6)

So, r =1 and VTn = VTp

Fig 7 Switching Threshold Representation

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Hence Threshold Voltage should be set at half of Supply voltage and threshold of both NMOS and PMOS
should be equal for high noise margin.
Fig 9 is VTC curve of a CMOS inverter; Vt=0.75V.
Fig 10 is VTC curve of CMOS inverter; Vt=2.5V and supply voltage Vdd=5V.
We can see transmission is instantaneous when threshold voltage is set to half of Supply Voltage and
Threshold of both NMOS and PMOS are equal. Yellow line cuts VTC at Switching Voltage

Fig 8 VTC at 0.75V

Fig 9 VTC at 2.5V

Graph in Fig 10 is derived from setting various Threshold Voltage for a Supply of 5v, to calculate the Noise
Margin of each curve. Hence confirming that Noise Margin is highest when: -

Vth=Vm=Vdd/2 (7)
Fig 10 Noise Margin VS Threshold
3.2.Dimensions of MOSFET

Drain Current Id is the defining parameter of MOSFET. In a CMOS circuit MOSFET’s function is switching
between OFF state and Saturation state and act as a switch.
In Linear Region: -
Ids= K*(W/L)[(Vgs-Vt)*Vds-(Vds)2/2] (8)
In Saturation Region: -
Ids= K*(W/2L)[Vgs-Vt]2 (9)
We can see Drain Current depends upon the size of the MOSFET i.e ratio of W/L. So the length of the Gate is
indirectly proportional to charge flowing through the channel. This is due to Transconductance of the
channel:-
Gm= (Cgu/L2)*(Vgs-Vt) (10)
Cg is Capacitance of Gate oxide
Gm α W/L (11)
In [5], with higher Transconductance faster flow of charges occurs which in turn lead to faster switching and
better performance of circuit.

Fig 11 VTC at 75nm

In below Figure 11 and 12 Threshold voltage is set to half of supply voltage, but the length of gate is set to
1um in Fig 12, so we can clearly see a little deviation from perfect transfer curve of an inverter .
 Fig 12 VTC at 1um

3.3.Effects of Parameters on SRAM Cells

SRAM cells are basic block of Static RAM used as Cache Memory, ROM, etc. The most basic SRAM cell
consists of 6 MOSFETS, 4 NMOS and 2 PMOS. They are implemented by cross-coupled CMOS inverters as
shown

Fig 13 Schematic of a 6T SRAM Cell

Plotting a graph of power dissipated through MOSFETS against the temperature gives efficiency of our
SRAM cell when varied in Gate Size or Technology used.

Fig 14 Power Loss at 10nm

Fig 15 Power Loss at 1nm

 -

Fig 16 Power Loss at 0.1nm

The Figures 14, 15, 16 are curve of power leakage in a SRAM cell against the temperature range of -10̊̊ C to
55C. Following the Constant Field Scaling Technology in Figure 14 is of 100nm, which is th ֯en scaled to
10nm, 1nm and 0.1nm in figures 14, 15, 16 respectively. We can see at Size 10nm the dissipation of power is
almost half of at 100nm. At Gate length of 1nm the curve gets non linear and leading to uncertain power
losses, at 0.1nm Gate length from moderate to high temperature graph is very non linear and fluctuations are
rampant.

4. Future Work

With MOSFET technology’s failing to follow Moore’s law designing of more compact and faster system lies
with new technology such as CNT-FET (structure shown in Fig. 18) which is abbreviation for Carbon Nano
Tube Field Effect Transistor. This came as an alternative to double gate MOSFET. In [6][7], a carbon nanotube
field-effect transistor (CNT- FET) refers to a field-effect transistor that utilizes a single carbon nanotube or an
array of carbon nanotubes as the channel material instead o bulk silicon like in the MOSFET structure. In
Nano meter scale CNTFET is being preferred over MOSFET due to lesser Quantum Capacitance.

Fig 17 Structure of CNT- FET

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5. Conclusions

Open source simulation software is unable to produce verifiable results for new generation technologies which
lie in Nano Meter regime as it is unable to account for Quantum Losses and variables. CMOS is reaching its
limit for scaling and for higher density designs. Students should focus on new technologies such as Carbon-
Nano Tube, etc. As Power Dissipation and size of a Transistor are two most important parameters in design of
a circuit. For a chip with few such transistors, power loss may not be very noticeable, but in field of VLSI and
ULSI, where thousands to millions of chips might comprise a circuit marginal power loss in each transistor
can add up to a large value and hence increase power demand, low battery life of devices and worse
temperature efficiency.