International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882

Volume5, Issue4, April 2016

FAST AND WIDE RANGE VOLTAGE CONVERSION IN

MULTISUPPLY VOLTAGE DESIGNS
Shrikant Adinath Narute, Prof. Shailesh Jadhav
Department of Electronics and Telecommunication,
Savitribai Phule Pune University, Pune

Abstract Level shifter (LS) is inserted between

two modules when low voltage drives high voltage
modules. Multi supply voltage is used to reduce the
static and dynamic power consumption. Multi supply
voltage domain (MSVD) technique consists of
portioning the design into separate voltage domain. So
the time critical domain runs at higher power supply
voltage where non-critical domain is runs at lower
power
supply
voltage.
The
conventional
multithreshold CMOS (MTCMOS) greatly reduces the
leakage power. But it does wide voltage conversion
range is not achieved in level shifter design. So we use
a multiple level shifter instead of single level shifter
with multi threshold CMOS device. The multiple level
shifter design can be achieved the conversion voltage
range of 180 mV to 1V. Post layout simulation results
demonstrate that the new level shifter shows a
propagation delay of 16.6ns, a static power dissipation
of 8.7nW and total energy per transition of only 77fJ.
It can be designed by using 90nm technology.
Keywords Level shifter (LS), multisupply voltage
design (MSVD), subthreshold operation, ultra low
power.

I. INTRODUCTION
Energy efficiency is one of the most important
issues to address in todays System-on-Chip designs.
Among the techniques known in the refered papers to
reduce power consumption, those based on power
supply voltage reduction are considered very effective
even though they can severely penalize speed
performances.
An alternative approach, known as the multi-supply
voltage domain technique which consists of
partitioning the design into separate voltage domains
(or voltage islands), each operating at a proper power
supply voltage level depending on its timing
requirements. Time-critical domains run at higher
power supply voltage (VDDH) to maximize the
performance, whereas noncritical sections work at
lower power supply voltage (VDDL) to improve
power efficiency. For extremely low-power
applications, the presence of sections of the system
operating in a sub-threshold regime is a valuable
option. A key challenge in the design of efficient

multiple-supply circuits is minimizing the cost of

the level conversion between different voltage
domains while maintaining the overall robustness of
the design. To such a purpose, level shifter (LS)
circuits have to be used. To down-convert from a
higher voltage (within the oxide breakdown limits) to a
lower voltage domain, CMOS inverters are usually
adequate. On the contrary, more complex LS
topologies are required to up-convert signals from the
lower to the higher power supply domain. The issue is
particularly compounded when the VDDL is lowered
below the transistors threshold voltage. In fact, in
such a case, balancing the input section driving
capability of the LS with sections of the circuit
working at the VDDH voltage level requires proper
design techniques.
There are different type Level Shifters which are
designed for conversion of voltage in Multisupply
Voltage Design but they have some drawback which
overcomes by proposed level Shifter. This design
gives the high speed performance and that also
consume low static and dynamic power. Conventional
level shifter unable to convert subthreshold voltage
level to above threshold voltage level. Proposed level
shifters are capable to do this with fast and wide range.
In System on chip design power consumption is
important issue to reduce power leakage by static and
dynamic power consumption is controlled by
technique that is multisupply voltage design in that
technique voltage conversion is done by level shifter.
But aim is that conversion should be fast and wide
range.

II. PROPOSED DESIGN

A. System Architecture
The system LS was designed using the commercial
90-nm CMOS ST Microelectronics process
technology. The latter provides the designer with lowvoltage threshold (lvt), standard voltage threshold
(svt), and high-voltage threshold (hvt) transistors. As
shown in Fig.1, the novel circuit consists of an input
inverter, a main voltage conversion stage, and an
output inverting buffer.

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236

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume5, Issue4, April 2016

Fig.1. Proposed LS design

To provide fast differential low-voltage input signals,
the input inverter was created using lvt devices. To
increase the strength of the pull-down network of the
main voltage conversion stage, it was also designed by
using lvt transistors. The cross-bar current flowing
through the nodes NH and NL at the beginning of their
high to low transition could be of concern. Thus, to
reduce this effect, two lvt PMOS devices (MP2 and
MP3) are adopted.
MP4 and MP5 were chosen as hvt transistors. This
helps in weakening the pull-up networks of the main
voltage conversion stage, thus reducing contention at
NH and NL nodes. This choice also reduces the
leakage current flowing through the pull-up networks
when they are turned off. Finally, to ensure reliable
voltage conversion, two diode-connected hvt PMOS
devices (MP6 and MP7) were placed between the pullup logics and the supply rail VDDH. These devices
limit the pull-up strength, but also lead to considerable
reduced static power. now briefly describe the running
of the proposed circuit with particular attention to the
differences between the new architecture and the
conventional DCVS one. A high to low transition of
the main input causes MP4 being turned on. Its drain
current brings the diode-connected MP6 device into
the saturation region. This creates a voltage drop
(i.e.Vth,MP6) across MP6 terminals that produces a
correspondent bulk source voltage drop on MP4. Due
to the bulk effect, this increases the MP4 threshold
voltage. The reduced voltage level (VDDH-Vth, MP6)
on the source terminal of MP4 limits its VGS, thus
further weakening the MP4 action. All the above
effects reduce the contention on the node NH, thus
allowing faster discharging to be achieved.
When MP4 is turned on, MP5 is consequently
turned off. In this case, the small leakage current
flowing through MP5 is not enough to turn MP7 on.
For this reason, MP5 results power gated from the
VDDH power rail, leading to a significant reduction in

its sub-threshold current. The diode connected MP7

device participates in minimizing the leakage current,
also by increasing the threshold voltage of MP5. In
fact, MP7 causes the source of transistor M5 to be at
lower voltage than the bulk node and thereby reduces
the sub-threshold leakage current due to the bulk
effect. Since MP6 limits the output range of the main
conversion stage to [0 V, VDDH VTp], an output
inverter is connected to node NH, to assure a rail-torail conversion. The pull-down of such an inverter uses
an svt device, whereas its pull-up is designed by
exploiting an hvt PMOS transistors stack, thus limiting
the leakage current flowing through the pull-up
network of the output inverter, when NH is high.
Opposite and substantial threshold voltage variations
on MP6 and MP8-MP9 could, in theory, cause the
latter transistors to go in weak inversion, thus
increasing the static power dissipation.
Table I: Transistors Sizes
Transistor W/L(um) Transistor
MN1
0.3/0.1
MP4
MN2
1.5/0.2
MP5
MN3
0.9/0.2
MP6
MN4
0.36/0.2
MP7
MP1
0.45/0.1
MP8
MP2
0.3/0.2
MP9
MP3
0.18/0.1

W/L(um)
0.3/0.2
0.18/0.2
0.3/0.2
0.18/0.2
0.6/0.2
0.6/.02

In Table I, the transistors sizes used in the design of

the designed LS are reported. Transistors with a
channel length of 0.20m (twice the minimum allowed
channel length) were used in the main voltage
conversion stage and the output inverting buffer, to
reduce sub-threshold leakage currents. On the
contrary, since the leakage current is a minor issue for
the input inverter, it has been made with minimum
channel length devices, thus enhancing speed. It is
worth noting that the right branch of the main voltage
conversion stage is downsized with respect to the left
one because of the reduced load on the node NL.
In Fig. 2. illustrates the physical design of the
proposed LS. It exploits the double-cell-height layout.
Power supplies are available through the top and the
bottom metal-1 rails, while a shared ground rail travels
at the center of the cell. The width of the ground rail is
twice the width of the other rails in order to have
consistent abutment with neighboring single-height
standard cells. Note that the use of the double-height
layout strategy allows well-sharing between PMOS
transistors driven by the same power supply in
different standard-cell rows, thus leading to more
compact system layouts.

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237

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume5, Issue4, April 2016

Fig.3. PVT analysis of the propagation delay (in log

scale) versus VDDL

Fig. 2 Layout of Proposed Level Shifter

III. RESULTS AND DISCUSSION

A. Simulation Results
All the simulation result given below are refer from
the paper [7], the Cadence Spectre tool was employed
for the post-layout analysis. Simulations for three
process-voltage-temperature (PVT) corners were
performed considering the input signal frequency of 1
MHz, input signal rise- and fall-times of 10 ns, and
100 fF of capacitive load. The typical case corner
involves typical-NMOS and PMOS transistors, a 1-V
high supply voltage, and a temperature of 25C. The
worst case (WC) corner was determined considering
that, in a sub-threshold running condition, the weakly
driven pull-down NMOS transistors have to overpower
the corresponding pull-up PMOS devices. Thus, the
slow-NMOS, fast-PMOS are used in this case together
with an increased VDDH (1.1 V) that further worsens
the contention between pull-up and pull-down at nodes
NH and NL. Moreover, a temperature of 25 C was
considered, which implies weaker transistor operation
in the sub-threshold region. Finally, for the best case
condition fast-NMOS, slow-PMOS, VDDH = 0.9 V
and a temperature of 125 C was assumed. Obtained
simulation results are shown in Fig.3.

The novel circuit operates correctly for VDDL as

low as 0.18V for all PVT corners. When VDDL 0.35
V (i.e., the sub-threshold region is reached for the
chosen technology process), the propagation delay
exponential increases. However, the running frequency
of the proposed circuit is always maintained above 1
MHz. Fig.3. shows the plot of the operating frequency
as a function of VDDL. It is interesting to note that it
increases exponentially with VDDL in the deep subthreshold region because, in such operating conditions,
the strength of the pull down transistors MN2 and
MN3 exponentially depends on VDDL. Then, after a
further but slower increment in the near-threshold
zone, it saturates toward 100 MHz. This happens
because the balancing between the pull-up and pulldown strengths is altered when VDDL scaling
requirements are low (a large voltage level conversion
is not required).

Fig.4. Operating frequency versus VDDL at the typical

PVT corner

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume5, Issue4, April 2016

Fig.5 reports results from a 10000-run Monte Carlo

(MC) simulation performed considering both inter-die
and intra-die variations. The delay as shown in
Fig.5(a) and the static power dissipation shown in
Fig.5(b) are log-normally distributed, consistent with
the subthreshold regime.
Table II. Comparative results
Tech.

VD

Mim.

Dela

Etr.

DH

VDL

(pJ)

(v)

(ns)

Result

(v)

Fig. 4 Energy-per-transition (@ 1 MHZ) and static

power versus VDDL
Fig.4 illustrates the total energy dissipated per
transition as a function of VDDL, when an input signal
with a frequency of 1 MHz is assumed. The static
power consumption versus VDDL is reported in the
same figure. The designed circuit shows a relatively
wide flat energy minimum (for the VDDL ranging
from 200 to 400 mV). The consumed energy
significantly rises when VDDL = 180 mV because
short circuit effects become dominant. The static
power dissipation of the proposed circuit ranges from
6.3 nW (@VDDL = 180 mV) to 11.5 nW (@VDDL =
0.75 V). These results confirm the benefits brought by
the static current limiting design strategies used.

[6]

0.35um

0.23

10^4

5.8

Measured

[5]

0.18um

1.8

0.13

10^4

300

Measured

[3]

0.13um

1.2

0.18

57.9

N.A.

Measured

[1]

0.13um

1.2

0.1

50

25

Measured

[1]*

90mm

0.1

43.2

0.18

Pre-layout

3
[4]

90mm

0.1

18.4

0.09

Pre-layout

4
[4]*

90mm

0.1

*
Pro
pos

90mm

0.18

18.7

0.08

21.8

0.07

Pre-layout

Post-layout

ed

Fig.5. Monte Carlo simulation results@ VDDH = 1 V,

VDDL = 200 mV, and T = 25 C. (a) Delay
distribution. (b) Static power distribution.

B. Comparison of new LS with previously proposed

design
The characteristics of the new LS are compared in
Table-II. with previously proposed designs. The LS
proposed in [6] has been realized using a 0.35-mm
process. However, it exhibits a quite low-power
consumption. Unfortunately, this is obtained at the
expense of a very high propagation delay. On the
contrary, thanks to the use of the DTMOS technique,
the circuit exhibit considerable speed, but they
dissipate higher energy. The last four rows of Table II.
reports data from circuits designed using a 90-nm
process, thus they can be directly compared. In
particular, the circuit discussed in [1] and implemented
in a 90-nm technology process by Ltkemeier et al.
shows the highest delay and energy per transitions.
Based on the results shown in [6], we decided to
replicate the current mirror-based circuit presented in
[4] exploiting the 90-nm ST Microelectronics CMOS
technology. For the sake of fair comparison, the output
buffer was designed as suggested in the original paper

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume5, Issue4, April 2016

[4] and the complete LS was simulated in the same

operating conditions as the proposed circuits. The
replicated [4]** shows the lowest delay and quite low
energy per transition. However, it is worth noting that,
in both the original paper [4] and our replication,
layout effects are not taken into account.
Unfortunately, since the output node of the current
mirror floats when the input voltage signal is high, a
detrimental effect on sub-threshold leakage of the
output buffer occurs. This leads to a large static power
dissipation of the complete LS architecture (20.3
nW@ 0.2 V).
The proposed design, benefiting from specific subthreshold leakage-reduction design techniques,
achieves static power as low as 6.4 nW@ 0.2 V, an
energy dissipated per transitions of only 74 fJ for a
0.2-V 1-MHz input pulse, and a delay of 21.8 ns (or
484 FO4). Furthermore, it requires only 36.5 m2 of
silicon area, or 11 times the area of a minimum-sized
standard cell inverter in the chosen technology. Silicon
areas required by [3] are estimated to be 16 and 52
times the respective inverter standard cell. Finally, the
novel LS requires 16% less active area than the
solution proposed in [4].

[4]

[5]

[6]

[7]

IV. CONCLUSION
New low-power LS suitable for robust logic voltage
shifting from near/sub-threshold to above threshold
domain. The proposed circuit exploits proper design
strategies to limit energy and static power
consumption. Thanks to these features, when used for
sub-threshold to above threshold voltage conversion,
the proposed design exhibits the lowest static power
and energy consumption with respect to previously
proposed LSs that use similar design parameters.
Moreover, even though the novel LS is optimized for
low power consumption, it also reaches high-speed
performances and supports a wide voltage conversion
range.

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