Int. J. Electron. Commun.

(AEÜ) 138 (2021) 153857

Contents lists available at ScienceDirect

International Journal of Electronics and Communications

journal homepage: www.elsevier.com/locate/aeue

Regular paper

An efficient high speed and low power voltage-level shifter

Neda Rezaei *, Mitra Mirhassani
Electrical and Computer Engineering Department, University of Windsor, Windsor, ON N9B 3P4, Canada

A R T I C L E I N F O A B S T R A C T

Keywords: This study proposes a novel negative level shifter capable of converting low levels of input voltages to high
Level shifter output voltages while maintaining high speed and low delay and superior static power dissipation. The proposed
Body biasing level shifter is composed of a combination of cross-coupled and current mirror configurations. The minimal
Static power
operating voltage of the proposed level shifter is 400 mV. In addition to the operating range, the power con­
Propagation delay
sumption and delay of the proposed level shifter were designed for low-power applications. Under VDDL=0.4 V,
2010 MSC:
VDDH=1.8 V and fin = 1 MHz condition, the average power, energy/transition and static power were 2.6 μW,
00-01
99-00
26 fJ/Transition, and 70 pW, respectively.

1. Introduction The LS circuits in [11–14] are based on the current-mirror (CM)

In the past few decades, one of the most efficient methods to achieve
a significant reduction in the digital circuits’ power consumption is to
reduce their supply voltage [1,2]. As the complexity of systems on chips
(SoCs) increases, circuits operating in the sub-threshold region have
attracted more attention to be utilized in low-power applications.
However, the main problem is that lowering the power supply decreases
circuit speed [3].
One effective solution to address this problem is to apply multiple
supply voltage (MSV) in order to feed different parts of the system. In
this methodology, higher voltages are employed for the circuits that
require higher speed and the reverse is employed for lower speeds [4].
Therefore, level shifters (LS) that are able to provide wide voltage
conversion ranges to convert the signal between different voltage do­
mains were introduced [4]. The level shifters have been used in voltage
controlled oscillators (VCO) and frequency to voltage rectifiers (FVR)
[5], in comparators in RF power harvesting systems [6], as well as
environmental sensors [7,8], and healthcare devices.
The main challenge associated with MSV is the minimization of delay
and power for level conversion between different voltage levels [9].
Furthermore, the increase in the number of power lines makes this issue
particularly critical [10]. Thus, the design of an LS plays a vital role in
the overall system performance.
Several level shifter structures were recently proposed to enable
voltage conversion from the deep sub-threshold region up to the nomi­
nal supply voltage level [11–14].
configuration; these conventional CM-based lever shifters convert deep
sub-threshold voltages to higher voltage levels. This is done due to the
high drain-to-source voltage of PMOS transistors that facilitates the
construction of a stable current mirror, which presents an effective
on–off current comparison at their output node. However, these struc­
tures face high static current consumption, which results in high standby
power [11–14].
Alternatively, a conventional cross-coupled level shifter (CC LS) is a
differential cascade voltage switch logic (DCVSL) used to raise a low
voltage level. Two factors significantly impact the operating range of CC
LSs: transistors’ threshold voltage and size; however, this operating
range is difficult to extend to the sub-threshold region (concerning the
NMOS threshold voltage). Furthermore, for converting a sub-threshold
voltage, CC-based LSs require an exponential increase in NMOS tran­
sistor size, which is not area efficient[15].
To address these problems, several LS circuits have been reported in
literature [16–18]. The LS proposed in [16] applied the Wilson current
mirror scheme. The main advantage of this circuit is a fast operation;
however, it happens at the expense of large standby power consumption
[17,18]. To lower static power concern, some modified Wilson current
mirror-based LS configurations were recently presented in [17,18].
However, static power consumption remains considerable.
Author [19] proposed a self-controlled current limiter by detecting
output error to reduce power. This achieves relatively robust operation;
however, this design increases power consumption and instantaneous
short-circuit power, mainly at the fast corner and high temperature. The

* Corresponding author.
E-mail address: rezaein@uwindsor.ca (N. Rezaei).

https://doi.org/10.1016/j.aeue.2021.153857
Received 27 April 2021; Accepted 9 June 2021
Available online 18 June 2021
1434-8411/© 2021 Elsevier GmbH. All rights reserved.
N. Rezaei and M. Mirhassani
Fig. 1. Proposed level shifter.
work in [20] removes the input inverter to decrease the falling edge
delay. This design also could cut off the static power; however, it would
be vulnerable to noisy or leaky environments. The falling edge delay is
also reduced in [3] by employing a level-shift capacitor charged to the
voltage difference of VDDH and VDDL.
In this study, we present the design of an ultra-low-voltage energy-
efficient level shifter designed in 180 nm CMOS. The proposed level
shifter includes a combination of a current mirror and cross-coupled-
based level shifters and a current limiter. This proposed circuit ex­
ploits improved static power consumption by utilizing a body biasing for
the required high/low threshold voltage devices.
The rest of this paper is organized as follows. Section 2 describes the
proposed level shifter design. Section 3 presents the results compared
with previously published competitors. Finally, conclusions are given in
Section 4.
2. Proposed Level Shifter Design
Fig. 1 demonstrates the proposed LS structure, which is composed of
an input inverter (Mn4 and Mp6 ), a current mirror (Mp3 and Mp4 ), a cross-
coupled pair (Mp1 and Mp2 ), a diode-connected current limiter (Mn3 ),
and an output inverter (Mn5 and Mp5 ).
The input inverter transistors, Mn4 and Mp6 , provide the differential
low-voltage signals, and the output inverter (Mn5 and Mp5 ) is designed to
assure adequate output driving strength. Moreover, the combination of
the current mirror and cross-coupled configuration creates a cascading
effect, which lowers the drain-source voltage drop across transistors,
and in turn decreases the leakage current.
Fig. 2. Bulk current of Mp5 and Mp6 as VDDL varies between 0.4 and 1 V at different PVT corners.
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AEUE - International Journal of Electronics and Communications 138 (2021) 153857
In the proposed design here, when the signal IN goes from high to
low, the Mn1 is turned off, while the differential signal INL provided by
input inverter turns ON transistor Mn2 . By turning Mn2 ON, the voltage at
node X hovers above zero, which results in Mp5 entering the ON state.
Finally, VDDH voltage level is transferred to the output node. The same
procedure would happen when signal IN goes to high, which results in a
low-output voltage.
In sub-threshold region, an increase in the threshold voltage expo­
nentially decreases the operating current. The low threshold (lV th ) de­
vice improves the circuit performance in sub-threshold region, but it
contributes to the leakage power [21]. Therefore, the lV th devices are
only employed to improve performance.
The key strength of the proposed design is that rather than utilizing
multi-threshold techniques to improve design performance in the sub-
threshold region as same as the works in [18,22,15], the body biasing
technique is employed. The main advantage is that the threshold voltage
could be controlled without using different devices in the design.
In the proposed scheme, all PMOSs’ body terminal, except Mp5 and
Mp6 , are tied to the highest voltage level (VDDH) while all NMOSs’ body
are grounded; however, Mp6 is required to have low-threshold voltage to
enhance the performance in sub-threshold region. On the contrary, the
pull-up Mp5 connects to a high-threshold voltage (hV th ) to reduce
leakage current. In this context, the threshold voltage of Mp5 is risen by
applying an external 1.8 V voltage.
The Mp6 ’s body voltage should be less than the minimum VDDL. This
required body voltage is generated by a voltage divider. The voltage
divider is composed of two diode-connected MOSs, Mn7 and Mn8 , as a
load and an extra NMOS, Mn6 , to break the VDDL down to the lower
voltages. Moreover, the output node, Bn , would supply the Mp6 ’s body
voltage. The main advantage is that the Mp6 ’s body voltage can be
updated with the VDDL changes. Hence, its threshold voltage and the
whole performance of the circuit will be adjusted if VDDL changes. Fig. 2
illustrates the bulk current of Mp5 and Mp6 when VDDL varies between
0.4 and 1V at different PVT corners. As this figure exhibits, the Mp5 bulk
current is saturated to some orders of atto-amp across different corners,
which could be neglected. However, the amount of current the Mp6 ’s
bulk leaks increases to almost 200 pA at fast–fast corner and VDDL of
0.6 V. However, it would exponentially increase to almost 120 nA at
VDDL of 1 V. These results validate that the proposed circuitry could
effectively keep the leakage current low as VDDL is small.
Along with the mentioned proposal, a novel topological strategy is
also employed in this design. The proposed circuit combines the cross-
coupled and current mirror LS structures. Through this combination,
the voltage drop across MOSs which are placed between VDDH and
N. Rezaei and M. Mirhassani AEUE - International Journal of Electronics and Communications 138 (2021) 153857

Table 1 transistor sizes are listed in Table 1.

Transistor sizes.
Transistor W/L(μm) Transistor W/L(μm) 3. Results and Comparison
Mn1 -Mn3 0.45/0.18 Mp1 -Mp3 0.45/0.18
Fig. 3 shows the layout view of the proposed LS, which is imple­
Mn4 0.45/0.18 Mp4 0.85/0.18
mented using the TSMC 180 nm CMOS technology. For this imple­
Mn5 0.45/0.18 Mp5 0.45/0.18
mentation, the bodies of transistors Mp1 -Mp4 placed in a common high
Mn6 -Mn8 0.45/2 Mp6 1/0.18
voltage N-well tied to VDDH whereas Mp5 is placed in a 1.8 V N-well.
Furthermore, transistors Mp6 are reside in a low voltage N-well tied to
Bn . To implement long-length MOSs in the voltage divider configuration,
four 0.5 μm length transistors are also attached in series. In such tech­
nology, the physical design of the proposed level shifter including
voltage divider occupies a silicon area of 99.875 μm2 (11.75 μm ×
8.5 μm).

3.1. Performance Evaluation

The circuit is implemented using 180 nm CMOS technology. Simu­

lations were performed for three process temperature (PT) corners
( − 20 ◦ C, 27 ◦ C and 100 ◦ C), considering an input signal frequency of
1 MHz, with VDDH fixed at 1.8 V. Three important parameters for
proper operation of LSs includes: Propagation delay, power consump­
Fig. 3. Physical design.
tion, and energy per transition, which are discussed in this section.

3.1.1. Propagation-Delay Assessment

Fig. 4. Transient results of the proposed negative level shifter.
ground is decreased. Therefore, the leakage current and in turn the
static-power consumption are lowered. A current limiter, Mn3 , is also
employed to decrease the leakage current furthermore. The optimal
The propagation delay of a logic gate is the difference in time
(calculated at 50% of input–output transition), when output switches,
after application of input.The average delay of fall-time and rise-time is
reported as the propagation delay.
Fig. 4 shows the signal transition of the proposed negative level
shifter circuit, where the circuit can operate under a typical corner and
temperature of 27 ◦ C at 1 MHz.
Fig. 5 shows the delay variation of the proposed LS with VDDL
variations across five corners and three temperature conditions
( − 20 ◦ C, 27 ◦ C and 100 ◦ C). As expected, when VDDL increases, delay
decreases significantly. Furthermore, when temperature raises from
− 20 ◦ C to 100 ◦ C, the delay in the typical corner decreases from 15.5 ns
to 7 ns at VDDL=0.4 V. The obtained delay at 27 ◦ C for typical-typical
corner also falls under 570 ps as VDDL increases from 0.4V to 0.9 V.
The worst delay was 160 ns under slow-fast corner and − 20 ◦ C, whereas
the best delay (350 ps) was happened under fast–fast corner at 100 ◦ C.
3.1.2. Power Consumption Assessment
Fig. 6 exhibits the relationship between the proposed LS’s power

Fig. 5. Delay versus VDDL variations for five corners at temperatures of − 20 ◦ C, 27 ◦ C and 100 ◦ C.

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N. Rezaei and M. Mirhassani
Fig. 6. Static power versus VDDL variations for five corners at temperatures of − 20 ◦ C, 27 ◦ C and 100 ◦ C.
Fig. 7. Histogram of delay and static power consumption of the proposed LS.
Fig. 8. Static power versus temperature.
consumption and VDDL. The results illustrate that the typical static
power at 27 ◦ C evaluated for VDDH = 1.8 V and VDDL between 0.4 to
0.9 V, saturates to Pico-Watt (70 pW for 0.4 V VDDL). Our proposed LS
has also achieved a minimum power of 58 pW when VDDL is 0.9 V under
slow-slow corner and − 20 ◦ C, and exhibits the maximum power of
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AEUE - International Journal of Electronics and Communications 138 (2021) 153857
374 nW when VDDL is .9 V under fast–fast corner and 100 ◦ C.
To investigate the robustness of the proposed level shifter, a 5000-
point Monte Carlo simulation (see Fig. 7) was performed under
typical-typical corner at VDDL=0.4 V.
In case of delay, the highest number of samples were happened at
10ns, which is as expected. With regard to static power, the most number
of samples was also occurred at 75 pW, which is closed to the reported
static power in Section 3.1.2 (70 pW under VDDL=0.4 V and typical
corner at 27 ◦ C).
3.1.3. Thermal Assessment
Fig. 8 shows the static power changes in different corners as tem­
perature varies from − 20 ◦ C to 100 ◦ C. With regard to static power, the
thermal variation of the fast-slow and fast–fast corners are significant
compared with three other corners. The power at fast-slow and fast–fast
corners increases to 7 nW and 9.66 nW respectively. The static power
also increases by 1.4 nW in typical-typical corner. However, the thermal
changes at slow-fast and slow-slow are in order of pico-watt, which are
respectively 743 pW, and 433 pW.
3.2. Comparison
Fig. 9 compares delay, energy per transition and total power of the
proposed LS with the obtained result in [10,14,24]. From the
N. Rezaei and M. Mirhassani AEUE - International Journal of Electronics and Communications 138 (2021) 153857

Fig. 9. Delay–energy-characteristics comparison.

Table 2
Performance summary and comparison with the state of the art.
[3] [25] [14] [10] [19] [23] [23] [23] [23] [24] ThisWork
MCMLS SCMLS DDSLS Cross-Coupled

Year 2017 2017 2017 2017 2018 2021 2021 2021 2021 2021 2021
Technology (nm) 180 180 180 180 180 180 180 180 180 180 180
Results chip sim chip chip chip sim sim sim sim sim sim
min VDDL (V) 330m 360m 80m 200m 250m - - - - 240m 400m
VDDH (V) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8
Operating frequency (Hz) 500 ​ K 1​M 10 ​ K 100 ​ K 140 ​ K 100 ​ M 100 ​ M 100 ​ M 100 ​ M 1​M 1​M
Pavg (μW) - - - - - 4.2 7.2 12.7 8.1 - 2.6
Energy(fJ/Transition) 61.5 4.7 240 173 42.9 77.1 130.9 81.7 38.39 26
Pstatic (W) 330p 200p 150p 55p 1.5n 37.6p 31.5p 37.6p 33.5p 98.3p 70p
Delay (s) 29n 30n 21.4n 31.7n 180n 553.4p 931.7p 575.2p 854.2p 6.43n 10n
Area (μm2 ) 229.5 - 95.6 108.8 - - - - - 99.875

observation, the proposed LS topology in this study has lower propa­
gation delay at VDDL of 0.45 V compared with [10,14,24]. The LS in
[10] also has a delay of 20 ns at 0.4 V which is exactly twice of the re­
ported delay in this study under same condition. This is a major verifi­
cation of the higher speed of our LS.
In terms of energy per transition, our proposed LS could also perform
better than two others at low VDDL. As it is shown, it consume 26 fJ at
VDDL=0.4 V; however, the circuitries proposed in [10,14] needs energy
in order of some hundreds of femto-joule (180 fJ and 200 fJ respec­
tively). Our proposed LS could also perform better than what was
designed in [24] because ours could consume almost 3 times less energy
in average than the LS in [24].
Table 2 compares the proposed circuit with several state-of-the-art
ultra-low-voltage level shifters. To extend our comparison analysis, six
recent proposals designed with the same technology were considered.
Among the level shifters realized in the 180 nm technology, the
SCMLS design proposed in [23] exhibits the lowest static power con­
sumption (31.5 pW) at VDDL=0.4 V. However, this performance is
achieved at the cost of higher Energy than ours (77.1f J/T compared
with 26 fJ/T), which is almost 3 times more than our reported energy.
The MCMLS, DDSLS and cross-coupled designs in [23] also consume
less static power than our proposal; however, all these three models
require more energy/transition than our LS (42.9 fJ, 130.9 fJ, and
81.7 fJ respectively compared with 26 fJ). The same issue is also occurs
for the LS in [10]. It consumes less static power while requires higher
energy ( × 6.65) than the proposed LS in this study.
In terms of propagation delay, the level shifters proposed in [23,24]
exhibits faster operation; however, this achievement is obtained at the
cost of a higher energy and static power respectively than what is
proposed in this paper.
The level shifter proposed in [25] has ≈ 2.85, and 3 times more static
power and delay respectively than our proposed design. However, it
requires 5.5 times less energy per transition.
4. Conclusion
In this paper, a fast and low-power level shifter in 180 nm CMOS
technology has been proposed. The level shifter in this study is
composed of a combination of the cross-coupled and current mirror-
based level shifters. It is also equipped with a current limiter to guar­
antee low-leakages. Moreover, the body biasing technique is employed
to generate multi-threshold devices. The required body biasing voltage
is fed by a voltage divider, which is updated by VDDL. The reported
results confirm that the proposed level shifter is capable of handling low-
voltage input signals into high-voltage output signals (convert a 400 mV
input voltage into a high-voltage output of 1.8 V). The static power and
propagation delay of the proposed LS was 70 pW and 10 ns respectively
under VDDL=0.4 V, VDDH=1.8 V and fin = 1 MHz.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.

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