5386 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO.
6, JUNE 2024
Two-Stage Three-Phase Transformerless Hybrid
Multilevel Inverter for Solar PV Application
Neha Tak , Student Member, IEEE, and Sumit K. Chattopadhyay , Member, IEEE
Abstract—The proposed inverter topology is emerged
from the multiple level-doubling-network (LDN) based
topology for grid-connected solar photovoltaic (PV) sys-
tem, where dc buses of three phases could not be merged
without electrical isolation. Three-phase T-neutral point
clamped (TNPC) is used to merge all the three phases
without transformer. Due to LDN operation, balancing the
capacitors of TNPC (main bridge) is a major challenge. A
dc–dc converter is customized in this work, which is nor-
mally required for two-stage operation of solar PV inverter.
This converter topology reduces the size and losses of filter
inductors due to high-resolution inverter output voltage in
addition to restricting the leakage current well below the rel-
evant standards. To validate the concept, experiments are
carried out using hardware prototype and those matched
well with simulation result.
Index Terms—Asymmetric multilevel converter topology,
capacitor balancing, coupled inductor, leakage current,
level doubling network (LDN), photovoltaic (PV), space vec-
tor modulation, T-neutral point clamped (TNPC).
I. INTRODUCTION
RID-CONNECTED photovoltaic (PV) inverters have
G been developed and commercialized over the past few
years. Inverter topologies are currently being researched to
improve power quality, reliability, and efficiency while reducing
the number of components [1] to make cost-effective inverter
solution [2]. Due to insulation limit of PV module, solar PV array
voltage must be restricted to 600 to 900 V, which means current
has to be very high for multimegawatt converters. Chopping this
current at high frequency causes high switching losses mainly in
two-level and three-level inverters. Tradeoff between switching
losses and power quality of a two-level inverter [3] makes it
less desirable option for utility-scale PV applications. To meet
the high power handling requirement of large PV systems,
multilevel converters are being considered as a viable solution.
One of the most widely used transformer-free topologies in
solar PV systems is the neutral-point-clamped converter [4]. A
neutral point controller is described in [5], which is expected
to minimize the fluctuation of the neutral potential. Instead of
Manuscript received 3 February 2023; revised 15 April 2023 and 16
June 2023; accepted 5 July 2023. Date of publication 8 August 2023;
date of current version 19 January 2024. (Corresponding author: Neha
Tak.)
The authors are with the Department of Energy Science and Engi-
neering, Indian Institute of Technology Delhi, New Delhi 110016, India
(e-mail: neha.tak@ces.iitd.ac.in; sumit@dese.iitd.ac.in).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2023.3299027.
Digital Object Identifier 10.1109/TIE.2023.3299027
0278-0046 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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using clamping diodes, active switches are used in the active
neutral-point-clamped (ANPC) [6] topology. To prevent switch
overvoltage, Zhuang et al. [7] proposed an ANPC zero-crossing
switching method.
A nonisolated converter is used along with single-phase full-
bridge inverter in [8] to effectively eliminate the leakage current
[9]. However, this is achieved at the cost of one diode and two
additional switches. This configuration is applicable for single
phase and may not be cost-effective solution for three-phase
system. Moreover, a greater number of switches are coming
in the conduction path as compared to similar transformerless
topologies for PV application. Control of two-stage inverter
is presented in [10] and mainly addresses low-voltage ride-
through (LVRT) condition. LVRT in grid-connected PV inverter
is achieved in most of the cases by deviating the PV array voltage
toward the open-circuit voltage during fault condition.
A transformerless converter is developed in [11]. This con-
figuration provides low-cost converter with better efficiency. A
switched capacitor multilevel inverter is proposed in the litera-
ture, which improves power quality and reduces leakage current
[12], [13]. In order to eliminate leakage current in five-level
cascaded H-bridge (CHB) multilevel inverter (MLI), a novel
PSPWM modulation technique is proposed in [14]. A two-stage
transformerless T-neutral-point-clamped (TNPC) MLI, which
consist of a three-level boost converter, is propsed to enhance
the efficiency and reduce the cost of inductor [15]. Neutral point
converter is presented with some mechanism to limit leakage
current, common-mode voltage and to compensate neutral point
[16].
Power frequency transformers are unavoidable in the topology
present in [17]. Voltage stress in all the switches will be equal
to main dc-link voltage. In order to develop five levels in output
voltage, 12 switches are used in [18]. Tradeoff is done between
capacitor size and switching frequency in this work. A similar
topology is presented in the literature to generate 13 levels
in line-to-line voltage [19]. In this work, six-phase machine
is utilized to instantaneously remove the neutral-point voltage
fluctuations.
Multilevel inverters, such as CHB and modular multilevel
converters, provide high power quality and efficiency [20],
[21]. However, higher number of PV arrays are required to fed
multiple H-bridges in CHBMLI [22]. When three phases are
fed by different PV array, it results in an unbalanced current
injection or power imbalance among the phases due to partial
shading. Various methods for resolving these issues are proposed
in [23]. Asymmetrical multilevel inverter [24] gives higher
TAK AND CHATTOPADHYAY: THREE-PHASE TRANSFORMERLESS HYBRID MULTILEVEL INVERTER FOR SOLAR PV APPLICATION
power quality with same number of bridges as compared to
symmetrical CHBMLI. However, asymmetrical MLI bridges
[25] are fed by different PV array, which causes uneven power
distribution and interarray leakage current. More isolated dc
sources with different power ratings are needed for asymmetrical
multilevel inverter topologies and, moreover, these isolated dc
sources consume power in very different range, which causes
high cost of implementation. Maintaining power quality in input
side becomes difficult as power consumption is very different
in different bridges. Consequently, the voltage rating of the low
voltage cells and the need for bidirectional power sources are
some concerns.
Level doubling network (LDN) is proposed to reduce the
power rating of isolated auxiliary sources. In H-bridge, if half-
bridge is get added, then it helps to get double the number of out-
put voltage levels. Half-bridges are fed by capacitors and known
as LDN, and full-bridges are fed by dc sources. Capacitors are
self-balanced, and its voltage will be maintained at half of its
corresponding bridge voltage. This topology does not require
any closed-loop control to balance capacitor voltage. In the liter-
ature, it is found that 1:7 is the optimal ratio of asymmetry to get
higher number of output voltage levels using concept of double
LDN. In this work, auxiliary bridges are fed by bidirectional
isolated sources. Though power requirement by these sources
are just 7% of total rated power, however, it will contribute
substantial cost to the converter. In this double LDN-based
topology [26], dc buses of main bridges are merged with the help
of three isolation transformers to reduce capacitor requirement
and to prevent current imbalance in phases. However, the use
of power transformers reduces system efficiency and increases
the cost, weight, and volume of the system. In [26], isolated
auxiliary sources are used, though the power requirement by
these isolated sources is very less but it get reflected in total
system cost. These isolated sources have been removed in [27]
with the help of low-gain PI controller. In this converter, only
main bridge is fed by dc source. As observed in aforementioned
literatures, in order to develop a practical inverter solution, main
focus is given to remove transformer, mitigate leakage current,
reduce part count, and semiconductor losses. The work reported
in this article addresses all the aforementioned aspects along
with high power quality, reliability, and efficiency. The following
contributions are made in order to achieve the aforementioned
attributes in a single PV inverter.
1) Double LDN-based high-resolution multilevel inverter
is modified in this work for two-stage grid-connected
solar PV application. This architecture doubles the power
handling capability of the inverter by incorporating a
dc–dc converter.
2) For central inverter applications, the dc-buses of three
phases are merged without using isolation transformer to
decrease capacitor ripple and to reduce the probability
of interarray leakage current. As three-isolation power
frequency transformers of the full-scale converter rating
are removed in this work, it is expected to reduce the
implementation cost by 35%–50%.
3) In this work, in order to remove transformers of full con-
verter rating, main H-bridges are replaced by three-phase
TNPC.
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5387
Fig. 1. Circuit diagram of the prior art converter topology.
4) A coupled inductor-based buck–boost converter is used as
first stage of the two-stage PV inverter topology in order
to achieve NPC capacitor balancing without closed-loop
control.
5) In the proposed topology, the path of common mode
current (reduced using a common mode choke) is dif-
ferent from the PV array leakage current. Moreover,
both currents are maintained within standard safety
limits.
This article consists of six sections. Section I depicts motiva-
tion and challenges to use multilevel inverter in grid-connected
PV systems. Section II gives brief idea of double LDN-based
topology with transformer. Section III explains different con-
verter configuration for hybrid multilevel inverter topology to
develop efficient, cost-effective, and high-performance inverters
that meet PV system requirements. Capacitor balancing method
for TNPC is also explained in detail in this section. Section IV
discusses the simulation results. Section V validates the con-
cept through hardware results. Section VI presents an in-depth
analysis on performance of the converter based on analysis, sim-
ulation, and experimental results. Finally, Section VII concludes
this article.
II. TOPOLOGY TO REMOVE TRANSFORMER AND ITS
BACKGROUND
LDN-based topologies are useful to achieve high resolution
in output voltage with limited switches. In prior art [26], main
bridge dc buses of three phases are merged in order to reduce
capacitor requirement and to prevent unbalance current injection
due to partial shading. To merge three phases, three isolation
transformers are required, as shown in Fig. 1, which makes
system bulky as well as expensive. Isolation transformers are
replaced in the presented work by using three-phase TNPC
topology along with a customized dc–dc converter for two-stage
PV application. This topology is not only useful to merge the
three PV arrays without isolation transformer, but also helpful to
limit the leakage current. Complete circuit diagram of the hybrid
converter topology is illustrated in Fig. 2.
This hybrid power converter needs 12 switches per phase
and only one dc source in complete converter topology to
reach optimal voltage resolution. The inverter section of the
5388
Fig. 2. Proposed two-stage grid-connected PV inverter topology.
presented topology can generate high-resolution output voltage,
as discussed in [27]. The aim of this work is to merge dc buses
of three phases of main bridges without isolation transformer.
This converter is developed by hybridizing TNPC topology and
LDN modules. It is relevant to note that TNPC topology is more
suitable for PV application (due to limited PV array voltage)
compared to any other neutral-point-clamped topologies.
In proposed topology, TNPC and main LDN are of value 20
and 5 V, respectively, and its combination is known as high-
voltage module. Low-voltage module that is auxiliary bridge
and auxiliary LDN is of value 2 and 1 V, respectively. Auxiliary
bridge needs closed-loop control to balance the capacitor volt-
age, whereas LDNs are self-balanced, and they do not require
any closed-loop control. LDN voltage converges to half of
its corresponding bridge voltage through self-balancing with-
out closed-loop control. Main module work on fundamental
switching frequency and auxiliary module operates at relatively
higher switching frequency. Main bridge and auxiliary bridge
maintain 1:5 ratio of asymmetry to remove auxiliary voltage
sources. To remove auxiliary sources, it is necessary to ensure
that fundamental component of input reference voltage should
match with fundamental component of output of main module
in the steady state. Hence, input of auxiliary module will not
have any fundamental component.
TNPC is preferred over NPC as in curent path, the number of
semiconductor devices are lower in three-level TNPC as com-
pared to three-level NPC to achieve positive and negative volatge
levels. However, the voltage stress across TNPC switches is
double as compared to NPC. Though conduction loss can be
reduced by selecting appropriate switches. TNPC is fed by two
floating capacitors connected to neutral point of the converter.
Voltage across these two floating capacitors, i.e., C1 and C2 ,
should be maintained at half of the main dc-bus voltage.
Proposed hybrid topology brings the challenge of capacitor
balancing due to LDN operation. In the literature to balance
the upper and lower capacitors of NPC-based topologies, space
vector redundancies are selected in such a way that charging
and discharging will take place from both the capacitors to
maintain equal voltage across capacitors. However, in order to
satisfy LDN principle, it is not possible to form space vector
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 6, JUNE 2024
using multiple redundancies. Hence, only one set of space vector
combination is used to balance the LDN capacitors. Moreover, it
brings the challenge to equalize the charging and discharging of
upper and lower capacitors “C1 ” and “C2 ,” respectively. Either
upper capacitor will supply power to LDN or lower capacitor will
supply power depending on the topological configuration. As
presented in [26], lower capacitor of TNPC will always supply
power to the LDN. Hence, it brings a limitation due to different
rate of discharging in both the capacitors. In absence of some
additional balancing circuit between C1 and C2 , the upper and
lower capacitors will substantially diverge. Unequal distribution
of voltage at upper and lower dc bus will not be able to maintain
the desired voltage across main and auxiliary LDN, which will
distort the output line-to-line voltage to an unacceptable level.
Hence, it is required to have some additional circuit with proper
controller to equalize the charging and discharging of upper
and lower capacitors. For two-stage grid-connected PV system,
dc–dc converter is modified and customized in such a way that
no extra controller and converter will be needed to balance
the capacitor voltages, as shown in Fig. 2. Operation of the
customized dc–dc converter is presented in the next section.
III. GRID-CONNECTED TWO-STAGE OPERATION OF THE
PROPOSED HYBRID TOPOLOGY
Proposed work is specifically for two-stage grid-connected
PV system where dc–dc converter is important part of complete
system, and it cannot be avoided in order to operate inverter
around unity modulation index and to have decoupled control
of maximum power point tracking (MPPT) and grid current.
This dc–dc converter helps to double the inverter power handling
capacity for grid-connected solar PV application compared to a
single-stage PV inverter.
In presented work, the coupled inductor-based buck–boost
converter itself is used to equalize the voltages of the upper
and lower capacitors. Relation between voltage and flux and
inductance of a single inductor coil is given in (1) and (2).
Hence, the voltage across single inductor coil can be calculated
using (3). However, for coupled inductor, flux (Ф22 ) generated
by secondary current (i2 ) known as mutual flux (Ф12 = Ф21 ) in
the secondary winding is also linked to the first winding. The
rate of change of current in both primary and secondary windings
will give voltage across primary (VL1 ) and secondary windings
(VL2 ), as given in (4) and (5)
dΦ
V =N (1)
dt
NΦ
L= (2)
i
di
V =L (3)
dt
di1 di2
VL1 = L11 + L12 (4)
dt dt
N1 Φ11 N1 Φ12
where L11 = i1 and L12 = i2
di1 di2
VL2 = L21 + L22 . (5)
dt dt
TAK AND CHATTOPADHYAY: THREE-PHASE TRANSFORMERLESS HYBRID MULTILEVEL INVERTER FOR SOLAR PV APPLICATION 5389

Fig. 3. Circuit diagram of customized dc–dc converter with single-

phase TNPC and LDN.
Fig. 5. LDN operation. (a) LDN (half-bridge) charging through lower
capacitor of TNPC. (b) LDN discharging through upper capacitor of
TNPC.

Lb2 will be as high as Vpv or Vdc (neglecting loss due to leakage

and stray parameters). Turns ratio of coupled inductor also help
to determine the blocking voltage of diode Db1 and Db2 . Like
a buck–boost converter, the inductor currents ILb1 and ILb2 of
coupled inductor will vary with load
diLb1
VLb1 |Sb =1 = Vin = Lb1 (6)
dt
 
diLb1  ΔiLb1 ΔiLb1 ΔiLb1  Vin
= = or =
Fig. 4. Working of customized buck–boost converter circuit to equalize dt Sb =1 Δt DT DT Sb =1 Lb1
the voltage across upper and lower capacitors. (a) Schematic diagram.
(b) Charging of lower capacitor C2 when (Vc2 <Vc1 ) and charging of DT Vin
(ΔiLb1 )|Sb =1 = (7)
upper capacitor C1 when (Vc2 >Vc1 ). Lb1
VDb1 |Sb =1 = VLb2 + VC1 (8)
Customized dc–dc converter consists of one switch “Sb ,”
coupled inductors “Lb1 ” and “Lb2 ,” and diodes “Db1 ” and “Db2 ,” VDb2 |Sb =1 = VLb1 + VC2 (9)
which will help to boost the PV voltage in present case as well NS NS
as to balance the capacitor voltages. No additional capacitors VLb2 |Sb =0 = VLb1 = Vin . (10)
NP NP
are needed for this dc–dc converter because the capacitors used
in the main converter will be used in this dc–dc converter. When switch “Sb ” is ON, the inductor current will flow on
Circuit diagram of a customized coupled inductor-based dc–dc one side, and capacitors on the other side will be discharged
converter with single-phase TNPC and LDN is shown in Fig. 3. in response to the load. Lower capacitor C2 is having higher
Working of capacitor voltage balancing is explained through discharge rate owing to LDN operation as per the polarity of
Fig. 4. For capacitor voltage balancing, two cases are considered, LDN, as depicted in Fig. 5(a) and (b). In the present topo-
i.e., ideal and nonideal situations. For initial investigation, it logical configuration, LDN charges in the negative half cycle
is assumed that there is no parametric difference in terms of and discharges in a positive half cycle, as shown in Fig. 5(a)
stray resistance and inductance and only ideal components are and (b), which means in the negative half cycle, power goes
considered. from the lower capacitor of TNPC to charge LDN capacitor.
Current will flow through inductor Lb1 when switch “Sb ” is For this configuration, lower dc-bus capacitor will discharge
closed, as shown in Fig. 4(a). The polarity of “Lb1 ” will be more than the upper dc-bus capacitor. However, if LDN has
determined by the coupled inductor. When Sb is turned ON, given negative voltage with respect to the ground, this situation
current will flow through Lb1 irrespective of the three voltages, could have been reversed. Hence, any configuration can be
namely Vdc , VC1 , and VC2 , as given in (6) and (7). Furthermore, taken for this converter topology, and accordingly charging and
regardless of the voltage on the upper capacitor “C1 ,” the diode discharging rates of capacitors will be decided. In present work,
“Db1 ” will be reverse biased by the reflected voltage polarity on lower capacitor C2 is having higher discharge rate. The moment
Lb2 . The blocking voltage of diode Db1 will be equal to voltage switch Sb will be turned OFF and current will be developed in
appearing at Lb2 and the voltage of upper capacitor C1 , as given inductor as per polarity. In this situation, inductor voltage will be
in (8). Similarly, blocking voltage of Db2 will be decided on the clamped to the lower capacitor voltage, as depicted in Fig. 4(b).
basis of voltage across Lb1 and C2 , as given in (9). Voltage across For example, when VC2 is less than VC1 , then current will be
Lb2 will be decided based on turns ratio of coupled inductor, as able to flow in loop 2, i.e., through Lb1 , Db2 , and C2 . Relation
given in (10). When 1:1 ratio is considered, the voltage across between capacitor voltage VC2 and input voltage (Vin = Vdc )

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5390 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 6, JUNE 2024

is given in (11)–(14). Current can flow in a particular loop only TABLE I

SIMULATION PARAMETERS
when inductor voltage is clamped to capacitor voltage, as shown
in Fig. 4(b). Since Lb1 and Lb2 are mutually coupled, rate of
change of flux will be common for them (neglecting the effect
of stray resistance and leakage inductance). There can be other
situation when VC1 is less than VC2 , then current will be able
to flow in loop 1, i.e., through Lb2 , Db1 , and C1 , then change
in inductor current and VC2 can be calculated using (15)–(17).
However, this situation will not occur as LDN is charging from
lower capacitor C2 (resulting into higher discharge rate of C2 ).
At steady state, both the capacitor voltages will be equal and
accordingly number of turns will be decided, as given in (18)
and (19)
VLb1 |Sb =0 = Vc2 (11)

diLb1 
Lb1 = Vc2 (12)
dt Sb =0
Vc2
(ΔiLb1 )|Sb =0 = (1−D)T
Lb1 (13)
(ΔiLb1 )|Sb =1 + (ΔiLb1 )|Sb =0 = 0
D Fig. 6. Voltage waveforms without balancing circuit. (a) Upper and
Vc2 = −Vin (14) lower capacitors. (b) Main LDN and auxiliary LDN capacitors.
(1 − D)
VLb2 |Sb =0 = Vc1 (15)
 will be equalized. The moment voltage across both capacitors
diLb1 NS 
Lb1 = Vc1 (16) will equalize, the inductor current will be distributed equally
dt NP Sb =0 across both the capacitors. Then, the voltage in both capacitors
(1 − D) T Vc1 NP will begin to rise uniformly. At steady state, both the capacitor
(ΔiLb1 )|Sb =0 = (17) voltages given in (21) and (22) will get equalized, then it will
Lb1 NS
help to calculate the number of turns in primary as well as in
NS
Vc1 − Vc2 = VLb1 − VLb1 (18) secondary
NP
∫0DTs (Vin − r1 iLb1 (t))
NP = NS . (19) (ΔiLb1 )|Sb =1 = (20)
(Lb1 + Lleak1 )
Current distribution in both the capacitors will get affected by  2
diLb2 NS diLb2
nonidealities, such as stray resistance and leakage inductance. VC1 = Lb2 + Lleak2
In proposed circuit configuration, current in leakage inductance dt NP dt
will have path to flow through diodes Db1 and Db2 , as shown − r2 iLb2  (21)
in Fig. 4. Hence, snubber circuit is not required to handle the
leakage current in the proposed converter topology. The total diLb1 diLb1
VC2 = Lb1 + Lleak1 − r1 iLb1  . (22)
stray resistance (diode and inductor) and leakage inductance dt dt
in loops 1 and 2 is r1 and r2 , Lleak1 and Lleak2 , respectively.
However, for nonideal condition, when stray parameters and IV. SIMULATION RESULTS
leakage are considered, inductor voltage and voltage across The analysis of proposed transformerless hybrid asymmetri-
capacitor C2 will slightly differ in compared to ideal situation, cal multilevel inverter is done using MATLAB/Simulink. The
as given in (20)–(22). So, when VC1 > VLb1 , it will not allow main purpose of this simulation is to test a double LDN-based
current to flow in that particular loop. In this situation, lower inverter for two-stage grid-connected solar PV applications to
capacitor C2 will carry current through inductor Lb1 . However, merge three phases without an isolation transformer. The simu-
its coupled version is unable to supply any current, despite the lation parameters are presented in Table I.
voltage being impressed. This process will keep on going as In absence of some balancing mechanism to have a local
long as these two capacitor voltages are not getting equalized. power flow between C1 and C2 , the upper capacitor C1 and
While discharging takes place continuously in C2 due to LDN lower capacitor C2 will not be able to maintain its voltage and
operation, this capacitor will share majority of charging cur- voltage of both the capacitors will be diverge from its desired
rent from the inductor during the switch Sb is OFF. However, voltage, as shown in Fig. 6(a). Due to voltage imbalance in main
discharging can be through both the capacitors, and it varies dc-link capacitors, the main LDN and auxiliary LDN capacitors
at different instances. The lower capacitor will charge through will continue to discharge until they reach zero at steady state,
inductor Lb1 , and at some point, the voltages of both capacitors as shown in Fig. 6(b). Due to divergence of capacitor voltages

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TAK AND CHATTOPADHYAY: THREE-PHASE TRANSFORMERLESS HYBRID MULTILEVEL INVERTER FOR SOLAR PV APPLICATION
Fig. 7. Voltage across upper and lower capacitors for grid-connected
system with customized coupled inductor-based dc–dc converter for
MPPT tracking.
Fig. 8. Voltage across main LDN, main bridge, and auxiliary LDN
capacitors for the grid-connected system.
Fig. 9. Inverter output line-to-line voltage.
from their required value in inverter, output ac voltage and
subsequently grid current will be distorted far beyond the accept-
able limit. With customized coupled inductor-based converter
for MPPT tracking, voltage across upper and lower capacitors
will also be equalized and maintained at desired voltage for
grid-connected system, as shown in Fig. 7. Due to equal voltage
at upper and lower capacitors, LDN capacitor voltage will be
maintained at half of the corresponding bridge voltage. Fig. 8
depicts the balanced capacitor voltage across the main LDN,
the auxiliary bridge, and the auxiliary LDN for a PV-fed grid-
connected system without any addidtional balancing circuit.
High-resolution inverter ouput voltage is shown in Fig. 9.
Line voltage and corresponding phase voltage at a given grid
voltage (+), i.e., at 0.85 modulation index, are shown in Fig. 10.
Line voltage waveform is near to sinusoidal, and phase voltage
contains triplen harmonics, which is getting cancelled out in
line voltage. Grid voltage and current waveform for a given
modulation index at unity power factor operation are shown in
Fig. 11.
Fig. 12 depicts the impact of varying loads on capacitor
balancing. It can be observed from Fig. 12 that after 3 s, solar
insolation is reduced to half, which finally reduces the output
power and grid current correspondingly. A PI controller is used
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5391
Fig. 10. Line voltage and corresponding phase voltage @ grid voltage
of 840 V.
Fig. 11. Grid voltage and current at unity power factor.
Fig. 12. Impact of insolation on capacitor balancing, power, and grid
current.
to adjust direct component of grid current to stabilize the main
dc-link voltage. Fig. 12 represents the inverter operation with
pure active power injection into the grid.
Fig. 13 indicates the impact of load-side current and TNPC
switching on the capacitor balancing. C1 and C2 are having
different currents, i.e., IC1 and IC2 , and current difference will
be determined by the switching combinations of three phases
together. Impact of TNPC output voltage and load current on
IC1 , IC2 , VC1 , and VC2 for one cycle is shown in Fig. 13(a). Its
expanded view is illustrated in Fig. 13(b) to analyze the capacitor
voltage balancing. A particular instance is considered to analyze
different states. Combination of different phase output voltages
can be categorized, as shown in Fig. 13(b), and its detailed study
is given in case 1 to case 4, which are as follows.
Case 1: During T0 <T<T1 , R and B phases clamped to negative
dc bus and Y phase to positive dc bus. IC1 will be equal to IC2
at such condition as a result, VC1 and VC2 will converge to
Vdc /2. Same situation can be observed during T2 <T<T3 .
5392
Fig. 13. Impact of TNPC voltage and load current on voltage and
current of upper and lower capacitors. (a) Overall view for one cycle.
(b) Expanded view.
Case 2: During T1 <T<T2 , Y phase will be clamped to neutral,
and R and B phases to negative dc bus. At this instance, C1
will not be connected to load, whereas C2 will observe the
load impedance.
Total current will flow through C2 , and capacitor voltage will
diverge till next switching, and this is the worst case. Diver-
gence of VC1 and VC2 is restricted by natural adjustment in
current magnitude of IC1 and IC2 , respectively.
Case 3: During T3 <T<T4 , Y phase clamped to positive dc bus,
B phase to neutral, and R phase to negative dc bus. C1 and
C2 will observe unequal loading and consequently discharge
rates of C1 and C2 are different. Charging current from the
dc–dc converter IC1 and IC2 is naturally adjusted to limit the
divergence of voltage at this stage.
The aforementioned analysis gives an idea about the effect
of different output voltage vectors on capacitor balancing and
indicates that the capacitor voltages will remain balanced at all
operating conditions. In dc–dc converter circuit, current ILb1
and ILb2 will be different in both the inductors as per switching
action of Sb , as shown in Fig. 14. Inductor Lb1 is expected to
have a higher average current because it is always conducting,
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Fig. 14. Impact of nonidealities on coupled inductor currents Lb1 and
Lb2 , capacitor currents Ic1 and Ic2 , and voltage across capacitors Vc1
and Vc2 (a) with stray resistance and (b) with leakage inductance.
regardless of whether the switch is turned ON or OFF. While in
Lb2 , the current continues to flow when the switch is turned OFF.
This statement is true regardless of the kind of discharge in the
upper and lower capacitors. Fig. 14 depicts the impact of stray
parameters on current distribution in coupled inductor and both
the capacitors.
Capacitor with higher voltage will have smaller charging
current and vice versa. Ideally, no charging current from dc–dc
converter should flow into C1 , as voltage across C1 is greater than
C2 . However, both capacitors will carry charging current when
switch Sb is turned OFF. Distribution of charging current between
C1 and C2 depends on difference of those capacitor voltages,
respectively. The cause of voltage deviation, as explained in
Fig. 13, is time varying. So, entire window is difficult to illustrate
prominently. Hence, an arbitrary instance has been taken in
Fig. 14. In Fig. 14(a), it is clearly shown that at the instance
between T1 and T2 , C1 and C2 are having negative value of
current. Say, at T2 instance, IC1 is zero and IC2 has some
value (IC2 is following load-side current). Since IC1 is zero and
IC2 has some value that means C2 is discharging more. Here,
TAK AND CHATTOPADHYAY: THREE-PHASE TRANSFORMERLESS HYBRID MULTILEVEL INVERTER FOR SOLAR PV APPLICATION 5393

Fig. 15. Leakage current at full load in the solar PV array.

initially capacitor C2 is discharged higher so entire charging

current entered into capacitor C2 and then as time lapses, voltage
Fig. 16. Pictorial view of hardware setup for grid-connected system.
across C2 increases and both VC1 and VC2 increase. However, (a) Control desk. (b) Oscilloscope. (c) Additional buck–boost converter.
VC2 is increasing at higher rate. After certain instance at T3 , (d) Main module. (e) Auxiliary module. (f) NPC formed with discrete com-
they get equalized and then current IC2 is falling and IC1 is ponents. (g) Main LDN. (h) Synchronization switch. (i) Line inductors.
(j) Grid.
rising. When the difference between VC1 and VC2 , i.e., ΔV,
is larger, then it will affect the current distribution in IC1 and
IC2 at charging end, as shown in Fig. 14(a). Discharging is TABLE II
determined by the load. It can be observed that the current is EXPERIMENTAL SETUP PARAMETERS
not proportionally increasing in every cycle, as it depends upon
percentage of voltage difference in total capacitor voltage. At the
same time, leakage and other nonidealities are also constraints
for balancing the system. Appropriate balancing can be achieved
by adding few compensations turns in Lb1 winding. Capacitor
voltage balancing, inductor, and capacitor currents after con-
sidering leakage inductance case are shown in Fig. 14(b). In
proposed converter topology, leakage current is negligible since
the leakage capacitance (CL ) comes in parallel to the dc-link
capacitance (which is several hundred times bigger than the
leakage capacitance). Hence, no additional circuit is added to
restrict the leakage current, as shown in Fig. 2. Leakage current
in steady state is illustrated in Fig. 15. Peak magnitude of leakage
current is restricted to 0.15 A against rated ac-side peak current
of 85 A, i.e., leakage current is less than 0.2%.
The proposed topology can be directly connected to the dis-
tribution transformer, i.e., usually star grounded at low-voltage
side, which will cause common-mode current in three phases.
However, it may be found from Fig. 2 that path of common-
mode current will be different from the PV array leakage
current. Common-mode current can be effectively suppressed
Fig. 17. Voltage waveforms. (a) Inverter three-phase line-to-line volt-
within limit by common-mode choke or grid formed by delta- age. (b) Synchronization with polluted grid channel 1: Inverter voltage;
connected transformer. In the proposed topology, the magnitude channel 2: Grid voltage; math function: Difference between inverter
of common-mode current is less than 1% of the line current. voltage and grid voltage.
Hence, the effect of this common-mode current on output current
THD is negligible.
neutral-point-clamped configuration instead of TNPC, as shown
in Fig. 16. Parameters used in hardware are shown in Table II.
V. EXPERIMENTAL RESULTS
Fig. 17(a) illustrates balanced inverter output line-to-line volt-
Prototype of this inverter topology is developed in laboratory age at around 0.85 modulation index. The converter is designed
to verify the concept presented in earlier sections. dSPACE such that it will synchronize with the grid at its nominal voltage at
MicroLabBox is used for modulation and control of this inverter this modulation index. This is done to keep sufficient headroom
prototype. A three-phase NPC inverter is fed by a common dc for reactive power injection and to take care of the nonidealities.
source of 320 V and both the capacitors of NPC are maintained This hybrid converter is connected to the grid and its perfor-
at half of dc-link voltage, i.e., 160 V each. A pictorial view mance is verified with polluted grid, as shown in Fig. 17(b).
of the hardware setup for the grid-connected system and key Inverter line-to-line voltage and grid voltage are shown in
components of the hardware prototype is given in Fig. 16. In channels 1 and 2, respectively. It is important to note that even if
addition to this, six-pulse rectifier is used to supply the input the grid voltage is distorted, difference between inverter voltage
of the dc–dc converter. Experiments are conducted using a and grid voltage is not showing substantial distortion, as shown

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5394
Fig. 18. Inverter line voltage and corresponding phase voltages @ grid
voltage of 200 V for (a) three cycles. (b) Zoomed view.
Fig. 19. Inverter output performance channel 1: Line voltage; channel
2: Load-side phase voltage; channel 4: Line current at modulation index.
(a) Unity. (b) 0.5.
Fig. 20. Capacitor balancing channel 1: TNPC dc bus to neutral-point
voltage; channel 2: Main LDN voltage; channel 3: Auxiliary bridge volt-
age; channel 4: Auxiliary LDN voltage. (a) Cold start. (b) At steady-state
variation from unity to 0.9 modulation index.
in the math menu of Fig. 17(b). Inverter voltage is developed in
such a way that the effect of grid harmonics on output current is
nullified.
Inverter line voltage and its corresponding phase voltages are
shown in Fig. 18. It can be observed that the phase voltage
consists of triplen harmonics (generated by space vector modula-
tion) to satisfy floating capacitor balancing operation, which gets
cancelled out in line-to-line voltage. Fig. 18(a) and (b) depicts
inverter line and phase voltage for three cycles and its zoomed
view, respectively. Inverter output voltage and current for two
different modulation index are shown in Fig. 19. Fig. 19(a)
represents inverter output voltage at unity modulation index.
Channel 1 represents 43 levels in output line-to-line voltage,
channel 2 represents load-side phase voltage, and channel 4
represents the line current. Capacitor balancing and voltage
across all the floating capacitors are shown in Fig. 20. Start-up
transients for all floating capacitors are depicted in Fig. 20(a).
All floating capacitors converge toward their desired values. At
instant T1 , dc-bus is charged and at instant T2 , inverter operation
is started in Fig. 20(a). No closed-loop control is used to balance
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Fig. 21. Capacitor voltage variation under influence of load change
channel 1: Main LDN voltage; channel 2: Auxiliary bridge voltage; chan-
nel 3: Auxiliary LDN voltage; and channel 4: Load current.
Fig. 22. TNPC output voltage channel 1: R phase voltage; channel
2: Y phase voltage; channel 3: B phase voltage. (a) Complete cycle.
(b) Possible voltage combination of three phases.
the capacitor voltages of LDN. However, due to limited number
of channels in oscilloscope, it is not possible to illustrate voltage
across both the capacitors. Similarly, auxiliary bridge voltage
(32 V) will be maintained as per 1:5 ratio of asymmetry w.r.t.
voltage across TNPC capacitor (160 V), as shown in Fig. 20(a).
Capacitor balancing due to variation in modulation index, i.e.,
from unity to 0.9 modulation, is shown in Fig. 20(b). It is evi-
dent from Fig. 20(b) that voltage across capacitors is stabilized
without any significant deviation.
Impact of load variation on capacitor balancing is shown
in Fig. 21 to demonstrate the performance of inverter during
dynamic operation. Load is changed from 200 to 600 W at time
instance T1 and 600 to 1000 W at time instance T2 . This may be
observed that there is variation in capacitor voltage ripple w.r.t.
load variation. However, average values of capacitor voltage
remain unchanged.
In proposed converter topology, capacitors do not require
any precharging circuit as all the floating capacitors are getting
balanced through the load. However, it is important to note
that LDNs are self-balanced in open loop and auxiliary bridges
require closed-loop control to reach desired capacitor voltage
after cold start.
Voltage across individual phases of TNPC is shown in Fig. 22.
An overall view of three TNPC phase voltages is illustrated in
Fig. 22(a), whereas Fig. 22(b) displays possible TNPC output
voltage combinations in an expanded view. This matches well
with the results shown in simulation.
Impact of load-side current and switching of main bridge
on the balancing of capacitor is shown in Fig. 23. Voltage
across upper and lower capacitors is shown in channels 1 and 2,
respectively. Both the capacitor voltages are equalized, and their
TAK AND CHATTOPADHYAY: THREE-PHASE TRANSFORMERLESS HYBRID MULTILEVEL INVERTER FOR SOLAR PV APPLICATION
Fig. 23. Channel 1: Upper capacitor voltages; channel 2: Lower ca-
pacitor voltage; channel 3: ILb1 current; channel 4: ILb2 current; math
function: Sum of ILb1 and ILb2.
respective voltage is maintained at 160 V. Resultant inductor
current (sum of current flowing in both the inductor windings)
is shown in red color at a given instance and it is in continuous
conduction mode. It is found by summing up the two winding
currents of the coupled inductor.
Inductor winding currents ILb1 and ILb2 are shown in channel
3 and channel 4, respectively. When switch “Sb ” of Fig. 2 is “ON,”
then the diode corresponding to upper capacitor (C1 ) comes in
reverse bias and ILb2 current immediately falls to zero. At the
same time, inductor current will be transferred from ILb2 to ILb1 .
So, there is a step rise in the inductor current in Lb1 winding and
this winding is going to observe the PV array voltage. As long as
switch is ON, ILB1 will keep on increasing and ILB2 will remain
zero. The moment switch is turned OFF, slope of rise and fall of
ILb1 and ILb2 will be determined by capacitor voltages, leakage
inductance, and stray resistances. Due to leakage inductance of
the respective windings, current will not change immediately.
It can be concluded that Lb2 on average is going to carry much
smaller fraction of current compared to Lb1 at all conditions.
Inductor Lb1 is expected to have a higher average current because
it is always conducting, regardless of whether the switch is
turned ON or OFF. This statement is true regardless of the kind
of discharge in the upper and lower capacitors.
VI. DISCUSSION
Usefulness of the presented two-stage high-resolution PV
inverter is analyzed in this section from component requirement,
leakage current, and efficiency perspective, respectively, as dis-
cussed in the following sections.
A. Component Requirement and Efficiency
There are number of factors that affect the cost of a power
electronic converter. However, among them, two factors are
considered, which affects the cost substantially, which are men-
tioned as follows.
1) Number of components.
2) Rating of components.
There is about 1.3 times increment in cumulative volt–ampere
(VA) rating of the power semiconductor switches (due to TNPC
converter) in the inverter part and nearly 2 times in the dc–dc
converter part (due to high blocking voltage of switch used in
coupled inductor-based dc–dc converter). However, component
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5395
TABLE III
COST COMPARISON
count (no. of gate drivers, switches, and heat sinks) will remain
same w.r.t. prior art shown in Fig. 1. Moreover, increase in VA
rating of power semiconductor switches (increase in chip area)
does not necessarily result into proportional increase in cost due
to other materials and manufacturing cost (nearly fixed cost)
associated with a power semiconductor module. Moreover, it is
important to note that the cost of module is a smaller fraction
compared to total cost of the system, which includes cost related
to controller, cabinet, GUI, heat sink, cabling, assembly, etc.
Cost of these components will remain almost unaffected. In-
verter cost is determined by number of components. Component
cost keeps on changing with power rating, component availabil-
ity, inflation, and geographical location of the manufacturer and
buyer. An indicative figure is provided in Table III on the basis of
statistical data related to transformer and inverter cost for same
power rating.
In a typical transformer-isolated PV inverter, transformer cost
is near about 40% of total system cost. Overall cost of inverter
owing to higher power rating of switches (only for main bridge
and dc–dc converter) is expected to increase the total converter
cost by less than 10%. In standard inverter, 65% is the cost of
power electronic circuitry, so in presented work, converter cost
may increase to 72% approximately. Hence, a tentative idea of
total system cost is highlighted in Table III. A power frequency
transformer also contributes a major components of system
losses. Hence, removal of transformer, small size of filter (owing
to high-resolution output voltage), and low switching losses
together can ensure better efficiency or at least no compromise
in efficiency other than its superior performance, as discussed
in earlier sections.
B. Leakage Current
PV inverters connected to the grid without a transformer
present a significant challenge when it comes to restrict the PV
array leakage current, which flows through terminal to frame
capacitance known as leakage capacitor. Leakage current limits
are specified by the German VDE0126-1-1 standard. For low
power rating, as per standards, common-mode leakage current
should be below 300 mA. However, in presented work, even
for high power (70 kWp), leakage current is restricted below
200 mA, as shown in Fig. 11.
C. Comparison of Well-Known Multilevel Inverter
Topologies
In order to evaluate the merits and limitations of the proposed
hybrid converter topology, well-known converter topologies for
two-stage grid-connected solar PV applications are compared
5396
TABLE IV
COMPARISON OF VARIOUS TWO-STAGE CONVERTER TOPOLOGIES
to the number of output voltage levels. The topologies have
been compared using a baseline of 12 switches (per phase).
In this comparison, it is considered that dc buses of three
phases are merged in order to limit capacitor voltage ripple.
All the three phases are fed by a common PV array, which
will eliminate the interarray leakage current. However, three
isolation transformers are required in order to merge three dc
buses. Whereas, in present with this three-phase single-sourced
double-stage transformerless converter topology in Table IV.
One of the most important aspects of the proposed MLI topology
is the elimination of isolated auxiliary dc power sources through
a fair tradeoff in converter topology, isolation transformers are
removed, three-phase H-bridges are replaced by TNPC, and
one additional converter is added to balance the capacitors of
double LDN-based converter topology. It is well known that for
two-stage converter topology, dc–dc converter is required and
that dc–dc converter is customized in such a way that it will help
to balance capacitor voltages as well as to remove three isolation
transformers.
In proposed converter topology, as input capacitor of TNPC
comes in parallel to stray capacitance, this ensures the leakage
current within permissible limits. In order to remove isolation
transformer, TCVAR becomes high as compared to other con-
verter topologies, as mentioned in Table IV. TCVAR is ratio of
cumulative VA (CVA) rating of total switches to VA rating of
inverter, as given in (23). Table IV indicates that the transformer
is removed in the presented topological configuration by trading-
off with cumulative VA rating of switches. It is apparent from
the comparison that the proposed topology has 50% higher CVA
rating. Though, the number of switches and corresponding gate
drivers will remain same w.r.t. prior arts indicated in Table IV and
increased CVA rating will not have proportional impact on the
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cost. Removal of isolation transformer of full converter rating
will reduce the overall implementation cost and increase the
efficiency of PV plant with some tradeoff in CVA rating.
The switch utilization factor (SUF) is analysed with respect
to a standard single-phase full-bridge inverter. For which the
CVA rating of the switches is eight times higher than the VA
rating of the inverter. SUF is inversely proportional to the ratio
of TCVAR of the H-bridge to the ratio of TCVAR of the given
converter topology. It is important to note that keeping the
number of switches unchanged with reduced utilization factor
is not expected to increase the implementation cost of the total
system in linear proportion
CVA rating of total switches
TCVAR = (23)
VA rating of inverter
Hbridge
SUF = TCVAR /TCVAR . (24)
The cost of the gate driver circuits will not differ significantly
compared to the topologies mentioned in Table IV. Owing to
nearly same efficiency w.r.t. standard topologies, the heat sink
volume will not change significantly. Considering the require-
ment of limited computational resources, the controller cost is
also expected to be unaffected. On the contrary, this topology
has advantages because it does not require an auxiliary dc
supply, and three isolation power frequency transformers of the
full-scale converter rating are removed, which reduces the imple-
mentation cost by 35%–50%. In the proposed hybrid converter,
the switching loss is negligible since the TNPC operates close to
the fundamental switching frequency and auxiliary cells operate
at around 1 to 2 kHz. Proper selection of switches also helps
to limit the conduction losses. Due to high power quality of
this converter topology, filter losses will be absent. In this way,
TAK AND CHATTOPADHYAY: THREE-PHASE TRANSFORMERLESS HYBRID MULTILEVEL INVERTER FOR SOLAR PV APPLICATION
TABLE V
COMPARISON OF TRANSFORMERLESS TOPOLOGIES
this topology provides an efficient, reliable, and cost-effective
converter solution.
A few potential transformerless topologies are compared
w.r.t. major parameters in Table V. Other than NPC (or its
variants, such as T-NPC), most of the transformerless topologies
presented in the literature are for single-phase and low-power
applications. In those topologies, also additional switch/circuit is
added to remove the transformer. Moreover, for those topologies,
switching losses and filter losses are much higher than the pro-
posed solution. Key merits and the limitations of the presented
work can be identified in this table.
D. Reliability of Proposed Converter Topology
Reliability analysis of the proposed topology can be broken
into two parts: Reliability of the dc–dc converter (mostly de-
termined by switch Sb ) and reliability of the inverter consisting
large number of switches.
Reliability issues due to switch Sb can be addressed by having
multiple dc–dc converter units connected to same inverter. This
is a common practice in a large-scale two-stage PV inverters to
have multiple dc–dc converters (i.e., multiple MPPT trackers)
[31], [32]. In the proposed configuration, voltage and current
stress in the coupled inductor-based dc–dc converter is also not
significantly high compared to the well-known dc–dc converters
used in two-stage applications.
Reliability issue for the inverter part is achieved by ensuring
lower junction temperature of the power semiconductor devices
due to significantly lower conduction loss per switch and neg-
ligible overall switching loss. It is found that the overall effi-
ciency of the converter (even without considering filter losses)
is competitive (or even better) with the standard topologies
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5397
with limited switches. Since this loss is distributed in several
devices, corresponding junction temperatures are restricted to
substantially lower value (40–50 °C lower than two-level case).
Lower junction temperature has two-fold effect on failure rate:
Peak junction temperature is reduced, and temperature variations
during thermal cycling is also reduced. As a consequence, failure
rate of individual devices can be lowered by a factor as high as
100 or even much higher. Considering this, overall reliability
is expected to be comparable or improved w.r.t. presently used
topologies.
VII. CONCLUSION
A grid-connected two-stage transformerless multilevel con-
verter for utility-scale solar PV application was presented in
this article. Hybridization of TNPC with double LDN-based
topology was done to remove isolation transformers. The dc–dc
converter for MPPT in two-stage solar PV inverter was cus-
tomized in this work to balance the TNPC capacitors and double
the inverter’s power handling capacity. No extra converter and
controller were needed to balance capacitor voltages. Hence,
complexity and cost related to controller were negligible in
presented work. The key benefit of the proposed work was the
use of a single PV source in a complete converter topology
that does not require any isolation transformer or any auxiliary
power supply. This converter topology also kept leakage current
within acceptable limits without adding any additional circuit
elements. High-resolution output voltage of presented inverter
was expected to offer an efficient and reliable converter solution
for PV central-inverter application. This article presented a thor-
ough simulation study, analysis, as well as experimental results.
The experimental results acquired from a hardware prototype
resembled well with the simulation results.
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Neha Tak (Student Member, IEEE) received the
B.Tech. degree in electrical and electronics en-
gineering from Rajasthan Technical University,
Udaipur, India, in 2012, and the M.Tech. degree
in electric drives and power electronics from the
Indian Institute of Technology Roorkee, Roor-
kee, India, in 2016. She is currently working to-
ward the Ph.D. degree in power electronics spe-
cialization with the Department of Energy Sci-
ence and Engineering, Indian Institute of Tech-
nology Delhi, New Delhi, India.
She has 4.5 years’ experience in industry as well as in academics.
Her research interests include multilevel inverter and power electronic
converter for solar PV application.
Sumit K. Chattopadhyay (Member, IEEE) re-
ceived the B.E. degree in electrical engineer-
ing from Burdwan University, Burdwan, India, in
2004, the M.Tech. degree in industrial electrical
systems from the National Institute of Technol-
ogy Durgapur, Durgapur, India, in 2006, and
the Ph.D. degree in electrical engineering from
the Department of Electrical Engineering, Indian
Institute of Technology Kharagpur, Kharagpur,
India, in 2016.
He has about five years of industrial experi-
ence in power electronic system design. In 2018, he joined the Depart-
ment of Energy Science and Engineering, Indian Institute of Technology
Delhi, New Delhi, India, where he is currently an Assistant Professor. His
research interests include development of reliable and efficient power
electronic converters for renewable energy, electric vehicles, and other
industrial applications.