7256 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO.

8, AUGUST 2019

High-Conversion-Ratio Isolated Bidirectional

DC–DC Converter for Distributed Energy
Storage Systems
Junlong Lu , Member, IEEE, Yi Wang , Member, IEEE, Xin Li , and Changliang Du

Abstract—In this paper, a novel high-conversion-ratio isolated

bidirectional dc–dc converter for distributed energy storage sys-
tems is proposed. In the buck mode, the proposed converter is
equivalent to that of a cascade consisting of an isolated buck–boost
converter and a buck converter, thus achieving a high step-down
ratio. Likewise, in the boost mode, the converter is equivalent to the
cascaded structure consisting of a boost converter and an isolated
buck–boost converter, and then, a high step-up ratio is achieved.
Therefore, the proposed topology exhibits a high conversion ra-
tio with low transformer turns ratio, improving the efficiency of
high-frequency transformers and the integration and reliability of
the control system. In addition, voltage spikes caused by the leak-
age inductance can be avoided as the leakage inductance energy
is released to capacitors in a high-voltage side or a low-voltage Fig. 1. Diagram of the typical distributed generation system.
side. Moreover, a zero-voltage-switching (ZVS) operation reduces
switching losses and improves the conversion efficiency. The oper-
ating principles and theoretical derivations of the proposed con-
verter along with ZVS implementations are discussed in detail in between the dc bus and either the battery or the ultracapaci-
this paper. Furthermore, the validity and performance of the pro- tor to provide a bidirectional flow of energy. Specifically, the
posed converter are verified using a prototype with 600-V high battery or ultracapacitor is charged through the converter when
voltage, 48-V low voltage, and 2-kW output power. the output power of the photovoltaic panel or fuel cell is large,
Index Terms—Bidirectional dc–dc converter, energy storage, whereas they discharge through the converter to stabilize the
high conversion ratio, zero-voltage switching (ZVS). dc-bus voltage when the output power of the photovoltaic panel
I. INTRODUCTION or fuel cell declines.
Several studies have addressed bidirectional dc–dc convert-
VER-increasing developments on distributed generation
E have derived in abundant research over recent years. Still,
the intermittent power generated by distributed generation sys-
ers, with many of them focusing on non-isolated converters
given their simple structure and low cost. For instance, bidi-
rectional dc–dc converters based on interleaved techniques are
tems must be processed before supplying a stable and contin- discussed in [5] and [6]. These converters exhibit a low output
uous output. To this end, distributed generation systems com- current ripple, which decreases as more phases are included.
monly rely on energy storage units. Bidirectional dc–dc con- However, this structure is usually unable to provide a high con-
verters are essential components to achieve energy storage and version ratio. Furthermore, its current-sharing scheme increases
stable output power [1]–[4]. Fig. 1 shows the diagram of a typ- the complexity of the control system. In contrast, the converters
ical distributed generation system with energy storage units, proposed in [7]–[10] deliver a high conversion ratio through
where the bidirectional dc–dc converter is the essential link coupled inductors. Still, additional voltage clamping circuits
are required to eliminate voltage spikes caused by the leakage
Manuscript received June 17, 2018; revised September 10, 2018; accepted inductance. To mitigate voltage spikes, the topology proposed
November 7, 2018. Date of publication November 14, 2018; date of current in [11] integrates dual active half-bridge circuits into the con-
version May 22, 2019. This work was supported by the National Natural Science ventional buck–boost bidirectional dc–dc converter. In addition,
Foundation of China under Grant 51677035. Recommended for publication by
Associate Editor M. Amirabadi. (Corresponding author: Yi Wang.) the conversion ratio is increased through a coupled inductor and
J. Lu, Y. Wang, and X. Li are with the Power Electronics and Electrical Drives a voltage doubler cell. However, this topology has a narrow
Research Center, Harbin Institute of Technology Shenzhen Graduate School, operating range of the duty cycle and high voltage stress on
Shenzhen 518055, China (e-mail:,junlonglu@163.com; wangyisz@hit.edu.cn;
973688371@qq.com). the switches, thus limiting its applicability. In [12], a two-stage
C. Du is with Xi’an XD High Voltage Apparatus Co., Ltd., Xi’an 710018, converter implemented with two cascaded boost converters is
China (e-mail:,313324534@qq.com). proposed, but the high voltage and current stress sharply re-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. duces its efficiency according to the voltage difference between
Digital Object Identifier 10.1109/TPEL.2018.2881085 the input and output voltages.
0885-8993 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS
Unlike non-isolated converters, isolated bidirectional dc–dc
converters provide large conversion ratios and galvanic isola-
tion, thus being more suitable for different applications. To
reduce voltage spikes caused by the leakage inductance, a
converter with an active flyback and two passive capacitor–
diode snubbers is proposed in [13]. However, the extra snubber
networks consisting of many components increase the circuit
complexity and reduce the conversion efficiency. Alternatively,
dual-active-bridge converters have been widely used due to their
high performance and reliability [14]–[19]. The extended phase-
shift control strategy of the bridge circuit is introduced in [14],
and it features an inner phase-shift control that can reduce the
backflow power compared to the traditional phase-shift control.
However, this strategy results in a narrow range of zero-voltage
switching (ZVS) and high switching losses. Another dual-phase-
shift control strategy for dual-active-bridge converters adding
efficiency and power-density optimization is presented in [15].
However, the voltage conversion ratio is low, thus making the
converter unsuitable for applications with a large voltage differ-
ence. To both expand the scope of soft-switching and improve
the steady-state performance of the converter, a triple-phase-
shift control strategy is presented in [16]–[19]. Unfortunately,
the fixed inner phase-shift duty cycle reduces the maximum
output power of the converter under the same circuit parame-
ters. Furthermore, the control system complexity reduces the
stability and reliability of the converter.
A bidirectional flyback converter is proposed in [20] to
achieve a high voltage conversion ratio. However, the trans-
mitted power of this converter is limited because the energy is
stored into the transformer. A soft-switching bidirectional LLC
resonant topology that can change the output power and power
flow direction by regulating the switching frequency is proposed
in [21]. However, the voltage across the magnetizing inductance
of the transformer is clamped by the input voltage in the boost
mode and the resonant tank becomes LC resonance, which lim-
its the voltage gain in the boost mode. In order to solve the
problem in the traditional bidirectional LLC resonant converter,
a bidirectional CLLC converter is proposed and designed in [22]
to achieve bidirectional symmetrical operation in both forward
and reverse modes. This converter can be easily extended for
high power applications.
In this paper, a novel high-conversion-ratio isolated bidirec-
tional dc–dc converter for distributed energy storage systems
is proposed. A high conversion ratio is achieved with a low
transformer turns ratio, thus improving efficiency. In addition,
voltage spikes can be avoided as the energy from the leakage
inductance is reused at the output. Moreover, ZVS can be re-
alized in both the discontinuous conduction mode (DCM) and
continuous conduction mode (CCM). The operation principles
of the proposed converter in both the buck and boost modes
are introduced in Section II. Section III presents the theoretical
derivations, parameters selections, and ZVS operations analy-
sis. Section IV gives the comparisons between the proposed
converter and other similar converters. Then, the experimental
results are provided in Section V. Finally, conclusions are drawn
in Section VI.
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7257
Fig. 2. Topology of the proposed converter.
II. OPERATING PRINCIPLES OF THE PROPOSED CONVERTER
Fig. 2 shows the topology of the proposed bidirectional dc–dc
converter, where N is the turns ratio of the transformer Tr , V1
is the voltage in the high side (i.e., dc-bus side), and V2 is the
voltage in the low side.
Because the leakage inductance can be equivalent to an in-
ductor connected to the primary winding of the transformer Tr
in series, in order to simplify analysis, the inductor L1 in this
paper represents the sum of the leakage inductance of the trans-
former Tr and that of the external inductor series connected to
the primary winding in the real system. Thus, the energy stored
in the leakage inductance is contained in L1 . When energy is
transferred from the high- voltage to the low-voltage side, the
converter operates in the buck mode, whereas the opposite en-
ergy transference corresponds to operation in the boost mode. As
shown in Fig. 2, the battery or ultracapacitor is usually connected
to the low-voltage side of the converter, and hence, continuous
charging or discharging currents are required to avoid high peak
currents. Therefore, in both buck and boost modes, inductor L2
should be designed to operate in the CCM. Nevertheless, in-
ductor L1 may operate in either DCM or CCM depending on
the load, switching frequency, and inductance. Consequently,
the converter operation in the DCM or CCM implies the L1
operation in the corresponding mode.
To simplify the circuit analysis, the following assumptions
are made in this paper.
1) The switches and diodes are regarded as ideal devices, i.e.,
the ON-resistance and forward voltage drop are neglected.
2) Capacitors C1 , C2 , and C3 are large, and their respective
voltages VC 1 , VC 2 , and VC 3 are constant.
A. Buck Mode
Fig. 3 shows the switching sequence diagram when the con-
verter operates in the buck mode, where Ts is the switching
cycle of S1 –S4 , D1 is the percentage of time interval [t0 , t1 ] in
Ts , and Dd is the percentage of the dead time in Ts . In Fig. 3(a),
inductor L1 operates in the CCM, and Δ1 is the percentage of
time interval [t1 , t2 ] in Ts . In Fig. 3(b), inductor L1 operates in
the DCM, β1 is the percentage of the time interval [t1 , t3 ] in
Ts . Switches S6 and S8 are always turned OFF during the buck
mode.
As shown in Fig. 3(a), the converter has ten operation stages
during one switching cycle when operating in the CCM of the
buck mode. The value of D1 determines the output power. Fig. 4
illustrates the current flow in the CCM for the buck mode.
 7258
Fig. 3. Switching sequence diagram of the buck mode. (a) CCM. (b) DCM.
The switching frequency of S5 , S7 , and S9 is twice that of S1 –S4
when the converter operates in this mode.
Stage 1 [t0 –t1 ]: At t0 , S2 , S5 , S7 , and S9 are turned ON. As
L1 operates in the CCM, iL 1 has not decreased to zero at t0 .
Therefore, in this stage, L1 still operates in the freewheeling
state. This freewheeling state lasts until iL 1 decreases to zero at
t1 . Meanwhile, L2 is charged through S9 and C2 by the capacitor
voltage VC 3 .
Stage 2 [t1 –t2 ]: At t1 , iL 1 decreases to zero. Then, L1 is
charged through S3 , S7 , S5 , and S2 by V1 . The direction of iL 1
has changed compared with that in Stage 1 and the energy is
stored into L1 . Because S7 is turned ON in this stage, the current
will flow through the drain–source channel instead of the body
diode. In this case, S7 operates in the synchronous rectification
state, which reduces the conduction loss.
Stage 3 [t2 –t3 ]: At t2 , S3 , S5 , S7 , and S9 are turned OFF.
However, S4 will not be turned ON at t2 due to the dead time.
During the dead time [t2 , t3 ], inductor L1 freewheels through
S2 and the body diodes of S4 , S7 , and S6 . The energy in L1 is
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019
released to C3 . At the same time, L2 freewheels through C2 , V2 ,
and D3 .
Stage 4 [t3 –t4 ]: At t3 , switch S4 is turned ON. Then, L1 free-
wheels through S2 , S4 , and the body diodes of S7 and S6 . The
difference between stage 3 and stage 4 is that S4 operates in the
synchronous rectification state in this stage.
Stage 5 [t4 –t5 ]: At t4 , S2 is turned OFF. However, S1 , S5 , S7 ,
and S9 will not be turned ON at t4 due to the dead time. Like in
stage 1, iL 1 has not decreased to zero. Therefore, in this stage,
L1 still operates in the freewheeling state. Unlike the case in
stage 4, L1 freewheels through S4 and the body diodes of S1 , S7 ,
and S6 in this stage.
Stage 6 [t5 –t6 ]: At t5 , S1 , S5 , S7 , and S9 are turned ON. Then,
the current-flow path changes and L1 freewheels through S1 , S4 ,
S7 , and S5 . This freewheeling state lasts until iL 1 decreases to
zero. Meanwhile, L2 is charged through S9 and C2 by VC 3 .
Stage 7 [t6 –t7 ]: At t6 , iL 1 decreases to zero. Then, L1 is
charged through S1 , S5 , S7 , and S4 by V1 . The operating principle
in this stage is similar to that of in stage 2. However, the current
 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7259

Fig. 4. Current-flow paths in the buck mode for the CCM. (a) Stage 1 [t0 –t1 ]. (b) Stage 2 [t1 –t2 ]. (c) Stage 3 [t2 –t3 ]. (d) Stage 4 [t3 –t4 ]. (e) Stage 5 [t4 –t5 ].
(f) Stage 6 [t5 –t6 ]. (g) Stage 7 [t6 –t7 ]. (h) Stage 8 [t7 –t8 ]. (i) Stage 9 [t8 –t9 ]. (j) Stage 10 [t9 –t1 0 ].

direction of iL 1 in this stage is opposite to that of in stage 2,
that is, iL 1 increases in the opposite direction. S5 operates in
synchronous rectification state. At the same time, like the case
in stage 6, L2 is charged through S9 and C2 by VC 3 .
Stage 8 [t7 –t8 ]: At t7 , S4 , S5 , S7 , and S9 are turned OFF.
However, S3 will not be turned ON at t7 due to the dead time.
Then, L1 freewheels through S1 and the body diodes of S3 , S5 ,
and S8 . Then, the energy in L1 is released to C3 . At the same
time, L2 freewheels through C2 , V2 , and D3 . The operating
process in this stage is similar to that of in stage 3.
Stage 9 [t8 –t9 ]: At t8 , S3 is turned ON. Then, L1 freewheels
through S3 , S1 , and the body diodes of S5 and S8 . The difference
between stage 8 and stage 9 is that S3 operates in the synchronous
rectification state in this stage.
Stage 10 [t9 –t10 ]: At t9 , S1 is turned OFF. However, S2 , S5 ,
S7 , and S9 will not be turned ON at t9 due to the dead time.
Because iL 1 has not decreased to zero, L1 still operates in the
freewheeling state in this stage. Unlike the case in stage 9, L1
freewheels through S3 and the body diodes of S2 , S5 , and S8 in
this stage.
Fig. 3(b) depicts the switching sequence diagram of the DCM
in the buck mode. As shown in Fig. 3(b), when the proposed
converter operates in the DCM, the inductor current iL 1 de-
creases to zero before S2 is turned OFF in the positive half cycle.
Similarly, iL 1 decreases to zero before S1 is turned OFF in the
negative half cycle. The main operating principle of the DCM
is similar to that of the CCM.
B. Boost Mode
Fig. 5 shows the switching sequence diagram when the con-
verter operates in the boost mode, where Ts is the switching

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 7260
Fig. 5. Switching sequence diagram in the boost mode. (a) CCM. (b) DCM.
cycle, D2 is the duty cycle of S3 , S4 , S6 , and S8 , and Dd is
the percentage of the dead time in Ts . In Fig. 5(a), inductor L1
operates in the CCM, Δ2 is the percentage of the time interval
[t1 , t2 ] in Ts . In Fig. 5(b), inductor L1 operates in the DCM, β2
is the percentage of the time interval [t1 , t3 ] in Ts . Switches S1
and S2 remain turned OFF during the boost mode.
As shown in Fig. 5, the converter has ten operation stages in
one switching cycle when operating in the CCM of the boost
mode. The value of D2 determines the output power. The switch-
ing frequency of S9 is twice that of the other switches when the
converter operates in this mode. Fig. 6 illustrates the current
flow in the CCM during the boost mode.
Stage 1 [t0 –t1 ]: At t0 , S4 and S6 are turned ON. Then, L2 is
charged through D2 and S6 by V2 . As L1 operates in the CCM,
iL 1 has not decreased to zero at t0 . Therefore, in this stage, L1
still operates in the freewheeling state. This freewheeling state
lasts until iL 1 decreases to zero.
Stage 2 [t1 –t2 ]: At t1 , iL 1 decreases to zero. Then, L1 is
charged through S7 , S4 , the body diode of S2 , and S6 by VC 3
and the energy is stored into L1 . Meanwhile, L2 continues to be
charged in this stage.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019
Stage 3 [t2 –t3 ]: At t2 , S4 , and S6 are turned OFF. However, S5
and S9 will not be turned ON a t2 due to the dead time. During
the dead time [t2 , t3 ], L1 freewheels through S7 and the body
diodes of S3 , S2 , and S5 . Energy in L1 is released to V1 and iL 1
decreases linearly. At the same time, L2 freewheels through C3 ,
V2 , and the body diode of S9 and energy in L2 is released to C3 .
Stage 4 [t3 –t4 ]: At t3 , switches S5 and S9 are turned ON. In this
stage, both L1 and L2 continue to operate in the freewheeling
state. The difference between stage 4 and stage 3 is that both S5
and S9 operate in the synchronous rectification state in this stage.
Stage 5 [t4 –t5 ]: At t4 , S7 and S9 are turned OFF. However,
S3 and S8 will not be turned ON at t4 due to the dead time.
Because iL 1 has not decreased to zero, L1 still operates in the
freewheeling state in this stage. Unlike the case in stage 4, L1
freewheels through S5 and the body diodes of S3 , S2 , and S8 in
this stage. Meanwhile, L2 freewheels through C3 , V2 , and the
body diode of S9 .
Stage 6 [t5 –t6 ]: At t5 , S3 and S8 are turned ON. Then, L2 is
charged through D1 and S8 by V2 . In this stage, L1 freewheels
through S3 , S5 , S8 , and the body diode of S2 . This freewheeling
state lasts until iL 1 decreases to zero.
 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7261

Fig. 6. Current-flow paths in the boost mode for the CCM. (a) Stage 1 [t0 –t1 ]. (b) Stage 2 [t1 –t2 ]. (c) Stage 3 [t2 –t3 ]. (d) Stage 4 [t3 –t4 ]. (e) Stage 5 [t4 –t5 ].
(f) Stage 6 [t5 –t6 ]. (g) Stage 7 [t6 –t7 ]. (h) Stage 8 [t7 –t8 ]. (i) Stage 9 [t8 –t9 ]. (j) Stage 10 [t9 –t1 0 ].

Stage 7 [t6 –t7 ]: At t6 , iL 1 decreases to zero. Then, L1 is
charged through S5 , S3 , S8 , and the body diode of S1 by VC 3 .
The inductor current iL 1 increases in the opposite direction and
energy is stored into L1 . Meanwhile, L2 continues to be charged
in this stage.
Stage 8 [t7 –t8 ]: At t7 , S3 and S8 are turned OFF. However, S7
and S9 will not be turned ON at t7 due to the dead time. Then, L2
freewheels through C3 , V2 , and the body diode of S9 and energy
in L2 is released to C3 . Meanwhile, L1 freewheels through S5
and the body diodes of S1 , S4 , and S7 . Thus energy in L1 is
released to V1 .
Stage 9 [t8 –t9 ]: At t8 , S7 and S9 are turned ON. In this stage,
both L1 and L2 continue to operate in the freewheeling state.
The difference between stage 9 and stage 8 is that both S7
and S9 operate in the synchronous rectification state in this
stage.
Stage 10 [t9 –t10 ]: At t9 , S5 and S9 are turned OFF. However,
S4 and S6 will not be turned ON at t9 due to the dead time.
Because iL 1 has not decreased to zero, L1 still operates in the
freewheeling state in this stage. Unlike the case in stage 9, L1
freewheels through S7 and the body diodes of S1 , S4 , and S6 in
this stage. Meanwhile, L2 freewheels through C3 , V2 , and the
body diode of S9 .
Fig. 5(b) depicts the switching sequence diagram of the DCM
in the boost mode. As shown in Fig. 5(b), when the proposed
converter operates in the DCM in the boost mode, iL 1 decreases
to zero before S7 and S9 are turned OFF in the positive half cycle.
Similarly, iL 1 decreases to zero before S5 and S9 are turned OFF
in the negative half cycle.
Overall, the proposed converter can achieve a high step-down
ratio in the buck mode through an equivalent cascade structure
of an isolated buck–boost converter and a buck converter, and a

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 7262 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019

Hence, the voltage gain in the CCM can be expressed as

V2 4D1 (2Δ1 − D1 − Dd )
= . (2)
V1 N (1 − 2D1 )
In addition, average current I1 at the high-voltage side can be
calculated by
 t5 
1 2 1 V1
I1 = i1 (t)dt = Δ1 Ts Δ1 Ts
Ts /2 t 0 Ts 2 L1
1 V1
− (D1 − Δ1 )Ts (D1 − Δ1 )Ts
2 L1

1 2V1 V1 + NVC 3
− (D1 − Δ1 )Ts + Dd Ts Dd Ts
2 L1 L1
Fig. 7. Equivalent circuits of the proposed converter in the buck mode. V1 D1 (2Δ1 − D1 ) Dd
(a) First stage structure. (b) Second stage structure. = + [4V1 D1 (Δ1 − D1 )
L1 fs 2D1 L1 fs

high step-up ratio in the boost mode through an equivalent cas- − (2D1 V1 + N V2 )Dd ]. (3)
cade structure of a boost converter and an isolated buck–boost In an ideal scenario, the input power is equal to the output
converter. Therefore, a low turns ratio delivers a high conver- power, and thus, I1 is given by I1 = V2 I2 /V1 , where I2 is the
sion ratio, thus improving the transformer efficiency. Moreover, average current at the low-voltage side. When L1 operates in
the energy from the leakage inductance is reused at the out- the critical conduction mode, Δ1 is given by Δ1 = D1 . By
put capacitors in both buck and boost modes to prevent voltage substituting Δ1 = D1 into (2) and combining (3) with I1 =
spikes. V2 I2 /V1 , the average current I2 crit at the low-voltage side in
the critical conduction mode is given by
III. THEORETICAL DERIVATION AND ANALYSIS
V12 D12 V 2 Dd 2 V 1 N Dd 2
A. Derivation in the Buck Mode I2 crit = − 1 − . (4)
V2 L1 fs V2 L1 fs 2D1 L1 fs
The proposed converter is equivalent to a two-stage structure By substituting Δ1 = D1 into (2) and combining (2) with (4),
during the buck mode operation. Specifically, energy is trans- I2 crit is given by
ferred from V1 to VC 3 and from VC 3 to V2 in the first and sec- 
ond stages, respectively. The equivalent circuits of the proposed (1 − 2D1 )2 N 2 V2 Dd 2 2(D1 − Dd )Dd 2
I2 crit = 2 1− 2 − .
converter in the buck mode are shown in Fig. 7, where switches 16(D1 − Dd ) fs L1 D1 (1 − 2D1 )D12
Sa and Sb in Fig. 7(a) share the driving signal, and NVC 3 is (5)
obtained by the equivalent transformation of VC 3 through the
transformer. When switches Sa and Sb are closed, inductance By substituting V2 = I2 R2 into (5) and assuming R2 is the
L1 is charged through them by V1 , whereas when they are open, equivalent load resistor in the buck mode. Then, the CCM con-
L1 freewheels through Db , C3 , and Da . Therefore, the circuit in dition is determined by
Fig. 7(a) is equivalent to a buck–boost converter, and the circuit (1 − 2D1 )2 I2
in Fig. 7(b) corresponds to a buck converter. According to the I2 > I2 crit =
(D1 − Dd )2 Kbuck
2
operating principle of the buck mode, during the positive half 
cycle, Sa and Sb in Fig. 7(a) represent S2 , S3 , S5 , and S7 in Dd 2 2(D1 − Dd )Dd 2
× 1− 2 − (6)
Fig. 2. Meanwhile, Da and Db in Fig. 7(a) represent S2 , S4 , and D1 (1 − 2D1 )D12
the body diodes of S6 and S7 . During the negative half cycle, √ √
Sa and Sb in Fig. 7(a) represent S1 , S4 , S5 , and S7 in Fig. 2. where Kbuck = 4 fs L1 /(N R2 ).
Meanwhile, Da and Db in Fig. 7(a) represent S1 , S3 , and the Then, the CCM condition is given by
body diodes of S5 and S8 . Kbuck > Kbuck crit (D1 ) (7)
When the converter operates in the CCM, as shown in
Fig. 3(a), the volt–second balance law can be applied to both L1 where
within [t1 , t6 ] and L2 within [t0 , t5 ], yielding Kbuck crit (D1 ) = f1 (D1 )
⎧
⎪ Ts
⎪
⎪ V1 Δ1 Ts = N VC 3 (1 − 2D1 − 2Dd ) +(V1 +N VC 3 )Dd Ts 1 − 2D1 Dd 2 2(D1 − Dd )Dd 2
⎪
⎨ 2 = 1− 2 − .
+V1 (D1 − Δ1 )Ts D1 − Dd D1 (1 − 2D1 )D12
⎪
⎪
⎪
⎪ Ts Ideally, the dead time can be ignored, and Kbuck crit (D1 ) can
⎩ (VC 3 − V2 )D1 Ts = V2 (1 − 2D1 ) .
2 be simplified as (1 − 2D1 )/D1 . Actually, in the experiment, the
(1) dead time usually accounts for a very small proportion of the

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7263

Fig. 8. Boundary between CCM and DCM in the buck mode. Fig. 9. Dead-time effect on the voltage gain in the buck mode.

whole switching cycle. Therefore, let Dd = 0.02 in this paper. where 0 < D1 < [f1 −1 (Kbuck ) − Dd ].
According to (7), the boundary between the CCM and DCM According to aforementioned analysis, the voltage gain when
can be obtained in Fig. 8, where Kbuck > Kbuck crit (D1 ) cor- considering the dead time in the buck mode is shown in (8) and
responds to the CCM operation, and Kbuck < Kbuck crit (D1 ) (12). Then, when the dead time is ignored, the voltage gain can
corresponds to DCM operation. Fig. 8 shows the different be simplified as
value of Kbuck corresponds different critical duty cycle, for
V2
example, when Kbuck = 3.6, the critical duty cycle is 0.2, =
which means D1 ∈ [0, 0.2] corresponds to DCM operation and V1
⎧
D1 ∈ [0.2, 0.5] corresponds to CCM operation. ⎪ 4D1 1
⎪
⎨ MDCM buck = 0 < D1 ≤
By combining (2) and (3), the voltage gain in the CCM is N Kbuck Kbuck + 2
calculated by ⎪ 4(1 − 2D1 ) 1
⎪
⎩ MCCM = < D1 < 0.5 .
buck 2
V2 N Kbuck Kbuck + 2
MCCM buck =
V1 (13)

4 Dd (1 − 2D1 ) − 2Dd 2 By substituting Dd = 0.02, N = 3, and Kbuck = 3.6 into (8),
= 2 1 − 2D1 +
N Kbuck D1 (12), and (13), the voltage-gain curve in the buck mode can
(8) be obtained, as shown in Fig. 9. According to the switching
sequence diagram in Fig. 3(b), when the converter operates in
where f1 −1 (Kbuck ) < D1 < 0.5. the DCM, the inductor current iL 1 (t) has reduced to zero before
Similar to the CCM, when the converter operates in the DCM, the state transition of switches, then iL 1 (t) is always zero during
as shown in Fig. 3(b), during [t0 , t5 ], the volt–second balance the dead time, which means the dead time does not affect the
law can be applied to L1 and L2 separately, so operating process in the DCM. Fig. 9 shows that the dead-time
⎧
⎨ V1 D1 Ts = NVC 3 β1 Ts does not affect the step-down ratio in the DCM and has small
(9) effect on the step-down ratio in the CCM.
⎩ (VC 3 − V2 )D1 Ts = V2 (1 − 2D1 ) Ts . By substituting Kbuck = 3.6 and the prototype parameters
2
from Table I into (8) and (12), the voltage-gain curve under
By simplifying (9), then V2 can be expressed as different turns ratio N and similar load condition in the buck
2V1 D12 mode can be obtained, as shown in Fig. 10, where a high step-
V2 = . (10) down ratio is achieved with a low transformer turns ratio.
N β1
As seen from the operating principles in the DCM, average
B. Derivation in the Boost Mode
current I1 at the high-voltage side can be calculated by
 t2 Like in the buck mode, the proposed converter exhibits a
1 2 1 V1 V1 D12 two-stage structure during the boost mode operation. Specifi-
I1 = i1 (t)dt = D1 Ts D1 Ts = .
Ts /2 t 0 Ts 2 L1 L1 fs cally, energy is transferred from V2 to VC 3 and from VC 3 to
(11) V1 in the first and second stages, respectively. The equivalent
Then, the voltage gain in the DCM can be calculated by circuits for the converter in the boost mode are shown in Fig. 11,
where Fig. 11(a) corresponds to a boost converter, and Fig. 11(b)
V2 4D1 corresponds to a buck–boost converter with switches Sd and Se
MDCM buck = = (12)
V1 N Kbuck sharing the driving signal, and NVC 3 is obtained by the equiva-

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 7264 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019

TABLE I lent transformation of VC 3 through the transformer. According

MAIN CIRCUIT PARAMETERS
to the operating principle of the boost mode, during the positive
half cycle, Sc in Fig. 11(a) represents S6 in Fig. 2, while Sd and
Se in Fig. 11(b) represent S4 , S6 , and S7 in Fig. 2. Meanwhile,
Dc in Fig. 11(a) represents the body diode of S9 in Fig. 2. Dd
and De in Fig. 11(b) represent the body diodes of S2 , S3 , and
S5 in Fig. 2. During the negative half cycle, Sc in Fig. 11(a)
represents S8 in Fig. 2, while Sd and Se in Fig. 11(a) represent
S3 , S5 , and S8 in Fig. 2. Meanwhile, Dc in Fig. 11(a) represents
the body diode of S9 in Fig. 2. Dd and De in Fig. 11(b) represent
the body diodes of S1 , S4 , and S7 in Fig. 2.
As shown in Fig. 5(a), the volt–second balance law can be
applied to both L1 within [t1 , t6 ] and L2 within [t0 , t5 ], yielding
⎧
⎪ Ts
⎪
⎪ V2 D2 Ts + (V2 − VC 3 )(1 − 2D2 ) =0
⎪
⎪ 2
⎨
1 (14)
⎪
⎪ N VC 3 Δ2 Ts + (−V1 ) − D2 − Dd Ts
⎪
⎪ 2
⎪
⎩
+(−V1 − N VC 3 )(D2 − Δ2 + Dd )Ts = 0.
Hence, the voltage gain in the CCM can be expressed as
V1 2N (2Δ2 − D2 − Dd )
= . (15)
V2 (1 − 2D2 )(1 − 2Δ2 )
In addition, the average current I1 at the high-voltage side can
be calculated by
 t5
1 2
I1 = i1 (t)dt =
Ts /2 t 0 Ts
 
1 N V C 3 + V1 N VC 3
(D2 − Δ2 + Dd )Ts + Δ2 Ts
2 L1 L1
1 1
− D2 − Dd Ts + (D2 − Δ2 + Dd )
2 2
N V C 3 + V1
× Ts (D2 − Δ2 + Dd )Ts . (16)
L1
By substituting (15) into (16), I1 is given by
Fig. 10. Voltage gain in the buck mode according to D1 under different turns
ratio N. N V2 [(D2 + Dd )(Δ2 + 0.5 − D2 − Dd ) − Δ2 2 ]
I1 = . (17)
fs L1 (1 − 2D2 )
When L1 operates in the critical conduction mode, Δ2 is
given by Δ2 = D2 . By substituting it into (15) and (17), average
current I1 crit at the high-voltage side in the critical conduction
mode is given by
V1 [(D2 + Dd )(1 − 2Dd ) − 2D2 2 ](1 − 2D2 )
I1 crit = . (18)
4fs L1 (D2 − Dd )
The CCM condition is determined by
I1 [(D2 + Dd )(1 − 2Dd ) − 2D2 2 ](1 − 2D2 )
I1 > I1 crit =
Kb o ost (D2 − Dd )
(19)
where Kb o ost = 4fs L1 /R1 and R1 is the equivalent load resis-
tor in the boost mode.
Then, the CCM condition is given by
Fig. 11. Equivalent circuits of the proposed converter in the boost mode.
(a) First stage structure. (b) Second stage structure. Kb o ost > Kb o ost crit (D2 ) (20)

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7265

Fig. 12. Boundary between CCM and DCM in the boost mode. Fig. 13. Dead-time effect on the voltage gain in the boost mode.

where
Kb o ost crit (D2 ) = f2 (D2 )
[(D2 + Dd )(1 − 2Dd ) − 2D2 2 ](1 − 2D2 )
= ,
(D2 − Dd )
and Kb o ost crit (D2 ) = (1 − 2D2 )2 when the dead time is
ignored.
By substituting Dd = 0.02 into (20), the boundary between
the CCM and DCM in the boost mode can be obtained in Fig. 12,
where Kb o ost > Kb o ost crit (D2 ) corresponds to the CCM oper-
ation, and Kb o ost < Kb o ost crit (D2 ) corresponds to the DCM
operation. Fig. 12 shows the different value of Kb o ost corre-
sponds different critical duty cycle, for example, when Kb o ost = Fig. 14. Voltage gain in the boost mode according to D2 under different turns
0.14, the critical duty cycle is 0.32, which means D2 ∈ [0, 0.32] ratio N.
corresponds to DCM operation, and D2 ∈ [0.32, 0.5] corre-
sponds to CCM operation.
By combining (15) with (17), the voltage gain in the CCM is By combining (23) and (24), the voltage gain in the DCM can
calculated by be calculated by

V1 N (1 − Kb o ost + 4Dd 2 − Dd )
MCCM b o ost = =  (21) V1 2N D2
V2 (1 − 2D2 ) Kb o ost + 4Dd 2 MDCM b o ost = = √ (25)
V2 (1 − 2D2 ) Kb o ost
where f2 −1 (Kb o ost ) < D2 < 0.5.
Similar to the CCM, when the converter operates in the DCM, where 0 < D2 < [f2 −1 (Kb o ost ) − Dd ].
as shown in Fig. 5(b), during [t0 , t5 ], the volt-second balance According to aforementioned analysis, the voltage gain when
law can be applied to L1 and L2 separately, so considering the dead time in the boost mode is shown in (21)
⎧ and (25). Then, when the dead time is ignored, the voltage gain
⎨ V2 D2 Ts = (VC 3 − V2 )(1 − 2D2 ) Ts
2 (22) can be simplified as (26) as shown at bottom of the next page.
⎩ By substituting Dd = 0.02, N = 3, and Kb o ost = 0.14 into
N VC 3 D2 Ts = V1 β2 Ts .
(21), (25), and (26), the voltage-gain curve in the boost mode
By simplifying (22), V1 can be expressed as can be obtained as shown in Fig. 13. Similar to the buck mode,
N D2 V2 the dead time does not affect the step-up ratio in the DCM and
V1 = . (23) has small effect on the step-up ratio in the CCM in the boost
(1 − 2D2 )β2
mode.
As seen from Fig. 5(b), the average current I1 at the high- By substituting Kb o ost = 0.14 and the prototype parameters
voltage side in the DCM can be calculated by from Table I into (21) and (25), the voltage-gain curve under
 t2 different turns ratio N and similar load condition in the boost
1 2 1 V1 V1 β2 2
I1 = i1 (t)dt = Ts β2 Ts β2 = . (24) mode can be obtained, as shown in Fig. 14, where a high step-up
Ts /2 t 0 Ts 2 L1 L1 fs ratio is achieved with a low transformer turns ratio.

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 7266 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019

C. Inductance and Capacitance Selections

The duty cycle for the critical conduction mode in the buck
mode can be determined by substituting Δ1 = D1 into (2),
yielding

D1 crit =

N V2 (4V1 +N V2 )+4V1 Dd (V1 Dd − V2 N ) − NV2 +2V1 Dd
.
4V1
(27)

Then, substituting the parameters from Table I into (27) re-

trieves D1 crit = 0.2.
According to the theoretical derivation and Fig. 10, the volt-
age gain of the buck mode has a maximum point at the critical
duty cycle, and the maximum value decreases with the load
being heavier. So, as long as the voltage gain under full-load
condition meets the requirements, the voltage gain under all
range load conditions can meet the requirement by adjusting the
duty cycle. As shown in Fig. 8 and (27), when D1 crit = 0.2,
the corresponding Kbuck is 3.6 and the corresponding voltage
gain is 48/600 = 0.08, so to ensure that the voltage gain achieve
0.08 under the full load (R2 = 1.15 Ω, Po = 2 kW), just satisfy
that the corresponding load resistor of the critical duty cycle is
less than or equal to 1.15, namely

16fs L1 buck
R2 crit = 2 ≤ 1.15 Ω. (28)
Kbuck N2

Then, the range of L1 can be calculated as L1 buck ≤ 140 μH
in the buck mode.
Similarly, by substituting Δ2 = D2 into (15), the critical duty
cycle in the boost mode is given by
 V1 [(D2 + Dd )(1 − 2Dd ) − 2D2 2 ](1 − 2D2 )
2V1 + N V2 − N V2 (4V1 + N V2 − 8V1 Dd )
D2 crit = .
4V1
(29)
Then, substituting the parameters from Table I into (29) re-
trieves D2 crit = 0.32.
According to the theoretical derivation and Fig. 13, the volt-
age gain of the boost mode can reach infinity when the duty
cycle is close to 0.5, so the voltage gain is always satisfying the
requirements whatever the value of inductance L1 is. In order
to achieve wide range ZVS operations, it is expected that the
converter operates in the CCM within wide range load, so to
ensure that the converter operates in the CCM under full load
(I1 = 42 A, Po = 2 kW), from (18), the required inductance L1
Fig. 15. Voltage gain under different load conditions (N = 3). (a) Buck mode.
(b) Boost mode.
in the boost mode can be calculated by
L1 b o ost >
4fs I1 (D2 − Dd )
= 108 μH. (30)
In the boost mode, the greater the value of L1 is, the wider
is the range of ZVS, so L1 is selected to be 140 μH. In this
case, the converter operates in the critical mode under the full
load condition in the buck mode. By substituting L1 = 140 μH
and the parameters from Table I into (8), (12), (21), and (25),
the voltage-gain curve under different load conditions can be
obtained, as shown in Fig. 15(a) and (b), where Kbuck = 3.6
(full load), Kbuck = 3.1 (70% load), and Kbuck = 2.5 (half load)
in the buck mode and Kb o ost = 0.19 (full load), Kb o ost = 0.14
(70% load), and Kb o ost = 0.09 (half load) in the boost mode.
As seen from Fig. 15(a), when the values of Kbuck or Kb o ost are

⎧ √
⎪
⎪ 2N D2 1− Kb o ost
⎪ MDCM
⎨ b o ost = √ 0 < D2 ≤
V1 (1 − 2D2 ) Kb o ost 2
= √ √ (26)
V2 ⎪
⎪ N (1 − Kb o ost ) 1 − Kb o ost
⎪
⎩ MCCM b o ost =√ < D2 < 0.5
Kb o ost (1 − 2D2 ) 2

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7267

different, the critical duty cycle and the experimental working that the capacitor voltage VC 3 is stable in both buck and boost
duty cycle also have different values. To achieve wide range modes. Consequently, from (34) and (35), capacitance C3 is
ZVS operations in the buck mode, the converter is designed to selected to be 2.04 mF. Likewise, capacitances C1 and C2 can
operate in the CCM under all load conditions except the full be determined using a similar approach.
load in the duty cycle range of [0.2, 0.5].
Given that the low-voltage side is usually connected to either D. ZVS Analysis in Buck Mode
the battery or ultracapacitor in distributed energy storage sys- In practice, switching devices require a dead time to prevent
tems, inductor L2 should guarantee CCM operation with a low the shoot-through phenomenon, and this time should be con-
current ripple. Hence, the selection of inductance L2 depends on sidered in the analysis of ZVS. Fig. 3(a) shows the switching
the current ripple of iL 2 . The current ripple coefficient of iL 2 is sequence diagram with dead time in the buck mode when L1
α, i.e., ΔiL 2 = αIL 2 , where ΔiL 2 is the peak-to-peak current operates in the CCM. Because L1 operates in the CCM, iL 1
ripple in the buck mode expressed as has not dropt to zero at t4 when S2 is turned OFF, as shown in
(0.5 − D1 )V2 Fig. 3(a). Then, L1 freewheels through S4 and the body diodes
ΔiL 2 buck = . (31) of S7 , S6 , and S1 . The freewheeling state lasts until the time
fs L2
point t6 when iL 1 drops to zero. In this case, the drain–source
Coefficient α is considered as 0.05. Then, by substituting
voltage of S1 will be zero after the junction capacitor of S1 is
Po = V2 I2 = V2 IL 2 and D1 crit = 0.2 into (31), the required
discharged completely. Then, when S1 , S5 , S7 , and S9 are turned
inductance, L2 , in the buck mode can be calculated by
ON at t5 , the ZVS operation of S1 can be achieved. The operat-
(0.5 − D1 )V2 (0.5 − 0.2) × 48 ing principles during [t9 , t10 ] and [t0 , t1 ] are similar to the ones
L2 buck > = = 113 μH. during [t4 , t5 ] and [t5 , t6 ], where the ZVS operation of S2 can
αfs I2 0.05 × 60 × 103 × 42
(32) be achieved.
More specifically, to achieve ZVS of S1 , the energy stored
Similarly, inductance L2 in the boost mode can be calculated in L1 must be able to fully charge and discharge the junc-
by tion capacitors of S2 and S1 when S2 is turned OFF. More-
D2 V2 0.32 × 48 over, the charging and discharging periods should be shorter
L2 b o ost > = = 121 μH. (33)
αfs I2 0.05 × 60 × 103 × 42 than the dead time. Therefore, the ZVS conditions for S1 are
expressed as
Therefore, inductance L2 is selected to be 130 μH.
On the other hand, the selection of the capacitance C3 is 1 1
L1 [iL 1 (t4 )]2 > (Coss1 + Coss2 )V12 (36)
mainly based on its voltage ripple. The equivalent circuits of the 2 2
proposed converter in the buck mode (see Fig. 7) indicate that C3 (Coss1 + Coss2 )V1
is the output capacitor of the first stage and the input capacitor Dd Ts > (37)
iL 1 (t4 )
of the second stage. The voltage ripple coefficient of VC 3 is γ,
i.e., ΔVC 3 = γVC 3 , the charge variation of C3 is ΔQC 3 , and where Coss1 and Coss2 are the junction capacitors of S1 and S2 ,
the average output current of C3 is IC 3 . The ampere–second respectively.
balance principle can be applied to C3 during the switching In the buck mode, iL 1 (t4 ) can be expressed as
cycle Ts , and hence, capacitance C3 in the buck mode can be V1
iL 1 (t4 ) = · (D1 − Δ1 + Dd )Ts . (38)
determined by L1
⎧
⎪ C3 buck > ΔQC 3 = IC 3 D1 Ts = IC 3 D1
⎪ By combining (3), I1 = V2 I2 /V1 , and (8), then the expression
⎪
⎪ of Δ1 , which includes the average load current I2 in the buck
⎪
⎪ ΔVC 3 γVC 3 γVC 3 fs
⎨ mode can be obtained by
V2 = 2D1 VC 3 (34)
⎪
⎪ N 2 (1 − 2D1 )2 V2
⎪
⎪ D1
⎪
⎪ V2 I2 Δ1 = + . (39)
⎩ IC 3 = . 32D1 fs L1 I2 2
VC 3
Then, by combining (36), (38), and (39), the ZVS load range
Similarly, the capacitance C3 in the boost mode can be deter- at S1 is expressed as
mined by
⎧ I2
I¯2 =
⎪ C3 b o ost > ΔQC 3 = IC 3 D2 Ts = IC 3 D2
⎪
⎪ I2 m ax
⎪
⎪ ΔVC 3 γVC 3 γVC 3 fs
⎪
⎨ N 2 (1 − 2D1 )2 V2
VC 3 IC 3 = V2 I2 (35) > 
⎪
⎪ 16D1 fs L1 (D1 +2Dd − 2 (Coss1 +Coss2 )L1 fs )I2 m ax
⎪
⎪
⎪
⎪ V2 (40)
⎩ VC 3 = .
1 − 2D2 where I2 m ax is the output current of the full load in the buck
Coefficient γ is considered as 0.01. In addition, because of mode and I¯2 is the percentage of the load current.
the limited ripple current capability of the electrolytic capacitor In addition, because the converter is designed to operate in
in the actual systems, enough margin should be left to ensure the CCM in the duty cycle range of [0.2, 0.5], by substituting

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 7268
Fig. 16. ZVS region of S1 , S2 , S5 , and S7 in the buck mode according to D1 .
V2 = R2 I2 into (8), the relationship between the load current
and duty cycle when the converter works normally in the CCM
can be obtained as
I2 N (1 − 2D1 )V1
I¯2 = = .
I2 m ax 4fs L1 I2 m ax
According to the analysis in the buck mode, the operating
principles of S2 , S5 , and S7 are similar to that of S1 , so S2 , S5 ,
and S7 can, thus, be achieved under the same load conditions.
By substituting the parameters from Table I into (40) and (41),
we assume Coss1 = Coss2 = 1 nF, then the ZVS boundary curve
that depicts the ZVS region and the minimum value of I2 with
respect to D1 is obtained in Fig. 16. As shown in Fig. 16, most of
the working points (the red spots) are located in the ZVS region,
which implies that ZVS of S1 , S2 , S5 , and S7 can be realized
from 0% to 98% load in the buck mode.
To achieve ZVS of S1 , the range of the dead time can be
determined by (37). Specifically, by substituting (38), (39), and
the parameters from Table I into (37), the value of Dd is selected
as 2%.
Furthermore, in the buck mode, when S3 , S5 , S7 , and S9 are
turned OFF at t2 , S4 does not immediately turn ON due to the dead
time. Therefore, during [t2 , t3 ], L1 freewheels through S2 and the
body diodes of S4 , S7 , and S6 . Likewise, the body diode of S4 is
forward biased and the drain–source voltage of S4 decreases to
zero after the junction capacitor of S4 is completely discharged.
Then, when S4 is turned ON at t3 , its ZVS is achieved. The
analogous case occurs in the negative half cycle, where ZVS
of S3 can be achieved. Therefore, ZVS of S4 and S3 can be
achieved in both DCM and CCM during the buck mode.
The ZVS conditions of S4 are expressed as
1 1
L1 [iL 1 (t2 )]2 > (Coss3 + Coss4 )V12
2 2
where Coss3 and Coss4 are the junction capacitors of S3 and S4 ,
respectively.
In the buck mode, iL 1 (t2 ) can be expressed as
V1
iL 1 (t2 ) = · Δ1 Ts .
L1
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019
Fig. 17. ZVS region of S4 and S3 (the shadow area) as a function of D1 and
Kb u ck .
By substituting (43) into (42), the ZVS conditions of S4 are
obtained by
(41)
1  D1 2D1
2 > (Coss3 + Coss4 )L1 fs − .
Kbuck 2 (1 − 2D1 )2
(44)
Given that S3 and S4 are structurally symmetrical, the same
ZVS conditions and load range apply to S3 . According to the the-
2
oretical analysis in the buck mode, 1/Kbuck = 0.07(full load),
2 2
1/Kbuck = 0.14(half load), and 1/Kbuck =∝(no load). By sub-
stituting the parameters from Table I into (44), the ZVS bound-
ary curve can be obtained as shown in Fig. 17, which depicts
the wide ZVS region. As seen from Fig. 17, ZVS of S4 and S3
can be achieved from no load to full load in the full duty cycle
range.
According to the aforementioned analysis, the converter is
designed to operate in the CCM for extending the scope of
ZVS operation in the buck mode. However, this results in the
additional circulating energy in the circuit. Fig. 18 depicts the
circulating energy during each switching cycle in the buck mode,
wherein the shaded area indicates the circulating energy.
As shown in Fig. 18, because L1 operates in the CCM, iL 1
has not decreased to zero at t0 . Therefore, during [t0 , t1 ], L1
still operates in the freewheeling state. As a result, the energy is
circulated back into the input side V1 in this stage. This state lasts
until iL 1 decreases to zero at t1 . During [t4 , t5 ], switches S1 , S5 ,
S7 , and S9 will not be turned ON due to the dead time. According
to the operating principle of the buck mode, energy circulating
also occurs in this stage. But the difference from the case of [t0 ,
(42) t1 ] is that capacitor C3 is simultaneously charged by i1 during
[t4 , t5 ], which means the output side receives energy within [t4 ,
t5 ]. The case of [t5 , t6 ] is analogous to that of [t0 , t1 ], while the
case of [t9 , t10 ] is analogous to that of [t4 , t5 ]. According to the
aforementioned analysis, the CCM operation is conducive to
achieve ZVS of switches, but on the other hand, this will result
in the additional circulating energy, which increases the peak
(43)
current in the circuit.
 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7269

Fig. 19 ZVS boundary of S3 and S4 in the boost mode according to L1

and fs .

Fig. 18. Energy circulating in the buck mode.

E. ZVS Analysis in Boost Mode

Fig. 5(a) shows the switching sequence in the boost mode
considering the dead time and L1 operating in the CCM. In the
CCM and boost mode, L1 freewheels through the body diodes
of S4 during [t6 , t9 ], and iL 1 does not drop to zero at t0 in the
next switching cycle, as shown in Fig. 5(a). In this case, ZVS
of S4 can be achieved when it is turned ON at t0 , because the
drain–source voltage of S4 is zero at that instant. The same case Fig. 20. ZVS region of S5 , S7 , and S9 (the shadow area) as a function of D2
occurs in the negative half cycle to achieve ZVS of S3 . and Kb o o st .
The ZVS conditions of S4 in the mode are expressed as
iL 1 (t0 ) < 0 (45)
Therefore, the junction capacitor of S5 is discharged by iL 1 , and
and iL 1 (t0 ) can be expressed as the drain–source voltage of S5 decreases to zero after its junction
capacitor is completely discharged. Consequently, ZVS of S5 is
N V C 3 + V1
iL 1 (t0 ) = − · (D2 − Δ2 )Ts . (46) achieved when it is turned ON at t3 . The analogous case occurs
L1
in the negative half cycle, where ZVS of S7 can be achieved.
By combining (17), (45), and (46), the ZVS load range of S4 The ZVS conditions of S5 are expressed as
is given by 1 1
2 L1 [iL 1 (t2 )]2 > (Coss5 + Coss6 )VC2 3 (48)
(1 − 2D2 ) V1 2 2
I1 > . (47)
4fs L1 where Coss5 and Coss6 are the junction capacitors of S5 and S6 ,
Given that S4 and S3 are similar operating principles, the respectively.
same ZVS conditions and load range apply to S3 . Because in In the boost mode, iL 1 (t2 ) can be expressed as
the boost mode, the heavier the load, the wider the range of N VC 3
iL 1 (t2 ) = · Δ2 Ts . (49)
ZVS, by substituting the parameters from Table I into (47), the L1
ZVS boundary curve can be obtained as shown in Fig. 19, which By combining (17), (48), and (49), the ZVS conditions of S5
depicts the ZVS region and the minimum value of I1 with respect is obtained by
to L1 and fs . In addition, when L1 = 140 μH and fs = 60 kHz, ⎧ 
the ZVS load range is I2 > 2.3 A, which implies that the ZVS ⎪
⎪ D2 < 2 (Coss3 + Coss4 )L1 fs
⎪
⎨
of S4 and S3 can be realized from 70% to full load in the boost √ √
mode. (1 − Kb o ost ) Kb o ost < 2D2 − 3D2 2 (50)
⎪
⎪
Furthermore, in the boost mode, when S4 and S6 are turned ⎪
⎩ 
OFF at t2 , S5 does not immediately turn ON due to the dead time. −[2 (Coss3 + Coss4 )L1 fs − D2 ]2

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 7270 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019

TABLE II
COMPARISON BETWEEN THE PROPOSED CONVERTER AND OTHER CONVERTERS

and because all the energy-circulating stages are accompanied by

 energy receiving in the output side, which speeds up the decline
D2 > 2 (Coss3 + Coss4 )L1 fs . (51) of the circulating current iL 1 .

Because the operating principles and ZVS implementation

process of S7 and S9 are similar as that of S5 , ZVS of S7 and
S9 can be achieved under the same load conditions. √ According
to
√ the theoretical analysis in the
√ boost mode, √ Kb o ost (1 −
Kb o ost ) = 0.24
√ (full load), K
√ b o ost (1 − Kb o ost ) = 0.2
(half load), and Kb o ost (1 − Kb o ost ) = 0 (no load). Then,
from (50) and (51), the wide ZVS region of S5 , S7 , and S9 can be
depicted in Fig. 20, which shows ZVS of S5 , S7 , and S9 can be
achieved from the no load to full load in nearly full duty cycle
range.
Similar to the case of the buck mode, energy circulating also
exists in the boost mode due to CCM operation. As shown in
Fig. 5, because L1 operates in the CCM, iL 1 has not reduced
to zero at t0 . In this case, L1 still operates in the freewheeling
state during [t0 , t1 ]. Then, the energy will be circulated back
into capacitor C3 in this stage. In the meantime, the output side
V1 receives energy within [t0 , t1 ]. The cases of [t4 –t5 ], [t5 –t6 ],
and [t9 –t10 ] are analogous to that of [t0 , t1 ]. Hence, the energy
circulating in the boost mode is less than that of the buck mode,
IV. COMPARATIVE STUDY
High-conversion-ratio bidirectional dc–dc converters are
mainly divided into two types according to circuit structure:
one-stage type and two-stage type. This section gives the com-
parisons between the proposed converter and the two types of
converters in voltage gain and other performance.
A. Comparison With One-Stage Converters
Table II lists the characteristics of the proposed and similar
converters related to the circuit structure and performance. To
reduce voltage spikes and stresses caused by the leakage induc-
tance of the transformer, the converter in [13] adopts an active
flyback and two passive capacitor–diode snubbers, thus decreas-
ing the current difference between the leakage inductance and
current-fed inductor, but the extra snubber networks increase
the complexity of the circuit and reduce efficiency. Moreover,
this converter presents a narrow range of ZVS. A bidirectional

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS
Fig. 21. Voltage gain of the proposed converter and those in [13] and [15] according to the duty cycle. (a) Buck mode. (b) Boost mode.
converter with efficiency and a power density optimization de-
sign is presented in [15]. However, the voltage conversion ratio
of the converter is not high enough and it is not suitable for
the applications with large voltage difference. In addition, the
high peak-to-peak current at the low-voltage side can adversely
affect the batteries in energy storage systems. A soft-switching
bidirectional LLC resonant topology that changes both the out-
put power and its flow direction by regulating the switching
frequency is proposed in [21]. However, in the boost mode, the
voltage across the magnetizing inductance is clamped by the in-
put voltage, thus disregarding the magnetizing inductance from
the resonant network and limiting the voltage gain.
To solve the problem in the traditional bidirectional LLC res-
onant converter, a symmetrical CLLC topology is proposed in
[22] to achieve bidirectional symmetrical operation. This con-
verter is well designed with high efficiency, and the performance
of the converter is verified on the 5-kW prototype. This converter
achieves bidirectional symmetrical operation, which solves the
problem in the traditional bidirectional LLC resonant converter.
Both primary and secondary sides have resonant inductors and
resonant capacitors, which means the ac equivalent circuits in
both forward and reverse modes are consistent. Moreover, the
bidirectional CLLC topology presented in [22] can be easily
extended for high power applications. This converter is a good
choice for the applications with a low-voltage conversion ratio.
However, under the applications with a high voltage conversion
ratio, the bidirectional CLLC converter requires a wide range
of operating frequency, which results in a large volume of mag-
netic components and reduces the power density. On the other
hand, the voltage conversion ratio can be raised by increasing
the transformer turns ratio, however, this may reduce the conver-
sion efficiency. Therefore, the converter in [22] is not suitable
for the applications with a high voltage conversion ratio.
Overall, compared with other converters, the proposed
converter has a high conversion ratio, low transformer turns
ratio, and simple control scheme. Fig. 21(a) and (b) shows the
voltage gain of the proposed converter and those in [13] and
[15] with the same circuit parameters (N = 3, fs = 60 kHz, L1
= 140 μH, Po = 2 kW), where the voltage conversion ratio of
the proposed converter is clearly higher than that of the others.
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7271
Fig. 22. DAB converter followed by the buck–boost converter.
B. Comparison With Two-Stage Converter
1) In Voltage Gain: Two-stage structures are usually used
in the high-conversion-ratio bidirectional dc–dc converters for
improving the voltage gain. One of the conventional topology for
this application is to use the dual active bridge (DAB) converter
followed by the buck–boost converter, as shown in Fig. 22,
where the first stage is the DAB converter and the second stage
is the bidirectional buck–boost converter. In Fig. 22, V1 and
V2 represent the high-voltage side and the low-voltage side,
respectively. N is the turns ratio of the transformer Tr . In order
to simplify the circuit analysis, we assume that capacitors C2 is
large enough, and its voltage VC 2 is constant. Then, VC 2 is the
output of the first stage circuit.
Fig. 23 shows the main waveforms of the DAB converter in
the buck mode, where D1 is the phase-shift duty cycle in the
buck mode. In addition, D2 is the phase-shift duty cycle in the
boost mode, and D3 is the duty cycle of the second stage (buck
converter or boost converter). In addition, Ts is the switching
cycle, so the switching frequency is fs = 1/Ts .
As shown in Fig. 23, according to the operating principle of
the DAB converter, the average output current during half one
switching cycle in the buck mode is obtained by
  Ts

2n D1 Ts 2
īo = io1 (t)dt + io2 (t)dt
Ts 0 D1 Ts
n(1 − 2D1 )D1 V1
= . (52)
fs L1
 7272 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019

Fig. 23. Main waveforms of the DAB converter in the buck mode.

We assume that Req is the equivalent load resistor of the DAB

converter in the buck mode. Then, by substituting īo = VC 2 /Req
into (52), the voltage gain of the first stage is obtained by
VC 2 n(1 − 2D1 )D1 Req
= . (53)
V1 fs L1
Moreover, the output power is given by Po = VC2 2 /Req =
V22 /R2 ,where R2 is the load resistor in the buck mode. Then,
the voltage gain of the whole converter in the buck mode is
expressed as
V2 V2 VC 2 n(1 − 2D1 )D1 R2
= × = . (54)
V1 VC 2 V1 D3 fs L1
Similarly, the voltage gain of the whole converter in the boost
mode is expressed as Fig. 24. Voltage gain of the proposed converter and DAB+buck–boost
V1 V1 VC 2 n(1 − 2D2 )D2 R1 converter. (a) Buck mode. (b) Boost mode.
= × = (55)
V2 VC 2 V2 (1 − D3 )fs L1
where R1 is the load resistor in the boost mode. are the reference values of the output voltage and the voltage
According to the aforementioned analysis, Fig. 24(a) and (b) across C2 , respectively. In this circuit, the output of the first
depicts the comparison of the voltage gain between the converter stage is the input source of the second stage. In order to obtain
in Fig. 22 and the proposed converter in this paper in buck and a stable output in the first stage, a voltage closed loop should
boost modes, respectively. The voltage gain curves are drawn be adopted. Then, a double closed-loop control scheme with
under the same circuit parameters (N = 3, fs = 60 kHz, L1 = an outer loop on the output voltage and an inner loop on the
140 μH, and Po = 2 kW). As shown in the figures, compared inductor current is adopted in the second stage to obtain the
with the converter in Fig. 22, the proposed converter performs stable output voltage V2 . Therefore, there are two independent
a higher conversion ratio within a relatively large range of duty control variables in the overall control system.
cycle in the buck mode, while the voltage gain of the proposed In Fig. 25(b), v2 s , vC 3 s , and iL 2 s represent the sampling
converter in the boost mode is higher than the converter in values of the output voltage V2 , capacitor voltage VC 3 , and in-
Fig. 22 within a certain range of duty cycle. ductor current iL 2 , respectively. V2 ref is the reference value of
2) In Control System: Fig. 25 shows the control systems the output voltage. As shown in Fig. 25(b), the proposed con-
of the converter in Fig. 22 and the proposed converter under verter operates under the double closed-loop control scheme
the buck mode. The case in the boost mode can be analyzed with capacitor-voltage feedforward, which can improve the dy-
similarly. namic performance and stabilize the capacitor voltage VC 3 . The
Because the converter in Fig. 22 is cascaded by two stage output of the voltage compensator is used as the reference for
structures, the control scheme also consists of two stages, as the current compensator. Then, the PWM signals that are mod-
shown in Fig. 25(a). In Fig. 25(a), v2 s , vC 2 s , and iL 2 s represent ulated by the output of the current compensator are generated.
the sampling values of the output voltage V2 , capacitor voltage In this case, there are only one control variable in the overall
VC 2 , and inductor current iL 2 , respectively. V2 ref and VC 2 ref control system.

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS
Fig. 25. Control systems of the two converters. (a) DAB converter followed
by the buck–boost converter. (b) Proposed converter.
According to the aforementioned analysis, compared with the
converter in Fig. 22, the proposed converter has the following
advantages.
1) The proposed converter can achieve the same or higher
voltage gain and functions through the one-stage inte-
grated cascade structure instead of two-stage independent
structure, which improves the integration and reliability
of the converter.
2) The proposed converter has simpler control system and
better dynamic performance because there is only one
stage (one control variable) in the control scheme. In con-
trast, there are two parts (two control variables) in the
control system of the converter in Fig. 22, which may
affect the dynamic performance of the converter because
the complex control causes delay in response.
3) In addition, the proposed topology used one less active
switch than the converter in Fig. 22.
V. EXPERIMENTAL RESULTS
To verify the validity and performance, we constructed a
2-kW prototype of the proposed converter. The proposed con-
verter can be applied in the distributed energy storage system,
battery energy storage system, and uninterruptible power source
systems. The low-side voltage is selected as 48 V because 48 V
is usually a typical value for batteries. Meanwhile, the dc bus
voltage is usually designed as 600 V for the 380 VAC three-
phase power system. So the high-side voltage is selected as
600 V in the experiment. The controller was implemented using
the TMS320F28335 DSP (Texas Instruments Inc., Dallas, TX,
USA). A photograph of the prototype is shown in Fig. 26, and
its parameters are listed in Table I.
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7273
Fig. 26. Prototype of the proposed converter.
Fig. 27 shows the experimental waveforms in the buck mode.
Fig. 27(a) and (b) depicts the waveforms for the output power
of 1 kW (i.e., half load) and 2 kW (i.e., full load), respectively.
According to the voltage gain curve in Fig. 15(a) and the theo-
retical analysis in Section III, the duty cycle range in the buck
mode is designed to the interval [0.2, 0.5] for extending the
scope of ZVS operations. In this case, the proposed converter
operates in the CCM at light load, and then, the operation state
trends to draw close gradually to the critical conduction mode
as the load being heavy. Hence, the duty cycle of switch S7
in Fig. 27(a) is larger than that of in Fig. 27(b). Furthermore,
inductor L1 in Fig. 27(a) (half load) operates in the CCM, while
L1 operates in the critical conduction mode in Fig. 27(b) (full
load). In Fig. 27(c), output current i2 is around 42 A with a small
current ripple, which avoids high peak currents and meets the
requirements for battery or ultracapacitor charging. Fig. 27(d)
shows capacitor voltage VC 3 with its ripple in the buck mode.
The peak-to-peak ripple of VC 3 is approximately 1.5 V (i.e.,
1.3% of VC 3 ), thus exhibiting a stable value with a low voltage
ripple.
Fig. 28 shows the ZVS waveforms of switches S1 and S3 ,
while Fig. 29 shows the ZVS waveforms of switches S2 and S4 .
According to the operating principle in the buck mode, when
the converter operates in the CCM, both S1 and S2 can achieve
ZVS. Because the proposed converter is designed to operate
in the CCM within most of load range, S1 and S2 can realize
ZVS operations within wide load range. Moreover, during each
switching frequency, inductor L1 freewheels through the body
diode of S3 before it is turned ON due to the dead time. Hence,
the drain–source voltage of S3 drops to zero and its ZVS is
achieved. The analogous case occurs for S4 . In this case, both
S3 and S4 can achieve ZVS regardless of the DCM or CCM.
Fig. 30 shows the experimental waveforms in the boost mode.
Fig. 30(a) and (b) depicts the experimental waveforms in the
boost mode for the output power of 1 kW (i.e., half load) and
2 kW (i.e., full load), respectively. The output voltage stabilizes
approximately at 600 V under both half and full loads, and the
energy is transferred from the low-voltage side to the dc bus. In
Fig. 30(a), L1 operates in the DCM, where the inductor current
iL 1 oscillates slightly at zero crossing. This is caused by the
resonance between the parasitic capacitance of the switches and
the circuit inductance after iL 1 drops to zero. The resonance
lasts until the next half switching cycle begins, where iL 1 will
 7274 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019

Fig. 27. Experimental waveforms in the buck mode. (a) vG S 3 , vG S 7 , iL 1 , V2 , at half load (P o = 1 kW). (b) vG S 3 , vG S 7 , iL 1 , V2 , at full load (P o = 2 kW).
(c) vG S 3 , vG S 7 , i2 , V2 , at full load (P o = 2 kW). (d) vG S 7 , V C 3 , ΔV C 3 , at full load (P o = 2 kW).

Fig. 28. ZVS waveforms of S1 and S3 in the buck mode. (a) vG S 1 , vD S 1 . (b) vG S 3 , vD S 3 .

gradually increase from zero. Fig. 30(b) confirms the L1 op-

eration in the CCM for the output power of 2 kW. Moreover,
Fig. 30(c) confirms a discharging current i2 with low current
ripple, thus being suitable to increase the lifetime and perfor-
mance of batteries or ultracapacitors in the practical application.
Fig. 30(d) depicts the experimental waveform of the capacitor
voltage VC 3 and its ripple in the boost mode. The peak-to-peak
ripple of VC 3 in the boost mode is below 1.5 V (i.e., 1% of VC 3 ).
Therefore, the voltage across C3 shows a good performance un-
der the fluctuating load.
Figs. 31 and 32 show the ZVS waveforms of S5 , S7 , and S9
in the boost mode. According to the operating principles in the
boost mode, L1 freewheels through the body diode of S5 before
Fig. 29. ZVS waveforms of S2 and S4 in the buck mode. it is turned ON each cycle due to the dead time, which makes its

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 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS 7275

Fig. 30. Experimental waveforms in the boost mode. (a) vG S 6 , vG S 7 , iL 1 , and V1 , at half load (P o = 1 kW). (b) vG S 6 , vG S 7 , iL 1 , and V1 , at full load
(P o = 2 kW). (c) vG S 6 , vG S 7 , i2 , and V1 , at full load (P o = 2 kW). (d) vG S 7 , V C 3 , and ΔV C 3 , at full load (P o = 2 kW).

Fig. 32. ZVS waveform of S9 in the boost mode.

Fig. 31. ZVS waveforms of S5 and S7 in the boost mode.

Therefore, ZVS of S3 and S4 can be achieved when L1 operates

drain–source voltage drop to zero. The analogous case occurs
for S7 . In addition, L2 freewheels through the body diode of S9
before it is turned ON each cycle. Therefore, S5 , S7 , and S9 can
achieve ZVS regardless of L1 operating in the DCM or CCM.
Fig. 33 shows the ZVS waveforms of S3 and S4 in the boost
mode. During each switching cycle, L1 freewheels through the
body diode of S3 in the positive half cycle. When L1 operates
in the CCM, iL 1 still flows through the body diode of S3 at the
instant when S3 is turned ON. The analogous case occurs for S4 .
in the CCM.
The aforementioned analysis and experiment results verify
that the output voltage of the converter in the boost mode is
stabilized at 600 V through the closed-loop control. The fluc-
tuation of the converter output voltage should be small under a
sudden load variation. Hence, an electronic load was connected
at the high-voltage side and set to constant current mode to ver-
ify the converter dynamic performance by step variations of the
load, whose results in the boost mode are shown in Fig. 34. In

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 7276
Fig. 33. ZVS waveforms of S3 and S4 in the boost mode.
Fig. 34. Transient waveforms under load variation in the boost mode. Load
variation (a) from 1 to 2 kW and (b) from 2 to 1 kW.
the figure, V1 is the dc-bus voltage, ΔV1 is the ripple of this
voltage, and i1 is the dc-bus current. When the load steps from
1 kW (i.e., half load) to 2 kW (i.e., full load), the undershoot
of the dc-bus voltage remains below 15 V (i.e., 2.5% of the bus
voltage) with recovery time of about 8 ms. Similarly, when the
load steps from 2 to 1 kW, the overshoot of the dc bus voltage
remains below 12 V with a recovery time of about 10 ms. Al-
though the recovery time is relatively long, both the undershoot
and the overshoot of the dc-bus voltage are below 3% of the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 8, AUGUST 2019
Fig. 35. Efficiencies of the proposed converter and other similar converters,
(a) in buck mode, and (b) in boost mode.
total voltage, thus verifying suitable dynamic characteristics of
the proposed converter.
Fig. 35 shows the efficiencies versus the output power of the
proposed converter and other similar converters in literatures in
both buck and boost modes. As shown in efficiencies curves,
the maximum efficiency of the proposed converter in the buck
mode reaches 95.4% at Po = 1.5 kW, and that in the boost
mode reaches 96.2% at Po = 1.75 kW. Compared with similar
converters in literatures, the efficiency of the proposed converter
in this paper is higher than that of in other existing converters
within most of the load range under the case of a high voltage
conversion ratio.
VI. CONCLUSION
In this paper, a high-conversion-ratio isolated bidirectional
dc–dc converter for the distributed energy storage system is
proposed. The converter is equivalent to a cascade structure of
an isolated converter and a non-isolated converter in both buck
and boost modes, thus achieving a high conversion ratio with a
low transformer turns ratio. The steady-state operations of the
converter are analyzed in detail. The theoretical derivation and
ZVS operations are discussed in detail. In addition, the converter
is suitable for battery or ultracapacitor energy storage systems
because the current at the low-voltage side is continuous with
 LU et al.: HIGH-CONVERSION-RATIO ISOLATED BIDIRECTIONAL DC–DC CONVERTER FOR DISTRIBUTED ENERGY STORAGE SYSTEMS
a small ripple. Moreover, the experimental results verify the
high performance of the proposed converter, with maximum
efficiency of buck and boost modes being 95.4% and 96.2%,
respectively.
However, it must be acknowledged that the additional energy
circulating is caused due to the wide range operation of the CCM
in the buck mode, which increases the peak current accordingly.
In the future studies, we propose to address this issue for further
enhancing the performance of the proposed converter.
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Junlong Lu (M’14) was born in Jiangxi, China, in
1987. He received the B.S. degree from the Harbin
University of Science and Technology, Harbin,
China, in 2011, and the M.S. degree from the Harbin
Institute of Technology Shenzhen Graduate School,
Shenzhen, China, in 2013, where he is currently
working toward the Ph.D. degree in power electron-
ics and power drives.
His current research interests include power elec-
tronics, charge equalization converter, soft-switching
technique, and renewable energy systems.
Yi Wang (M’09) was born in Heilongjiang, China,
in 1966. He received the B.S. degree from the Xi’an
Technological University, Xi’an, China, in 1988, and
the M.S. and Ph.D. degrees from the Harbin Insti-
tute of Technology, Harbin, China, in 1996 and 2002,
respectively.
Since 2009, he has been a Professor with the Shen-
zhen Graduate School, Harbin Institute of Technol-
ogy, Shenzhen, China. His research interests include
renewable energy systems, electric motor drive de-
sign, electric vehicle control techniques, and power
electronics converter.
Prof. Wang is the Reviewer for the Proceedings of the Chinese Society for
Electrical Engineering.
Xin Li was born in Hebei, China, in 1993. She re-
ceived the B.S. degree from Yanshan University, Qin-
huangdao, China, in 2015. She is currently work-
ing toward the M.S. degree in power electronics and
power drives with the Harbin Institute of Technology,
Shenzhen Graduate School, Shenzhen, China.
Her current research interests include power elec-
tronics, electromagnetic compatibility and modeling,
and control of power converters.
Changliang Du was born in Gansu, China, in 1989.
He received the B.S. degree from the Harbin Uni-
versity of Science and Technology, Harbin, China, in
2011. He has been working toward the M.S. degree
with Air Force Engineering University, Xi’an, China,
since 2016.
He is currently working with Xi’an XD High
Voltage Apparatus Co., Ltd., Xi’an. His main re-
search interests include high voltage and insulation
technology.