IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO.
2, FEBRUARY 2022
Bridgeless Push–Pull Resonant AC/DC
Converter Featuring Balanced Switching
Loss Distribution
Hwasoo Seok , Member, IEEE, Adrià Junyent-Ferré , Senior Member, IEEE,
Bong-Hwan Kwon , Member, IEEE, and Minsung Kim , Senior Member, IEEE
Abstract—This article proposes a bridgeless push–pull
resonant ac–dc converter featuring naturally balanced
switching loss at the primary side. The proposed converter
employs a current-fed push–pull structure and two rectifier
diodes at the primary side and a series resonance circuit at
the secondary side. By incorporating two rectifier diodes,
a diode bridge can be removed from the grid side of the
proposed converter, and thereby that the number of compo-
nents and primary-side conduction loss are reduced. One
major advantage of the proposed converter is balanced
loss distribution over one cycle of grid voltage, which
guarantees high power transfer capability with enhanced
overall switch utilization. The series-resonant circuit pro-
vides zero-current switching turn-OFF at the output diode,
thereby reducing the reverse recovery loss. The operating
principles and theoretical derivations of the converter are
discussed in detail. The validity and performance of the pro-
posed converter are verified using a prototype with 1.65 kW
output power.
Index Terms—Balanced loss distribution, enhanced
switch utilization, heat sink, junction temperature, rectifier
diodes, series-resonance.
I. INTRODUCTION
APID development of new technology such as artificial in-
R telligence, cloud computing, big data, and 5G are creating
Manuscript received September 28, 2020; revised December 28,
2020; accepted January 29, 2021. Date of publication February 23,
2021; date of current version October 27, 2021. This work was sup-
ported in part by the Technology development Program (S2968635)
funded by the Ministry of SMEs and Startups (MSS, Korea) and in part
by the National Research Foundation of Korea (NRF) grant funded by
the Korea government (MSIT) (No. 2021R1C1C1004276). (Correspond-
ing author: Minsung Kim.)
Hwasoo Seok is with the Department of Creative IT Engineering,
Pohang University of Science and Technology (POSTECH), Pohang
37673, Korea (e-mail: aeinla@postech.ac.kr).
Adrià Junyent-Ferré is with the Department of Electrical and
Electronic Engineering, South Kensington Campus, Imperial
College London, London SW7 2BT, U.K. (e-mail: adria.junyent-
ferre@imperial.ac.uk).
Bong-Hwan Kwon is with the Department of Electrical Engineering,
POSTECH, Pohang 37673, Korea (e-mail: bhkwon@postech.ac.kr).
Minsung Kim is with the Division of Electronics and Electrical En-
gineering, Dongguk University, Seoul 04620, South Korea (e-mail:
mkim@dgu.ac.kr).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2021.3059547.
Digital Object Identifier 10.1109/TIE.2021.3059547
0278-0046 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1443
a new golden era of data-driven productivity and dramatically
increasing the market demand for data centers. The global power
market of the data centers was valued at $7.25 billion in 2018
and is anticipated to grow at a compound annual growth rate
of 7.3% during 2018–2026 [1]. Due to continuously increasing
power demands of the computer-network server equipment in
data centers, the power converter manufacturers are expected
to supply ac/dc power converter with significantly higher effi-
ciency, higher power densities, and longer life time [2]–[4].
The bridgeless topology as employed in the ac/dc power
converter circuit is attractive because they are simple in structure,
easy to control, and can be built with a small number of power
components. The bridgeless flyback ac–dc converter was de-
veloped in [5], where the bridgeless structure was implemented
by replacing the main switch of the flyback converter with the
bidirectional switches and using a center tapped transformer.
But the leakage inductance of the transformer induces switching
loss at the primary-side switches and the output diode suffers
from serious reverse-recovery. To minimize the effect of leakage
inductance, the bidirectional resistor–capacitor–diode snubbers
are used at the primary side of the transformer. In [6], [7], Lee and
Do introduced the lossless snubber circuit for bridgeless flyback
ac–dc converter to clamp the voltage spike of the switches
and recycle the leakage inductor energy. On the other hand,
the bridgeless resonant flyback ac–dc converters have been
proposed in [8], [9]. They incorporate a series-resonant circuit
in the output voltage doubler on the secondary side of converter,
where the converters transfer energy with resonance during one
half of the switching period and linearly during the other half
of the switching period over the grid cycle. The resonant power
transfer reduces the switching loss and increases overall power
conversion efficiency. Recently, bridgeless SEPIC converters
have been presented in [10]–[12] that can withstand higher
power capacity than the bridgeless flyback converters. They can
also cover wide input voltage range with low input/output ripple
currents.
The aforementioned converters are designed with the single-
ended topologies such as flyback and SEPIC ones. Compared
to single-ended topologies, the double-ended topologies such
as push–pull and full-bridge converters can achieve high power
easily. These converters utilize the transformer more efficiently
and allows them to operate at significantly higher power levels.
Moreover, the size of the input inductor can be reduced by using
1444 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 2, FEBRUARY 2022

the doubled effective switching frequency [13], [14]. The single

power conversion current-fed push–pull ac–dc converter has
been developed in [15]. It operates in the boundary conduction
mode and features small number of power components and
simple structure. Constant on-time and frequency modulation
techniques have been developed for current-fed push–pull ac–dc
converter in [16]. Quasi-resonant valley switching is achieved
on the switch and zero-current switching (ZCS) is achieved at
the output diode, which improves overall power conversion effi-
ciency. But the variable switching frequency makes the passive
component design difficult. It can operate under the fixed fre-
quency, but it inevitably suffers from hard-switching problems
and significant switching loss at the several active switches. This
problem becomes more serious when the circuit operates with
higher frequency and higher power. This switching loss can
be reduced by employing a resonant scheme in the push-pull
resonant dc/dc converters as proposed in [17], [18]. Employing
a resonant tank and operating the converter in the resonant mode,
the switching loss can be reduced significantly. These push-pull
resonant converters are extended to ac/dc applications by adding
a diode bridge at the grid side [19]. It is designed with soft-
switching technique and small number of power components for
ac/dc applications. But these single power-conversion resonant
ac–dc converters use the diode bridge on the input side of the Fig. 1. Circuit diagrams of push–pull topology-based ac–dc convert-
rectifier, which increases conduction loss and manufacturing ers. Dr‘k’ (k = 1, . . ., 4): rectifier diodes; Li : input inductor; S‘k’ , DS‘k’ ,
CS‘k’ (k = 1, . . ., 4): equivalent model parameters of the primary-side
cost. By replacing unidirectional switches at the primary side switches; Cc : clamp capacitor; T : transformer with turns ratio n =
with two bidirectional switches, the diode rectifier is removed Ns /(Np1 + Np2 ) = Ns /Np , where Np1 and Np2 are the number of
and the bridgeless structure is implemented in [20]. The full- primary winding turns and Ns is the number of secondary winding
turns. Lm1 and Lm2 : magnetizing inductances of T ; Lr : leakage in-
bridge circuit at the secondary side and switch modulation ductance measured at the secondary side of T ; D1 and D2 : output
method are also adopted to naturally clamp the voltage across the diodes; Cr1 and Cr2 : resonant capacitors; Co : output capacitor; Ro :
primary-side switches with zero-current commutation, thereby load resistor; vg : grid voltage; vi : input voltage; Vo : output voltage; VCc :
voltage across Cc ; vLi : voltage across Li ; vp1 and vp2 : primary-side
eliminating the need to use active-clamp circuit or passive snub- voltages of T ; vs : secondary-side voltage of T ; vCr1 and vCr2 : voltages
bers. Bridgeless double current-fed dual-active-bridge ac–dc across Cr1 and Cr2 ; ig : grid current; iLi : current flowing through Li ;
converter is introduced in [21]. Because the duty cycle of the iDr‘k’ (k = 1, . . ., 4): current flowing through Dr‘k’ ; iS‘k’ (k = 1, . . ., 4):
current flowing through S‘k’ ; iD‘k’ (k = 1, 2): current flowing through D‘k’
switches is always 0.5 and phase-shift control is adopted, the (k = 1, 2); iLm1 and iLm2 : currents flowing through Lm1 and Lm2 ; iLr :
input ripple current is almost zero and bidirectional operation current flowing through Lr . (a) Unfolding-type push–pull resonant ac–dc
is easily implemented. However, the costs of converters in [20], converter in [19]. (b) Proposed bridgeless push–pull resonant ac–dc
converter.
[21] are expensive because they require many active switches
and gate driving units.
In this paper, we introduce a bridgeless push–pull resonant
presented and experimental tests are conducted using a prototype
ac–dc converter that is able to achieve balanced loss at the
1.65-kW ac–dc converter.
primary side switches. The proposed converter consists of a
The rest of the article is organized as follows. Section II
current-fed push–pull circuit and two rectifier diodes at the
describes mode analysis of the proposed converter. Section
primary side and a series resonance circuit at the secondary side.
III presents steady-state analysis of the proposed converter.
By employing two rectifier diodes, it removes the diode bridge,
Section IV gives control strategy of the proposed converter.
thereby reducing the number of components and primary-side
Section V describes design guidelines of the proposed converter.
conduction loss. One notable feature is that this topology and the
Section VI represents experimental results and discussions.
corresponding switching modulation method realize balanced
Section VII concludes this article.
loss distribution for the primary side switches over one cycle of
the grid voltage. This aspect achieves balanced junction tempera-
ture among the switching devices and guarantees high power ca- II. PRELIMINARY AND MODE ANALYSIS
pability with enhanced overall switch utilization. Furthermore, The push–pull converter in [19] [Fig. 1(a)] requires a diode
the series-resonant behavior achieves ZCS turn-OFF at the output bridge at the grid side, which increases the number of power
diode and reduces the reverse-recovery loss. Due to this circuit components. As shown in Table I, S1 and S2 always operate as
structure and simple control algorithm, high efficiency, high the main switches and S3 and S4 operate as the active clamp
power density, and inherent power factor correction capability switches. In this topology, the positive offset current −iLm1
are achieved. The design guidelines of the proposed converter are or iLm2 and the positive resonant current niLr flow through

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SEOK et al.: BRIDGELESS PUSH-PULL RESONANT AC/DC CONVERTER FEATURING BALANCED SWITCHING LOSS DISTRIBUTION 1445

TABLE I
SWITCHING STRATEGY OF THE CONVERTER IN [19] AND
PROPOSED CONVERTER

AC: active-clamp.

the main switches whereas the negative offset current iLm1 or

−iLm2 and the positive resonant current niLr flow through the
active clamp switches. Therefore, the switching and conduction
loss of the main switches are much higher than those of the active
clamp switches. As a result, the loss distribution among switches
is unbalanced in unfolding-type push–pull converter in [19].
Then, the high junction temperature degrades the electrical
characteristics of switches and increases the metal migration,
which causes accelerated aging and increased failure rate.
On the other hand, the proposed bridgeless push–pull con-
verter [Fig. 1(b)] removes one diode leg from the converter
in [19] and thereby reduces the number of required power
components. Moreover, all switches serve as the main switches
and the active-clamp switches alternatively, so the accumulated
loss at the main switches is distributed among the primary-side
four switches during the grid period; and the accumulated loss Fig. 2. Equivalent circuits of the proposed converter when D ≤ 0.5
is reduced to half at each switch. This reduced loss can simplify and vg ≥ 0. (a) Mode 1L . (b) Mode 2L . (c) Mode 3L .
the design of the heat sink or even may be able to remove it. At
the primary side of T , the proposed converter exploits a single and the next half of the switching period. Thus, we only analyze
diode leg Dr1 , Dr2 and a current-fed push–pull circuit using the operation when vg ≥ 0 and 0 ≤ t < Ts /2 in this article. The
four switches S1 , S2 , S3 , and S4 , input inductor Li , and clamp operation principle can be divided into two different operating
capacitor Cc . Pulsewidth modulation (PWM) signals for S1 and regions (D ≤ 0.5 and vg ≥ 0) and (D > 0.5 and vg ≥ 0), along
S2 are complementary to those for S3 and S4 , respectively. PWM with the equivalent circuits (Figs. 2 and 4) and the theoretical
signals for one switch leg (S1 and S3 ) and the other switch leg waveforms (Figs. 3 and 5).
(S2 and S4 ) are 180◦ out of phase. At the secondary side of T ,
it employs a voltage doubler D1 , D2 , Cr1 , Cr2 , and Co with an A. Operation Principle When D ≤ 0.5 and vg ≥ 0
LC series-resonant circuit Lr , Cr1 , and Cr2 . Mode 1L [tL L L
0 , t1 ]: At time t0 , S2 is turned OFF and S4 is turned
In order to analyze the proposed converter, several assump- ON with zero-voltage switching (ZVS). Denoting the voltages at
tions are made. node A, node B, and node C as vA , vB , and vC [Fig. 1(b)], it fol-
1) vg and ig are constant during one switching period Ts lows that vA = vB = vC = VCc during this interval. Since the
because Ts is much smaller than the grid period Tg . voltage across Li is vLi = vg − vC = vg − VCc , iLi decreases
2) CC and Co are large enough to regard VCc and Vo as linearly as
constants.
3) Np1 = Np2 = Np /2, Lm1 = Lm2 = Lm /2, and vp1 = (VCc − vg )
iLi (t) = iLi (tL
0)− (t − tL
0 ). (1)
vp2 = vp /2. Also, the ripple currents ΔILm1 and ΔILm2 at Lm1 Li
and Lm2 are equal to ΔILm . The currents flowing through Lm1 and Lm2 can be calculated
4) Li >> Lm for superposition principle. by applying the superposition principle to the primary-side
5) Cr1 = Cr2 = Cr /2. The average voltages VCr1 and VCr2 equivalent circuit in mode 1L . Then, iLm1 (t) and iLm2 (t) can
of vCr1 and vCr2 are equal to Vo /2. Also, the ripple voltages be written as
ΔVCr1 and ΔVCr2 at Cr1 and Cr2 are equal to ΔVCr .
iLi (t)
6) The dead time among the PWM signals is small enough to iLm1 (t) = − + ix (t) (2)
be neglected. 2
The converter operates symmetrically according to the polar- iLi (t)
iLm2 (t) = + ix (t) (3)
ity of vg . Also, it operates symmetrically during the first half 2

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1446 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 2, FEBRUARY 2022

Fig. 3. Theoretical waveforms of the proposed converter when D ≤

0.5 and vg ≥ 0 during the switching period Ts . vgs‘k’ is the gate-source
voltage of switch S‘k’ (k = 1, . . ., 4).
Fig. 4. Equivalent circuits of the proposed converter when D > 0.5
and vg ≥ 0. (a) Mode 1G . (b) Mode 2G . (c) Mode 3G .

where the first parts of the right-hand sides of (2) and (3) are
the currents calculated by assuming vp = 0 and the second part
ix (t) is the current calculated by assuming iLi (t) = 0. Note that
ix (t) is given by
vp
ix (t) = ix (tL
0)+ (t − tL L
0 ) = ix (t0 ). (4)
Lm
Mode 2L [tL L L
1 , t2 ]: At time t1 , S3 is turned OFF and S1 is
turned ON. The resonant circuit is formed with Lr , Cr1 , and
Cr2 , and iLr follows the sinusoidal waveform. The state equation
corresponding to this equivalent circuit can be written as
diLr (t)
Lr = −nVCc + Vo − vCr1 (t) (5)
dt
dvCr1 (t) dvCr2 (t)
iLr (t) = Cr1 − Cr2
dt dt
dvCr1 (t) d(Vo − vCr1 (t))
= Cr1 − Cr2
dt dt
dvCr1 (t)
= Cr (6)
dt
with the initial condition
iLr (tL
1) = 0 (7)
Vo
vCr1 (tL
1) = + ΔVCr . (8)
2 Fig. 5. Theoretical waveforms of the proposed converter when D >
0.5 and vg ≥ 0 during the switching period Ts .
Solving (5)–(8) results in

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SEOK et al.: BRIDGELESS PUSH-PULL RESONANT AC/DC CONVERTER FEATURING BALANCED SWITCHING LOSS DISTRIBUTION 1447

r1 dvCr1 (t)
iLr (t) = sin [−wr (t − tL
1 )] (9) iLr (t) = Cr (21)
Zr dt
vCr1 (t) = −nVCc + Vo + r1 cos [−wr (t − tL
1 )] (10) with the initial condition
where r1 = nVCc√ − Vo /2 + ΔVCr , the resonant angular fre- iLr (tG
1)=0 (22)
quency
 w r = 1/ Lr Cr , and the characteristic impedance Zr = Vo
Lr /Cr . vCr1 (tG
1)= + ΔVCr . (23)
2
During this interval, vA = 0, vB = VCc , and vC = VCc /2.
Since vLi = vg − vC = vg − VCc /2, iLi increases linearly as Solving (20)–(23) results in
r1
(vg − 0.5 · VCc ) iLr (t) = sin [−wr (t − tG
1 )] (24)
iLi (t) = iLi (tL
1)+ (t − tL
1 ). (11) Zr
Li
vCr1 (t) = −nVCc + Vo + r1 cos [−wr (t − tG
1 )]. (25)
By applying the superposition principle to the primary-side
equivalent circuit in mode 2L , iLm1 (t) and iLm2 (t) can be During this interval, vA = 0, vB = VCc , and vC = VCc /2. Since
written as vLi = vg − vC = vg − VCc /2, iLi decreases linearly as
iLi (t) (0.5 · VCc − vg )
iLm1 (t) = − + ix (t) (12) iLi (t) = iLi (tG
1)− (t − tG
1 ). (26)
2 Li
iLi (t) By applying superposition principle to the primary-side equiv-
iLm2 (t) = + ix (t) (13)
2 alent circuit in mode 2G , iLm1 (t) and iLm2 (t) can be written
where as
vp VCc iLi (t) VCc
ix (t) = ix (tL
1)+ (t − tL L
1 ) = ix (t1 ) − (t − tL
1 ). iLm1 (t) = − + ix (tG
1)− (t − tG
1) (27)
Lm Lm 2 Lm
(14) iLi (t) VCc
iLm2 (t) = + ix (tG
1)− (t − tG
1 ). (28)
Mode 3 L
[tL
2, tL
3 ]:
At time tL
the resonance stops; iLr
2,
2 Lm
becomes zero and vCr1 is at its minimum as follows: Mode 3G [tG G G
2 , t3 ]: At time t2 , the resonance stops; iLr
iLr (tL becomes zero and vCr1 is at its minimum as follows:
2) = 0 (15)
Vo iLr (tG
2)=0 (29)
vCr1 (tL
2) = − ΔVCr . (16)
2 Vo
vCr1 (tG
2)= − ΔVCr . (30)
Since D2 is turned OFF with zero current, it does not suffer from 2
reverse recovery problem. iLi (t), iLm1 (t), and iLm2 (t) can still Since D2 is turned OFF with zero current, it does not suffer from
be written as (11), (12), and (13). reverse recovery problem. iLi (t), iLm1 (t), and iLm2 (t) can still
be written as (26), (27), and (28).
B. Operation Principle When D > 0.5 and vg ≥ 0
Mode 1G [tG G G III. STEADY-STATE ANALYSIS
0 , t1 ]: At time t0 , S3 is turned OFF and S1
is turned ON. During this interval, vA = vB = vC = 0. Since A. Voltage Gain M
vLi = vg − vC = vg , iLi increases linearly as
From the operation principle when D ≤ 0.5 and vg ≥ 0, the
vg
iLi (t) = iLi (tG
0)+ (t − tG
0 ). (17) volt–second balance law of Li can be written as
Li
(VCc − vg )(0.5 − D) · Ts = (vg − 0.5VCc )D · Ts . (31)
By applying superposition principle to the primary-side equiv-
alent circuit in mode 1G , iLm1 (t) and iLm2 (t) can be written Rearranging (31) for VCc and vg = |vg | yield
as
|vg |
iLi (t) VCc = . (32)
iLm1 (t) = − + ix (tG 1−D
0) (18)
2
Applying the inductor voltage-second law to Lr during mode
iLi (t) 2L results in
iLm2 (t) = + ix (tG
0 ). (19)
2  tL2
1
Mode 2G [tG G G (−nVCc + vCr2 (τ ))dτ = 0. (33)
1 , t2 ]: At time t1 , S2 is turned OFF and S4 is Lr tL1
turned ON with ZVS. The resonant circuit is formed with Lr ,
Cr1 , and Cr2 , and iLr follows the sinusoidal waveform. The Since VCr2 is the average of vCr2 , it can be written as
corresponding state equation can be obtained as  tL2
v (τ )dτ
tL Cr2
diLr (t) VCr2 = 1 L . (34)
Lr = −nVCc + Vo − vCr1 (t) (20) t2 − tL1
dt

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1448 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 2, FEBRUARY 2022

error. It is then used to generate the peak Ig,pk of grid current

reference ig,ref . By multiplying sin(ωg t) to Ig,pk , ig,ref can be
obtained. The sign of error between ig,ref and ig is decided by
the polarity of vg and the error is supplied as an input to the inner
loop of the proposed controller. The inner loop current controller
makes ig track ig,ref as closely as possible. For the stability of the
dual-loop control algorithm, the cut-off frequency of the inner
loop should be higher than that of the outer loop [22], [23]. It
is not easy to obtain the transfer function of the resonant-type
converter due to large ac variation of the resonant inductor
current and the resonant capacitor voltage. Therefore, the PI
controller gains for the controllers are obtained heuristically.
To reduce the burden from the outer loop controller, a nominal
duty-cycle Dn is also used as a feedforward control input.
Fig. 6. Block diagrams of the controller and PWM signal generator for
the proposed converter. PLL is phase-locked-loop algorithm.
Rearranging (36) for D, D = Dn and replacing Vo with the
output voltage reference Vo,ref yield
2n|vg |
Solving (33) and (34) yields Dn = 1 − . (40)
Vo,ref
VCr2 = n · VCc . (35) To achieve symmetric operation of the bridgeless push–pull
From (32) and (35) and VCr2 = Vo /2, the voltage gain M can ac–dc converter, the roles of the switch pairs (S1 , S2 ) and (S3 ,
be obtained as S4 ) change according to the polarity of vg (Fig. 6). When vg ≥ 0,
Vo 2 S1 and S2 work as the main switches and are turned ON with
M= = (36) duty-cycle D. S3 and S4 are switched in a complementary way
n · |vg | 1−D
to S1 and S2 . When vg < 0, S1 and S2 work as the active-clamp
and the same result can also be obtained from the operation switches and are turned ON with duty-cycle 1 − D. S3 and S4
principle when D > 0.5 and vg ≥ 0. are also switched in a complementary way to S1 and S2 .

B. Ripple Current ΔILi at Li V. DESIGN GUIDELINE

When D ≤ 0.5 and vg ≥ 0, iLi decreases with a slope of A. Input Inductance Li
−(VCc − vg )/Li during mode 1L with time interval (0.5 − D) ·
Ts . Then, ΔILi is expressed as Li should be designed to satisfy the following inequality:
VCc − vg ΔILi ≤ ΔILi,max (41)
ΔILi = · (0.5 − D) · Ts when 0 ≤ D ≤ 0.5.
2Li
(37) where ΔILi,max is the maximum allowable ripple current of Li .
From (39) and (41), Li is given as
When D > 0.5 and vg ≥ 0, iLi increases with a slope of vg /Li ⎧
during mode 1G with time interval (D − 0.5) · Ts . Then, ΔILi ⎪
⎪ Vo · D · (0.5 − D)
⎨ if 0 ≤ D ≤ 0.5
4nfs ΔILi,max
is expressed as Li ≥ . (42)
⎪
⎪ Vo · (D − 0.5) · (1 − D)
vg ⎩ if 0.5 ≤ D < 1
ΔILi = · (D − 0.5) · Ts when 0.5 < D ≤ 1. (38) 4nfs ΔILi,max
2Li
From (32) and (36), (37) and (38) are rewritten as The value of right-hand side of (42) when D=0.25 or 0.75
⎧ becomes maximum. Then, Li satisfying (42) for all D can be
⎪ Vo · D · (0.5 − D)
⎨ if 0 ≤ D ≤ 0.5 written as
ΔILi = V · (D 4nfs Li (39)
− 0.5) · (1 − D) Vo
⎪
⎩ o Li ≥ . (43)
if 0.5 < D ≤ 1 64nfs ΔILi,max
4nfs Li
where fs = 1/Ts is the switching frequency. B. ZVS Condition and Magnetizing Inductance Lm
IV. CONTROL STRATEGY The current iAC,on of the active-clamp switch when it is turned
ON can be written as
For single power conversion with high power factor, the
ILi
proposed converter uses the dual-loop control algorithm, which iAC,on = iS4 (tL G
0 ) = iS4 (t1 ) = − − ΔILm . (44)
consists of the outer loop to regulate output voltage Vo and the 2
inner loop to control the grid current ig (Fig. 6). Proportional- The ZVS turn-ON for the active-clamp switches is always achiev-
integral (PI) controllers are used for both control loops. The outer able because the term on the right-side hand of (44) is always
loop of the proposed controller first computes the output voltage negative regardless of the value of Lm .

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SEOK et al.: BRIDGELESS PUSH-PULL RESONANT AC/DC CONVERTER FEATURING BALANCED SWITCHING LOSS DISTRIBUTION 1449

C. Voltage Rating of Components and Turns Ratio n of

the Transformer
The voltage rating of the rectifier diodes and primary-side
switches can be written as
Vo
VDr1 = VDr2 = VS1 = · · · = VS4 = VCc = (45)
2n
where VDr‘j’ is the voltage rating of Dr‘j’ (j = 1, 2) and VS‘k’
is the voltage rating of S‘k’ (k = 1, . . ., 4).
The voltage rating of output diodes can be written as
VD1 = VD2 = Vo (46)
where VD‘j’ is the voltage rating of D‘j’ (j = 1, 2).
Note that the voltage ratings of the primary-side switches and
output diodes in [19] are the same as those of the proposed
converter. The difference lies in that the voltage ratings of
rectifier diodes in [19] are the peak of the grid voltage Vg,pk .

D. ZCS Condition and Resonant Capacitance Cr . Fig. 7. ZCS region of D1 and D2 of the proposed converter with
respect to F and D.
To achieve the ZCS of D1 and D2 , the resonance should be
finished within DTs when 0 ≤ D ≤ 0.5 and (1 − D)Ts when
0.5 < D ≤ 1. Then, we have

Tr DTs if 0 ≤ D ≤ 0.5
< . (47)
2 (1 − D)Ts if 0.5 < D ≤ 1
Dividing by Ts /2 on both sides of (47) and representing it for
F = fs /fr yields

fs Tr 2D if 0 ≤ D ≤ 0.5
F = = < . (48)
fr Ts 2(1 − D) if 0.5 < D ≤ 1
Using fr = fs /F , ωr and Cr can be obtained as
1 2πfs
ωr = √ = 2πfr = (49)
Lr C r F
F2
Cr = . (50)
4π 2 L 2
r fs
Fig. 8. Experimental setup of the proposed converter system.

Using (48), ZCS region of D1 and D2 of the proposed

converter with respect to F and D can be obtained (Fig. 7).
If F is close to 0, ωr becomes high. Then, the peak value of the
resonant current becomes high; this high peak current increases
the conduction losses of the switches and diodes. If F is close
to 1, the ZCS region becomes extremely small and switching
losses of switches and diodes increase.
VI. EXPERIMENTAL RESULTS
To demonstrate the performance of the proposed converter,
experimental tests are conducted using a 1.65-kW prototype
converter (Fig. 8) with grid voltage vg = 220 Vrms ; output
voltage Vo = 360 V; and rated output power Po,max = 1.65 kW.
The values of parameters and specification of components of
the prototype are listed in Table II. The digital control al-
gorithm is implemented using a TMS320F28377D microcon-
troller. Analog-to-digital converter (ADC) modules are embed-
ded in the microcontroller and are used to convert the grid
voltage, the grid current, and the output voltage into the digital
values. The sampling frequency of ADC is set to be 25 MHz;
this frequency is fast enough to detect the zero crossing point
of the grid voltage varying at 60 Hz. resistor-capacitor analog
filter is used to filter out the noise in the grid voltage. Then,
notch-filter-based phase-locked-loop algorithm is used for the
synchronization of the grid voltage.
S1 operates as the main switch when vg is positive and as the
active-clamp switch when vg is negative. While vg is positive,
S1 is turned ON and OFF under hard switching condition and
the current stress of it is high (Fig. 9). S4 operates as the
active-clamp switch when vg is positive and as the main switch
when vg is negative. While vg is positive, S4 is turned ON and
OFF under soft switching condition and the current stress of it is
low (Fig. 10). ZCS turn-OFF for D1 is achieved (Fig. 11). ig is
synchronized with vg at the full load (Fig. 12). Total harmonic
distortion of ig is measured ≤3.9% at the full load. Because of
the single power conversion, the double-line frequency ripples
are observed at Cc , Cr1 , Cr2 , and Co (Fig. 13). These ripples are

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1450 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 2, FEBRUARY 2022

TABLE II
PARAMETERS AND COMPONENTS OF THE PROTOTYPE

Fig. 9. Experimental waveforms of vg , vgs1 , and iS1 at the full load.

Fig. 10. Experimental waveforms of vg , vgs4 , and iS4 at the full load.

Fig. 12. Experimental waveforms of vg , ig , and Vo at the full load.

not significant compared to dc offset values of the voltages and

soft-switching conditions are not affected by them. The power
conversion efficiency was measured by Yokogawa WT3000E
digital power meter. The maximum power conversion efficiency
is 97.2% and the efficiency at the full load is 96.9% under
vg =220 Vrms (Fig. 14). The efficiency of the proposed converter
is 0.6% higher than that of the converter in [19] at the full
load because the bridgeless structure is adopted in the proposed
converter. When the efficiency curves are obtained, the same
power components are used for the proposed converter and the
converter in [19]. Measured efficiency of the proposed converter
Fig. 11. Experimental waveforms of vg and iD1 at the full load. is ≥95.2% and its power factor is ≥0.987 over the entire grid
voltage range (Fig. 15). Loss breakdowns for the converter

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SEOK et al.: BRIDGELESS PUSH-PULL RESONANT AC/DC CONVERTER FEATURING BALANCED SWITCHING LOSS DISTRIBUTION
Fig. 13. Experimental waveforms of VCc , vCr1 , vCr2 , and Vo at the
full load; the waveforms are measured under ac coupling mode on an
oscilloscope to observe the ac ripple clearly.
Fig. 14. Measured power conversion efficiency curves of the converter
in [19] and the proposed converter.
Fig. 15. Measured power conversion efficiency and power factor of the
proposed converter with grid voltage variation at the full load.
in [19] and the proposed converter are obtained based on the
parameters in Table II and [24]–[26]. In the loss breakdown for
the converter in [19], the switching losses occurred at primary-
side bottom switches (S1 and S2 ) and top switches (S3 and S4 )
are unbalanced [Fig. 16(a)]. Also, the conduction losses at the
rectifier diodes take a high portion in total loss. However, in the
loss breakdown for the proposed converter, the switching losses
occurred at primary-side bottom switches and top switches are
well balanced [Fig. 16(b)]. In addition, the conduction losses at
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1451
Fig. 16. Loss breakdowns at the full load. (a) Unfolding-type push–
pull resonant ac–dc converter in [19]. (b) Proposed bridgeless push–pull
resonant ac–dc converter.
the rectifier diodes take a lower portion in total loss than that of
converter in [19]. Thermal images (Fig. 17) verify balanced loss
distribution at primary-side switches of the proposed converter;
this trait can simplify the task of heat management and increase
the reliability of the converter.
In Table III, the proposed converter and other current-fed
ac–dc converters are compared in terms of topology, shape of
transformer current, the number of components, power conver-
sion efficiency, etc. Unfolding-type current-fed push–pull ac–dc
converter [19] has the diode bridge at the grid side. This diode
bridge increases the number of power components and the loss of
the converter. Also, this unfolding structure unbalances the loss
distribution among the switches; the size of required heat sink
becomes much larger. Compared to [19], the proposed converter
requires only two diodes at the grid side, which reduces the
size and the development cost of the converter. Also, it features
the naturally balanced loss distribution over the primary-side
switches. This trait significantly reduces the size of the heat
sink attached to the switches. Bridgeless double current-fed
push–pull ac–dc converter in [20] requires full bridge circuit
at the secondary side. The secondary-side modulation naturally
clamps the voltage across the primary side switches. Bridgeless
double current-fed dual-active-bridge ac–dc converter in [21]
also needs full-bridge circuit at the secondary side to generate
the voltage across the secondary side of the transformer. The
1452
TABLE III
COMPARISON OF THE CURRENT-FED AC–DC CONVERTERS
Fig. 17. Thermal images of S1 , S2 , S3 , and S4 at the full load.
(a) Unfolding-type push–pull resonant ac–dc converter in [19]. (b) Pro-
posed bridgeless push–pull resonant ac–dc converter.
full-bridge circuits used in [20], [21] increase the number of
power components and require the corresponding gate driving
circuits, which significantly increases the development cost of
the converter. Moreover, the linear power transfer increases the
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 2, FEBRUARY 2022
switching loss, which reduces the power conversion efficiency.
Compared to [20], [21], the proposed converter uses a voltage
doubler with series-resonant circuit, which reduces the required
number of power components and reduces the switching loss.
As a result, the proposed converter achieves high efficiency and
can be developed with compact size.
VII. CONCLUSION
This article presented a bridgeless push–pull resonant ac–
dc converter, that achieved balanced loss distribution among
primary-side switches. The proposed converter is equipped with
a current-fed push–pull circuit with two rectifier diodes on the
primary side and a series-resonant circuit on the secondary
side. By using two rectifier diodes, the diode bridge can be
eliminated, which in turn reduces the number of components
and primary-side conduction loss. With this topology and the
corresponding switching modulation technique, we are able to
achieve balanced switching loss at the primary-side switches and
guarantee high power transfer capability with enhanced overall
switch utilization. Moreover, it accomplishes ZCS turn-OFF at
the output diode by using the series-resonant circuit. To confirm
the validity of the proposed converter, a 1.65-kW prototype
ac–dc converter was built and tested. The proposed converter
achieves a peak efficiency 97.2% and provides a power factor of
nearly unity.
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1453
Hwasoo Seok (Member, IEEE) was born in
Incheon, South Korea, in 1993. He received
the B.S. degree in electrical engineering and
Ph.D. degree in creative IT engineering from the
Pohang University of Science and Technology
(POSTECH), Pohang, South Korea, in 2015 and
2021, respectively.
His research interests include power conver-
sion system and control, fuel-cell converters,
and bidirectional converters.
Adrià Junyent-Ferré (Senior Member, IEEE)
obtained the industrial engineering degree from
the School of Industrial Engineers of Barcelona
(ETSEIB), Polytechnic University of Catalonia
(UPC), Barcelona, Spain, in 2007, and the Ph.D.
degree in electrical Engineering from the UPC,
in 2011.
He was a Researcher with CITCEA-UPC from
2006 to 2012 and a Lecturer with the Barcelona
College of Industrial Engineering (EUETIB),
Barcelona, Spain, in 2012. In 2013, he joined
the Department of Electrical and Electronic Engineering, Imperial Col-
lege London, London, U.K., where he is currently a Senior Lecturer.
His research interests include power electronic converter applications
for wind power generation, VSC-HVdc transmission, and low voltage
distribution. He investigates how converters can be made resilient to
network transients with minimal oversizing.
Bong-Hwan Kwon (Member, IEEE) was born
in Pohang, Korea, in 1958. He received the
B.S. degree from Kyungpook National Univer-
sity, Daegu, Korea, in 1982, and the M.S. and
Ph.D. degrees from the Korea Advanced Insti-
tute of Science and Technology, Seoul, Korea,
in 1984 and 1987, respectively, all in electrical
engineering.
Since 1987, he has been with the Depart-
ment of Electronic and Electrical Engineering,
Pohang University of Science and Technol-
ogy (POSTECH), Pohang, Korea, where he is currently a Professor.
His research interests include converters for renewable energy, high-
frequency converters, and switch-mode power supplies.
Minsung Kim (Senior Member, IEEE) was
born in Ulsan, Korea, in 1986. He received
the B.S. degree in electrical engineering from
the Pohang University of Science and Technol-
ogy (POSTECH), Pohang, Korea, in 2008, and
the Ph.D. degree in electrical engineering from
POSTECH, Pohang, in 2013.
Since 2013, he has been with Department
of Creative IT Engineering and Future IT Re-
search Laboratory, POSTECH, where he was a
Research Assistant Professor. In 2016, he was
a Research Scholar with Future Energy Electronics Center, Virginia
Tech, Blacksburg, VA, USA. In 2017 and 2018, he was an Academic
Visitor with Control and Power System Group, Imperial College London,
London, U.K. Since 2018, he has been with the Division of Electronics
and Electrical Engineering, Dongguk University, Seoul, Korea, where he
is currently an Assistant Professor. His research interests include highly
efficient power conversion circuit design, intelligent controller design
for industrial electronics, and renewable energy and energy storage
systems.