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LIANG AND LEE: HIGH-CONVERSION-RATIO HIGH-EFFICIENCY ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4493
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4494 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 7, JULY 2015
Fig. 4. Equivalent circuits of the isolated bidirectional dc–dc converter in the high-step-down stage over one switching period during CCM
operation. (a) Mode I. (b) Mode II. (c) Modes III and X. (d) Modes IV and IX. (e) Modes V and VIII. (f) Mode VI. (g) Mode VII.
is transferred to C3 and VLV . Switch current iS1 is equal 2) Mode II [t1 , t2 ]: During this interval, S3 is on, whereas
to iLk , and switch current iS3 is equal to iL1 + iL2 . The S1 , S2 , and S4 are off. The equivalent circuit is illustrated
voltage across S2 is equal to VHV , and that across S4 is in Fig. 4(b). The leakage current iLk flows into the
equal to (VHV − vC1 )/n. This operating mode ends when antiparallel diode of S2 to charge C2 and to clamp the
S1 is turned off at t = t1 . maximum voltage spike of S1 such that the energy stored
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LIANG AND LEE: HIGH-CONVERSION-RATIO HIGH-EFFICIENCY ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4495
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4496 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 7, JULY 2015
Fig. 6. Equivalent circuits of the isolated bidirectional converter in the high-step-up stage over one switching period during CCM operation.
(a) Mode I. (b) Modes II and VII. (c) Modes III and V. (d) Mode IV. (e) Mode VI. (f) Modes VIII and X. (g) Mode IX.
main switches are S3 and S4 ; S1 and S2 are the synchronous 1) Mode I [t0 , t1 ]: During this interval, S3 and S4 are on,
rectifiers. The operating mode of the proposed converter can whereas S1 and S2 are off. The equivalent circuit is
be divided into ten operating modes over one switching shown in Fig. 6(a). The energy stored in LLk is released
period. via the antiparallel diode of S1 to VHV and C1 . Therefore,
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LIANG AND LEE: HIGH-CONVERSION-RATIO HIGH-EFFICIENCY ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4497
the leakage energy can be recycled, and the voltage of S2 and that across S4 is equal to vL1 + VLV . Energy from
is clamped at VHV . VLV and C3 simultaneously provide VLV and C3 is stored by L2 . The energy stored in L1 is
energy to L1 and L2 . This operating mode ends when iLk released to N2 . C2 and winding N1 are linked in series to
is equal to zero at t = t1 . release energy to C1 and VHV . This operating mode ends
2) Mode II [t1 , t2 ]: During this interval, S3 and S4 are when S1 is turned on at t = t8 .
on, whereas S1 and S2 are off. The equivalent circuit 9) Mode IX [t8 , t9 ]: During this interval, S1 and S3 are
is shown in Fig. 6(b). VLV and C3 continue to provide on, whereas S2 and S4 are off. The equivalent circuit is
energy to L1 and L2 . iL1 and iL2 are equal to iLt /2. shown in Fig. 6(g). S1 achieves ZVS when it is turned
Thus, the conduction losses of L1 and L2 and S3 and S4 on with the synchronous rectifier. The voltage across S4
are reduced, and system efficiency improves. The voltage is VLV + vL1 , and that across S2 is VHV . L2 continues to
across T1 is equal to zero, and that across S1 and S2 is store energy from VLV and C3 . The energy stored in L1
equal to VHV /2. iL1 is equal to iS4 , and iL2 is equal to continues to be released to N2 . C2 and N1 are linked in
iS3 . C1 releases energy to VHV . This operating mode ends series to release energy to C1 and VHV . This operating
when S3 is turned off at t = t2 . mode ends when S1 is turned off at t = t9 .
3) Mode III [t2 , t3 ]: During this interval, S4 is on, whereas 10) Mode X [t9 , t10 ]: During this interval, S3 is on, whereas
S1 , S2 , and S3 are off. The equivalent circuit is shown in S1 , S2 , and S4 are off. The equivalent circuit is shown
Fig. 6(c). L1 stores energy from VLV and C1 . The antipar- in Fig. 6(f). S1 achieves ZVS when it is turned off. L2
allel diode of S2 conducts to achieve ZVS conduction. continues to store energy from VLV and C3 . C2 and N1
The energy stored in L2 is released to C2 through T1 . iS4 are linked in series to release energy to C1 and VHV . This
is equal to iL1 + iL2 . The voltage across S3 is equal to operating mode ends when S4 is turned on at t = t10 .
VLV + vL2 , that across the magnetizing inductance Lm
is equal to n(VLV + vL2 ), that across C2 is equal to
III. S TEADY-S TATE A NALYSIS OF THE
n(VLV + vL2 ), and that across S1 is equal to VHV . C1
P ROPOSED C ONVERTER
continues to release energy to VHV . This operating mode
ends when S2 is turned on at t = t3 . To simplify the steady-state condition analysis of the
4) Mode IV [t3 , t4 ]: During this interval, S2 and S4 are high-step-down and high-step-up stages in CCM, the leakage
on, whereas S1 and S3 are off. The equivalent circuit is inductance LLk of the transformer is neglected because the
shown in Fig. 6(d). S2 achieves ZVS when it is turned on magnetizing inductance Lm of the transformer is much larger
with the synchronous rectifier and thus improves system than its leakage inductance.
efficiency. L1 continues to store energy from VLV and C3 .
The energy stored in L2 continues to be released to C2
A. Step-Down Stage
through T1 . C1 continues to release energy to VHV . This
operating mode ends when S2 is turned off at t = t4 . The turned-on period DTs and the turned-off period (1 −
5) Mode V [t4 , t5 ]: During this interval, S4 is on, whereas D)Ts of S1 and S2 in one switching period are defined as shown
S1 , S2 , and S3 are off. S2 achieves ZVS when it is in Fig. 3.
turned off. The equivalent circuit is shown in Fig. 6(c). L1 When S1 and S2 are the switches used in the turned-on
continues to store energy from VLV and C3 . The energy period DTs , inductor voltages vL1 and vL2 and high-capacitor
stored in L2 continues to be released to C2 via T1 and the voltage vC2 are given by
antiparallel diode of S2 . C1 continues to release energy
VHV
to VHV . This operating mode ends when S3 is turned on vL1 = vL2 = − VLV (1)
at t = t5 . 2n
6) Mode VI [t5 , t6 ]: During this interval, S3 and S4 are VHV
vC2 = . (2)
on, whereas S1 and S2 are off. The equivalent circuit is 2
shown in Fig. 6(e). The energy stored in LLk is released When S1 and S2 are the switches not used in the turned-off
via the antiparallel diode of S2 to C2 . Therefore, the period (1 − D)Ts , vL1 and vL2 for this interval are
leakage energy can be recycled, and the voltage of S1 is
clamped at VHV . VLV and C3 provide energy to L1 and vL1 = vL2 − VLV . (3)
L2 . This operating mode ends when iLk is equal to zero
at t = t6 . The application of the principle of volt-second balance to L1
7) Mode VII [t6 , t7 ]: During this interval, S3 and S4 are and L2 yields
on, whereas S1 and S2 are off. The equivalent circuit
S
DT TS
is shown in Fig. 6(b). L1 and L2 simultaneously store VHV
energy from VLV and C3 . This operating mode ends when − VLV dt + −VLV dt = 0. (4)
2n
S4 is turned off at t = t7 . 0 DTS
8) Mode VIII [t7 , t8 ]: During this interval, S3 is on, whereas
Based on (4), the voltage gain is
S1 , S2 , and S4 are off. The equivalent circuit is shown in
Fig. 6(f). The antiparallel diode of S1 conducts to achieve VLV 1
MStep-down = = D. (5)
the ZVS condition. The voltage across S2 is equal to VHV , VHV 2n
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4498 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 7, JULY 2015
Fig. 7. Comparison of voltage gains of the isolated bidirectional full- Fig. 8. Boundary-conduction mode of the proposed isolated bidirec-
bridge converters [30], [31] and of the proposed bidirectional converter tional converter in the high-step-down stage with n = 1.5.
in the high-step-down stage in CCM operation.
B. Step-Up Stage
From (5), the voltage gain of the isolated bidirectional full- The turned-on period DTs and the turned-off period (1 −
bridge converters [30], [31] are compared with that of the D)Ts of S3 and S4 in one switching period are defined as shown
proposed bidirectional converter in the high-step-down stage in Fig. 5.
in CCM operation with a turns ratio of n = 1.5 (see Fig. 7). When S3 and S4 are the switches used in the turned-on
The voltage gain of the proposed converter is smaller than that period DTs , vL1 , vL2 , and vC2 are given by
of other converters [30], [31] when the duty cycle D is lower
than 0.5. vL1 = vL2 = −VLV (13)
The voltage stresses of all four switches are given by n
vC2 = VLV . (14)
1−D
vS1 = vS2 = VHV (6)
VHV When S4 (S3 ) is the switch not used in the turned-off period
vQ3 = vS4 = . (7) (1 − D)Ts and S3 (S4 ) is the switch used in the turned-on
2n
period DTs , vL1 , vL2 , N2 , and vLm for this interval are
When the proposed converter is operated in boundary-
conduction mode, the peak currents of iL1 and iL2 and the vL1 = vL2 = vN 2 − VLV (15)
average currents of IL1 , IL2 , and ILV can be expressed as vLm
vN 2 = (16)
n
VLV VLV
iL1 = iL2 = (1 − D)Ts = (1 − D)Ts (8) vLm = VHV − vC2 . (17)
L1 L2
VLV VLV ILV The application of the principle of volt-second balance to L1
IL1 = IL2 = (1 − D)Ts = (1 − D)Ts = (9) and L2 yields
2L1 2L2 2
VLV VLV VLV S
DT TS
ILV = = (1 − D)Ts = (1 − D)Ts . (10)
R L1 L2 −VLV dt + (vN 2 − VLV )dt = 0. (18)
0 DTS
The boundary normalized magnetizing-inductance time con-
stant in the high-step-down stage is defined as The solution of (18) explains the voltage gain as follows:
L1 L2 vN 2 1
τStep-down ≡ ≡ . (11) = . (19)
RTs RTs VLV 1−D
The solution of (11) yields the following expression of Equation (18) can be rewritten as
τStep-down :
S
DT TS
VHV − nV LV
τStep-down = 1 − D. (12) −VLV dt + 1−D
− VLV dt = 0. (20)
n
0 DTS
Fig. 8 illustrates the relationship of τStep-down and D at n =
1.5. If the normalized magnetizing-inductance time constant From (20), the high-step-up voltage gain can be explained as
τL is higher than τStep-down in the high-step-down stage, the
converter is operated in CCM; otherwise, it is operated in VHV 2n
MCCM = = . (21)
discontinuous-conduction mode (DCM). VLV 1−D
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LIANG AND LEE: HIGH-CONVERSION-RATIO HIGH-EFFICIENCY ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4499
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4500 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 7, JULY 2015
and S4 is increased by the antiparallel diode reverse-recovery synchronous rectifier efficiency is higher than the antiparallel
effect. Fig. 11(e) shows the waveforms of VLV , iN 2 , and iLt . diode efficiency and that the peak efficiency is 95.6% in the
The low-side voltage VLV is 24 V. The current frequency of iLt high-step-up stage. S1 −S4 will suffer from high current spikes,
is double the operating frequency of the system. iLt indicates which occur due to the recovery problem of the switches’
that the current is reduced. antiparallel diodes; thus, the switch-current waveforms pre-
The measured results in the high-step-up stage at full load sented in the experiments are slightly different with the oper-
Po = 200 W and VLV = 24 V are shown in Fig. 12. Fig. 12(a) ating waveforms in Figs. 3 and 5. The proposed bidirectional
and (b) shows the waveforms of vgs4 , vS4 , iS4 , iLt , vgs3 , vS3 , converter can be applied in the photovoltaic (PV) stand-alone
and iS3 . vgs4 and vgs3 are phase shifts of 180◦ with an overlap, system, energy storage system, and emergency power systems.
which ensure that the inductor energy can be delivered to N1 . The output voltage of a single PV module is 24–40 V. A dc–dc
The voltage increase in S3 and S4 is about 75 V. The current converter will be used to converter the PV output voltage to dc
frequency of iLt is 100 kHz. Fig. 12(c) shows the waveforms bus voltage and also achieving maximum power tracking. The
of iL1 and iL2 . The interleaved inductor currents iL1 and dc bus voltage is usually designed as 200 V for the 110 Vac
iL2 reduce the ripple current of iLt . Furthermore, C3 enables power system. This is why we selected the dc bus voltage
the selection of a low capacitor value. Fig. 12(d) shows the VHV of 200 V and the battery voltage VLV of 24 V. In this
waveforms of vgs2 , vS2 , and iS2 . vgs2 is a gate signal with a system, the battery needs to be charged or discharged depending
synchronous rectifier. vgs2 and vS2 indicate that S2 achieves on the PV power generation and the load requirement. The
ZVS when it is turned on and turned off. Fig. 12(e) shows low voltage (battery voltage) with 24 V can prove the high
the waveforms of VHV , vC2 , and iLk . VHV is 200 V, and the efficiency of the proposed converter. If the battery voltage is
capacitor voltage vC2 is about 100 V. selected at 36 V or higher voltage level, the system efficiency
Fig. 13 shows the measured conversion efficiency of the will be higher because the conduction losses will be reduced.
proposed converter in the high-step-down stage. The maximum The proposed converter is suitable for portable energy storage
efficiency is 96.3% with a synchronous rectifier. Compared with systems, emergency power systems, and micro dc grid systems.
the conversion efficiency, the efficiency with the synchronous The power-loss analysis of the proposed converter in step-down
rectifier is higher than that with the antiparallel diode. Thus, mode at 200 W is shown in Table I. The measured efficiency is
the synchronous rectifier can significantly improve efficiency. 96.3% and the calculated result is 98.1%, because the calculated
Fig. 14 shows the measured conversion efficiency of the pro- results ignore the reverse-recovery effect of the antiparallel
posed converter in the high-step-up stage. Fig. 14 shows that the diode, iron, and resistance of circuit traces.
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LIANG AND LEE: HIGH-CONVERSION-RATIO HIGH-EFFICIENCY ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4501
V. C ONCLUSION
In this paper, a high-efficiency and high-conversion-ratio
isolated bidirectional dc–dc converter with a low transformer
turns ratio has been presented. The size of the capacitor on
the voltage side can be decreased by using current-doubler
circuits with low current ripples. The synchronous-rectifier
circuit can achieve ZVS and improve system efficiency. The
operating principles, steady-state analysis, and experimental
results are discussed in detail. The efficiencies of the proposed
converter with synchronous rectifiers and antiparallel diodes are
compared in the experimental results. The full-load efficiency
Fig. 14. Experimental conversion efficiency of the proposed isolated in the step-down and step-up stages is near 96.3% and 95.6%,
bidirectional converter in the high-step-up stage. respectively.
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4502 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 7, JULY 2015
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LIANG AND LEE: HIGH-CONVERSION-RATIO HIGH-EFFICIENCY ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4503
Tsorng-Juu (Peter) Liang (M’93–SM’10) was Jian-Hsieng Lee was born in Miaoli, Taiwan,
born in Kaohsiung, Taiwan. He received the in 1980. He received the B.S. and M.S. de-
B.S. degree in electrophysics from National grees in electrical engineering from I-Shou Uni-
Chiao Tung University, Hsinchu, Taiwan, in versity, Kaohsiung, Taiwan, in 2003 and 2005,
1985 and the M.S. and Ph.D. degrees in respectively. He is currently working toward the
electrical engineering from the University of Ph.D. degree at National Cheng Kung Univer-
Missouri, Columbia, MO, USA, in 1990 and 1993, sity, Tainan, Taiwan.
respectively. His research interests include high-efficiency
He is currently the Director of the Green power converters, renewable energy conver-
Energy Electronics Research Center, National sion, electronic ballasts, and high-efficiency
Cheng Kung University, Tainan, Taiwan, where lighting systems.
he is also a Professor of electrical engineering. His research interests in-
clude high-efficiency power converters, high-efficiency lighting systems,
renewable energy conversion, and power IC design.
Dr. Liang is currently an Associate Editor of the IEEE T RANSACTIONS
ON P OWER E LECTRONICS and the IEEE T RANSACTIONS ON C IRCUITS
AND S YSTEMS —I: F UNDAMENTAL T HEORY AND A PPLICATIONS and the
Technical Committee Chair of the IEEE Circuits and Systems Society
Systems Power and Energy Circuits and Systems Technical Committee.
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