Electrical Power and Energy Systems 63 (2014) 446–454

Contents lists available at ScienceDirect

Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

A novel low-ripple interleaved buck–boost converter with high

efficiency and low oscillation for fuel-cell applications
Vahid Samavatian ⇑, Ahmad Radan
Electrical and Computer Engineering Faculty, K.N. Toosi University of Technology, Seyedkhandan Bridge, 1431714191 Tehran, Iran

a r t i c l e i n f o a b s t r a c t

Article history: Efficiency and dynamics of DC–DC converters play a major role in proficiency of renewable energy exploi-
Received 21 January 2014 tation. This paper presents a novel DC–DC interleaved buck–boost converter for fuel-cell applications.
Received in revised form 31 May 2014 While keeping the same step-up/step-down voltage transfer ratio, the proposed converter exhibits
Accepted 3 June 2014
non-pulsating I/O currents using interleave technique. A damping network is also added to improve
Available online 5 July 2014
the inner dynamics of converter. Besides the steady state operation based on state space averaging
(SSA) method, design considerations of converter are thoroughly elaborated. MATLAB/SIMULINK environ-
Keywords:
ment is used for simulating the steady state operation of proposed converter, and the experimental
Low-ripple I/O currents
Interleaved technique
results are presented, to verify the theoretical expected merits of the converter including high efficiency,
Non-inverting buck–boost converter non-pulsating I/O currents and low voltage oscillation. Prototype setup of 360 W and 36 V output voltage
High efficiency for a fuel cell with a brand of ‘‘FCgen 1020ACS’’ Ballard Power Systems, Inc was implemented. Experimen-
Fuel cell tal results including efficiency and time domain responses in the steady state show impressive benefits of
the proposed converter.
Ó 2014 Elsevier Ltd. All rights reserved.

Introduction
With ever-increasing use of DC–DC power converters in many
applications such as battery charging, fuel cell systems, power fac-
tor correction (PFC), hybrid electric vehicles, communication
power supply, maximum power point tracking (MPPT) of photo
voltaic system (PVs) and for other renewable sources’ maximum
energy extraction, a considerable number of studies have been
conducted over these kinds of converters. On the whole DC–DC
converters fall into three categories; buck, boost and buck–boost.
A buck–boost converter is required when the output voltage is
within the input voltage range [1–12].
Although there are many single-active-switch step-up/
step-down DC–DC converters such as Sepic, Cuk, and conventional
inverting buck–boost and flyback converters, the non-inverting
buck–boost one constructed by combining a boost and a buck circuit
in cascade with two independently controllable switches is a popu-
lar choice for such applications requiring bidirectional conversion
capability, high efficiency and low component stresses [2–4].
In addition to the above-mentioned step-up/step-down DC–DC
converters topologies, it is possible to combine a buck converter
⇑ Corresponding author. Tel.: +98 21 88462408; fax: +98 21 88462066.
E-mail addresses: vahidsamavatian@ee.kntu.ac.ir, vahidsamavatian_90@yahoo.
com (V. Samavatian), radan@kntu.ac.ir (A. Radan).
with a boost one in cascade leading to a single inductor high per-
formance buck–boost converter for low voltage applications [5–7].
Although other topologies, capable of working through high
voltage applications, are reported in [8,9], their controlling systems
are completely involved. Another topology is KY buck–boost con-
verter with improving controlling system via eliminating right-
half-plane (RHP) zero in continuous conduction mode (CCM)
[10],but it poses a major problem in four power switches which
results in increasing the cost of the device. In order to mitigate this
problem, new topology with two reduced active switches and
aforementioned advantage is reported in [11].
Most of the DC–DC converters mentioned earlier have the
drawback of pulsating input/output (I/O) currents resulting in a
high noise level and complicated controlling system as well as cur-
rent limitations. In many applications, especially in hybrid electric
vehicles, power factor correction and fuel cell, low-ripple current is
preferred [13–15]. For subsiding this problem the two-switch tri-
state buck–boost is proposed [16] and with regard to capability
of using large inductance in pseudo-continuous conduction mode
(PCCM) [17,18], lower-ripple I/O currents can be achieved. Another
possible solution for this problem is to use the interleaved tech-
nique. Using this technique further benefits like harmonic cancel-
lation, better efficiency, component stresses reduction, better
thermal performance, and high power density can be easily
obtained [13,15,19–22]. The concept of interleaving is not new

http://dx.doi.org/10.1016/j.ijepes.2014.06.020
0142-0615/Ó 2014 Elsevier Ltd. All rights reserved.
 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 447

Nomenclature

C1, C2, Cd input, interface and output capacitor S1–S4 Q1–Q4 Signal activations
D12 steady state duty cycle of boost stage Ts switching period
D34 steady state duty cycle of buck stage u unified controlling variable
d12(t) duty cycle of boost stage vC1, iC1 capacitor 1 voltage and current
d34(t) duty cycle of buck stage vC2, iC2 capacitor 2 voltage and current
iL1–iL4 inductor 1 through inductor 4 current vCd, iCd damping network capacitor voltage and current
M(u) converter voltage transfer ratio vg, ig input voltage and current
M(D12, D34) converter voltage transfer ratio vL1–vL4 inductor 1 through inductor 4 voltage
PRd power dissipation in damping network resistor vout, iout output voltage and current

and covers a wide area of applications [22]. In [13], the 16-phase buck and boost operating modes [15]. Proposes an interleaved non
interleaved bidirectional boost converter for hybrid energy storage inverting buck–boost converter with a low-output current ripple,
system (HESS) has solved I/O currents high ripple but this topology but in this topology counteracting the input voltage variation in
can just operate in the boost mode and it is not generalized in both wide range is not completely achieved. In [20], the double-switch

Fig. 1. Schematic circuit diagram of proposed converter.

Fig. 2. Operating modes of proposed converter: (a) boost mode; (b) buck mode.
448 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454
buck–boost converter is proposed which can reduce the induc-
tance, raise the conversion efficiency and have simple control
strategy, but component stresses have been remained high
through this topology. Another solution reported in the study of
this paper is to utilize a non-inverting interleaved buck–boost con-
verter with a damping network, placed between a two-phase inter-
leaved boost part and a two-phase interleaved buck part. In this
way the drawbacks of high I/O currents ripple, low converter effi-
ciency and voltage oscillation have been improved by using inter-
leaved technique, reducing component stresses as result of
combining boost stage and buck stage in cascade connection,
which has also less component stresses as a result, and employing
damping network respectively. Through increasing the number of
interleaved phase in boost and buck stages, the proposed converter
can be easily used as a modular converter which is suitable for
transferring high power density in applications such as HESS and
other individual storage systems requiring the capability of
increasing power density.
The purpose of this paper is to analyze a cascaded combination
of interleaved boost and buck converters connected through a
damping network. After discussing the steady state operation
and state equations of the proposed converter in the following sec-
tion based on the depicted key waveforms, circuit design and its
implementation as an application of fuel cell voltage regulation
have been presented in Section 3. Section 4 focuses on the experi-
mental results and the last section presents a conclusion for this
study.
Fig. 3. Key waveforms of proposed converter shown in Fig. 1 for Vout = 36 V, (a) currents and voltages in boost mode with Vg = 26 V (D24 = 1), and (b) currents and voltages in
buck mode with Vg = 43 V (D12 = 0).
Steady state operation and analysis of the proposed converter
The proposed converter is shown in Fig. 1. This converter can
operate both in boost and buck modes as shown in Fig. 2(a and
b). The boost mode is achieved when the switches 3 and 4 (Q3
and Q4) turn on permanently and switches 1 and 2 (Q1 and Q1)
operate in PWM. Similarly, in buck mode Q1 and Q2 turn off perma-
nently and Q3 and Q4 operate in PWM. The steady state operation
waveforms of this converter for both modes of boost and buck are
illustrated in Fig. 3(a) and (b) respectively. The last traces in these
two figures, namely S1 to S4, are allocated to logic activation signals
of Q3 to Q4. The PWM activation signals of Q1 and Q2 are similar to
each other with a delay of T3/2 for catering the interleaved pattern
and their duty cycles are considered as d12(t). The same is true for
Q3 and Q4 activation signals with considering d34(t) as their duty
cycles. The duty cycle of switches is adjusted in such a way that
output voltage is regulated around a desired value (here is 36 V)
in both operational modes. Including a capacitor and resistor con-
necting in series, damping network plays the role of decaying input
voltage oscillation in buck mode where Q1 and Q2 are permanently
off.
The two main methods used for obtaining the differential equa-
tions describing the dynamic behavior of interleaved converters
are state space averaging (SSA) methods [3] and signal flow graph
(SFG) [23]. In this paper state space averaging method is preferred
due to simplicity.
 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 449

Assuming the operation of continuous conduction mode (CCM)

and a switching frequency much higher than the converter natural
frequencies, state space averaging method [3] can be applied to
explore the converter model considering the small-ripple approxi-
mation and the principles of inductor volt-second balance and
capacitor charge balance.
For obtaining the modeling equations for both modes of opera-
tion simultaneously, the switching pattern of Fig. 4 is considered.
Based on this figure, each period introduces 6 time intervals and
6 corresponding circuit diagrams illustrated in Fig. 5. Time interval
numbering and portioning are listed in Table 1. As the intervals 2
and 5 have the same time portions and the same switching state,
with regard to Figs. 4 and 5, the converter can be analyzed only
in 5 states as follows:

Interval 1: [t0  t1], Fig. 5(a). In this time interval Q1, Q3 and Q4
are in conducting mode causing inductor 1to start saving
energy and concurrently inductor 2 to transfer its stored energy
to output load and both output inductors via D2. Considering
Fig. 5(a), the differential equations describing the capacitors’
voltages and inductors’ currents can be given as follows:
8
>
>
>
mL1 ðtÞ ¼ L1 didtL1 ¼ mg ðtÞ
>
>
>
> mL2 ðtÞ ¼ L2 didtL2 ¼ mg ðtÞ  mc1 ðtÞ
>
>
>
>
< mL3 ðtÞ ¼ L3 diL3 ¼ mL4 ðtÞ ¼ L4 diL4 ¼ mc1 ðtÞ  mout ðtÞ
dt dt
ð1Þ
>
>
> ic1 ðtÞ ¼ C 1 dmdtC1 ¼ iL2 ðtÞ  ðiL3 ðtÞ þ iL4 ðtÞÞ  mC1 ðtÞ
Rd
mCd ðtÞ
>
>
>
>
>
> ic2 ðtÞ ¼ C 2 dmdtC2 ¼ iL3ðtÞ þ iL4 ðtÞ  moutRðtÞ
>
>
: i ðtÞ ¼ C dmcd ¼ mC1 ðtÞmcd ðtÞ
cd d dt Rd

Interval 2 and 5: [t1  t2 and t4  t5], Fig. 5(b). In this time inter-
val Q3 and Q4 are in conducting mode while Q1 and Q2 turn off.
Therefore the energy stored in inductors 1 and 2 starts transfer-
ring to inductors 3 and 4 via D1 and D2. Similar to time interval
1 a set of differential equations can be found for describing of
the capacitors’ voltages and inductors’ currents in this time
interval based on Fig. 5(b). One can find these equations in
Appendix 1.
Interval 3: [t2  t3], Fig. 5(c). In this time interval Q3 is in con-
ducting mode while Q1, Q2 and Q4 are off. Energy transfer in this
interval is completely similar to previous interval except that
the energy stored in both input inductor is transferred to the
inductor 3 only.
Interval 4: [t3  t4], Fig. 5(d). In this time interval Q2, Q3 and Q4
are in conducting mode while Q1 is off. Energy transfer in this
interval is as also similar to that of interval 1 except that the
functions of inductor 1 and 2 replace each other.

Fig. 5. Operating states. (a) Circuit diagram in interval 1, (b) circuit diagram in
interval 2, 5, (c) circuit diagram in interval 3, (d) circuit diagram in interval 4, and
Fig. 4. Switching pattern of converters’ MOSFETs. (e) circuit diagram in interval 6.
450 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

Table 1 The new voltage conversion ratio can be written as follows.

Required expressions for evaluating parameters’ values.
minð1; uÞ
Interval number Time interval Time portion MðuÞ ¼ ð8Þ
1  maxð0; u  1Þ
1 t0  t1 d12(t)TS
2 t1  t2 (d34(t)  d12(t)  0.5)Ts Using above equation as voltage conversion ratio a smooth transi-
3 t2  t3 (1  d34(t))Ts
tion can be easily established. This conversion ratio is depicted in
4 t3  t4 d12(t)Ts
5 t4  t5 (d34  d12(t)  0.5)Ts Fig. 6.
6 t5  t6 (1  d34(t))Ts It is noted that small signal modeling and dynamic analysis
have been completely studied in [24]. Therefore readers would
be referred to [24] for more details in such analyses.
Interval 6: [t5  t6], Fig. 5(e). In this time interval Q4 is in con-
ducting mode while Q1, Q2 and Q3 are off. Therefore the energy Circuit design
stored in inductor 1 and 2 is transferred to the output capacitor
and inductor 4. In this section, some design considerations related to the selec-
tion of proposed converter’s components are addressed. As it men-
Using the differential equations in all time intervals and apply- tioned earlier, need of low ripple I/O currents is key issue of this
ing averaging technique [3] on these equations over one switching study and accordingly inductors are selected so that this require-
period, the following set of differential equations are given: ment has been met. The inductors values can be selected such that
a desired current ripple (DiL) is obtained. Similarly, desired voltage
8 D E D E
> L1 diL1dtðtÞ ¼ L2 diL2dtðtÞ ¼ V g ðtÞ  V C1 ðtÞð1  d12 ðtÞÞ ripple (DmC) can be achieved through selecting the capacitors val-
>
>
>
> D E
Ts
D E
Ts ues properly.
>
>
>
> L3 diL3dtðtÞ ¼ L4 diL4dtðtÞ ¼ V out ðtÞ þ V C1 ðtÞd34 ðtÞ The appropriate capacitors and inductors values are obtained
>
>
>
> D
Ts
E
Ts
using the equations describing behavior of inductors voltages
>
>
< C 1 dV C1 ðtÞÞ ¼  V C1 ðtÞV cd ðtÞ
þ ðiL1 ðtÞ þ iL2 ðtÞÞð1  d12 ðtÞÞ and capacitors currents in time intervals. Since the slope of the
dt Rd
Ts ð2Þ inductor current and capacitor voltage during one of each time
>
> ðiL3 ðtÞ þ iL4 ðtÞÞd34 ðtÞ
>
>
>
> D E interval is specified as well as the length of that time interval,
>
> dV out ðtÞ
>
> C2 dt
¼ ðiL3 ðtÞ þ iL4 ðtÞÞ  V Rout the ripple magnitude of both current and voltage can be evaluated.
>
> Ts
>
> D E Therefore expressions required for calculating the values of capac-
>
: C d dV cd ðtÞ
dt
¼ V C1 ðtÞV cd ðtÞ
Rd itors and inductors are given for both modes of operation are listed
TS
in Table 2.
where d12 and d34 are the duty ratio of the switches Q1, Q2 and Converter system with higher orders (more than two) can
respectively. For obtaining the steady state inductor currents and encounter some internal oscillations which have to be decayed
capacitor voltages, the steady state operating value of duty ratios, using some methods described in details in [25], but here a damp-
D12 and D34, and input voltage, Vg, will be used. By applying the ing network has been employed to mitigate this behavior. This
principles of inductor volt-second and capacitor charge balance, damping network consists of a capacitor and a resistor connecting
another set of expressions describing the steady state operation in series for subsiding input voltage large variations.
can be derived as follows: Although the design procedure of damping network parameters
8 D34 V out is thoroughly elaborated in [24], but here a brief explanation has
>
> Ig ¼ IL1 þ IL2 ¼ 1D R
>
>
12
been presented. Regarding control-to-output transfer function of
>
> I ¼ I þ I ¼ V out
>
< out L3 L4 R this proposed converter in buck mode operation (9), the constraint
Vg V out of damping network parameters calculation has been identified
V C1 ¼ 1D ¼ D ð3Þ
>
> 12 34
>
> V Cd ¼ 0 [24]. One can find numerator coefficients in Appendix 2.
>
>
>
: D34
V out ¼ D34 V CI ¼ 1D 12
Vg

The last expression of Eq. (3) yields the voltage transfer ratio of con-
verter M (D1, D2) as follows:
V out D34
MðD12 ; D34 Þ ¼ ¼ ð4Þ
Vg 1  D12
The converter operation in boost and buck modes is determined by
following conditions.
Boost mode : fD34 ¼ 1 and 0 < D12 < 1g
ð5Þ
Buck mode : fD12 ¼ 0 and 0 < D34 < 1g
Fig. 6. Voltage conversion ratio of the proposed buck–boost converter.
For making the transition between two modes smooth, the voltage
transfer ratio M (D12, D34) should be written in terms of only one
control variable [4,7]. For establishing a meaningful relation Table 2
Required expressions for evaluating parameters’ values.
between D12 and D34, the variable u is defined:
Assuming Parameter Expressions
L1, L2 V g ðV out V g Þ
DiL1or2 V out T s
u ¼ D12 þ D34 ð6Þ L3, L4 V out ðV out V g Þ
DiL3or4 V g Ts
C1 ðV out V g Þ
Boost mode : 1<u<2 DmC1 R T s
ð7Þ C2 V out ðV out V g Þ
Ts
Buck mode : 0<u<1 DmC2 RV g
 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 451

m^out ðsÞ ad34 3 d34 2 d34

3 s þ a2 s þ a1 s þ a0
d34
Gmod34 ðsÞ ¼ ¼ ð9Þ
^34 ðsÞ
d b5 s5 4 3 2
þ b4 s þ b3 s þ b2 s þ b1 s þ b0

For improving internal dynamic, all the zeros in control-to-output

transfer function should be Left-Half-Plane (LHP) zeros. Accord-
ingly, applying Routh-Hurwitz stability criterion to the transfer
function numerator, following set of equation would be derived.
8
>
>
> ad34
0 ¼ RVD34out ð1  D12 Þ2  0
>
>
>
> d34 V out 2 2
> a1 ¼ D34 ðC d RRd D12  2C d RRd D12  L12 D34 þ C d RRd Þ  0
>
<
ad34
2 ¼ L12DV34out ðC d R þ C 1 R  D234 C d Rd Þ  0 ð10Þ
>
>
>
> 2
>
> ad34 ¼ R Rd CdDC341 L12 V out  0
>
> 3
>
: d34 d34
a2 a1  ad34 0 a3
d34
0

Regarding aforementioned conditions and using nonlinear optimi-

zation (Nelder–Mead method), following damping network param-
eters constraints can be expressed.
( qffiffiffiffiffi
L12
Rd > 0:65 C1 ð11Þ
C d > 8C 1

The damping resistor dissipation power is evaluated by the follow-

ing expression assuming that mcd has some ripples in form of trian-
gular waveforms [4].

Dm2C1
PRd ¼ ð12Þ
12R

Experimental results
Fig. 7. Proposed converter prototype, (a) power stage, (b) controller stage, and (c)
The proposed converter is designed as a voltage regulation sys- two isolated voltage sources for driving buck MOSFETs.
tem so that its output voltage is adjusted around 36 V when its
input voltage range varies from 26 to 43 V. The maximum output
power is limited to 360 W corresponding to a load resistance equal
to 3.6 Ohm. Using (4) and above data, it can be easily seen that the
duty cycles are limited within the ranges: 0 < D12 < 0.2777 and
0.837 < D34 < 1. The switching frequency is around 50 kHz and
the inductors’ current ripple and capacitors’ voltage ripple are lim-
ited to 1 A and 0.1 V respectively.
The proposed converter has been designed as a fuel cell voltage
regulation. The application requirements have been met so that
output voltage of fuel cell, with brand of ‘‘FCgen 1020ACS’’Ballard
Power Systems, Inc, is fixed around 36 for charging a battery bank.
Fuel cell input voltage range varies from 26 to 43 V. Using (4), the
expressions listed in Table 2 and the ripples specified earlier, the
list of components and their value are given in Table 3. It is worth
nothing here that for inductors the cores of Xinlli CORE Corpora-
tion and the calculation method of [3] have been selected.
Fig. 7 shows the top view of prototype in three stages; (a) the
power stage including MOSFETs, IRF840b, and SHOTTKY diodes,
MBR20100 and other main components denoted on figure, (b)
the controller stage with a micro controller ATMEGA16L, MOSFET

Table 3
Components for proposed converter.

Components Descriptions Types/values

Q1, Q2,Q3, Q4 Power MOSFET IRF840b
D1, D2,D3, D4 SCHOTTKY diodes MBR20100
L1, L2 Inductor 80 lH, 5 A
L3, L4 Inductor 100 lH, 5 A
C1 Capacitor 47 lF, 100 V
C2 Capacitor 68 lF, 100 V
Cd Capacitor 470 lF, 100 V
Rd Resistor 1 ohm, 1 W
Fig. 8. Activation signals, (a) boost mode, and (b) buck mode.
452 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

Table 4
Current ripple comparison.

Buck–boost converter Maximum input current

ripple percentages (%)
Proposed converter 5.2
Proposed converter in [4] 20
Proposed converter in [11] 13
Proposed converter in [14] 30
Proposed converter in [16] 30

to present the experimental waveform of steady state operation

Fig. 9. Input current and input inductors’ current ripple in boost mode, (a)
Vg = 26 V, and (b) Vg = 30 V.
in both modes by applying input voltage equal to 26 V and 30 V
in boost mode and 40 V and 43 V in buck mode under the full load
conditions.
The activation signals are depicted in Fig. 8(a) for boost mode
where D34 = 1 and D12 are operating in PWM and in Fig. 8(b) for
buck mode where D12 = 0 and D34 are operating in PWM.As it can
be seen from this figure, having a delay of Ts/2 guarantees the ben-
efits of interleaving technique.
As it mentioned earlier, steady state experimental results have
been illustrated in four various input voltages to verify the steady
state operation of proposed converter in the wide range of input
voltage. Figs. 9 and 10 illustrate the overall input current and
inductor currents ripples in boost and buck operation mode
respectively. As depicted from these figures, the maximum ripple
of inductor currents is limited to 1.05 A and it is about 0.52 A
(%5.2) for input currents. These figures show that the ripples of
both inductors are minimally different because all the inductors
are handmade. These values are not only satisfactorily met the
requirements but also, in comparison with recent studies
[4,11,14,16] which their input current ripple percentages are listed
in Table 4, proves a better steady state performance for the pro-
posed converter.

Fig. 10. Output current and output inductors’ current ripple in buck mode (a)
Vg = 43 V, and (b) Vg = 40 V.

driver ICs, ICL7667 and two fast optocouplers, 6N137 and (c) the
isolated voltage supplies. This section is organized in such a way Fig. 11. Capacitors voltage ripples in boost mode, (a) Vg = 26 V, and (b) Vg = 30 V.
 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 453

Fig. 12. Capacitors voltage ripples in buck mode, (a) Vg = 43 V, and (b) Vg = 40 V.
Fig. 13. Energy conversion efficiency for Vo = 36 V as: (a) function of the output
current for different input voltage levels; (b) function of the input voltage for
different output current levels.
The ripples of input, interface link and output voltages in both
operation modes are depicted in Figs. 11 and 12. Maximum ripple of several discontinuous conduction modes at light loads and
of input and capacitor voltages are restricted to 1 V, 0.2 V, 0.05 V RHP zero which are being worked to be solved and reported in near
(%0.14) respectively. future.
The energy conversion efficiency is the matter of any conver-
sion system. Efficiency traces are shown as a function of the output Appendix A
current iR for different input voltage levels in Fig. 13(a) and as a
function of the input voltage with different output current levels This appendix is provided to derive differential equations
in Fig. 13(b). With regard to Fig. 13, the maximum efficiency can describing the capacitors’ voltages and inductors’ currents in time
be obtained in both boost and buck modes and is not in the bound- intervals based on Fig. 5. These equations corresponding to first
ary of operating mode change because of mode transition. Maxi- interval have been explored in Section 2. However the other differ-
mum efficiency as function of the input voltage with different ential equations are expressed here.
output current levels occurs in all current levels when input volt- Interval 2 and 5: [t1  t2 and t4  t5], Fig. 5(b),
age in near to 36 V, because buck switches are permanently on in 8 diL diL
>
> mL1 ðtÞ ¼ L1 dt ¼ mL2 ðtÞ ¼ L2 dt ¼ mg ðtÞ  mC1 ðtÞ
1 2
this situation and there is only conduction power loss. >
>
>
>
> di L di L
> mL3 ðtÞ ¼ L3 dt3 ¼ mL4 ðtÞ ¼ L4 dt4 ¼ mC 1 ðtÞ ¼ mout ðtÞ
>
<
Conclusions dmC
> iC 1 ðtÞ ¼ C 1 dt1 ¼ ðiL1 ðtÞ þ iL2 ðtÞÞ  ðiL3 ðtÞ þ iL4 ðtÞÞ  mC1 ðtÞ
Rd
mcd ðtÞ
>
>
>
A new non-inverting buck–boost DC–DC converter is obtained >
>
> iC2 ðtÞ ¼ C 2 dmdtC2 ¼ iL3 ðtÞ þ iL4 ðtÞ  moutRðtÞ
>
>
through a cascade connection of an interleaved boost and an inter- : mcd
icd ðtÞ ¼ cd ddt ¼ mC1 ðtÞmCd ðtÞ
Rd
leaved buck stage and assisted by a damping network at the inter-
mediate capacitor to decay voltage oscillations and to improve Interval 3: [t2  t3 ], Fig. 5(c), ðA1Þ
converter inner dynamic. Simulation and experimental results of 8 di di
a prototype converter validate the predicted low-ripple I/O cur-
>
>
>
mL1 ðtÞ ¼ L1 dtL1 ¼ mL2 ðtÞ ¼ L2 dtL2 ¼ mg ðtÞ  mC1 ðtÞ
>
>
rents due to application of interleaved technique. Efficiency studies >
> diL
> mL3 ðtÞ ¼ L3 dt ¼ mC1 ðtÞ  mout ðtÞ
3
>
show that maximum efficiency can be achieved for buck mode, >
>
>
< m ðtÞ ¼ L diL4 ¼ m ðtÞ
where the switches boost stage are always OFF, and for boost L4 4 dt out
ðA2Þ
mode, where the buck stage switches are continuously ON. >
> iC 1 ðtÞ ¼ C 1 dmC
1
¼ ðiL1 ðtÞ þ iL2 ðtÞÞ  ðiL3 ðtÞ  mC1 ðtÞ mcd ðtÞ
>
> dt Rd
The capability of low-ripple I/O currents creates possibilities for >
>
>
>
many applications like battery, super-capacitor, PV panel, or fuel >
> iC2 ðtÞ ¼ C 2 dmdtC2 ¼ iL3 ðtÞ þ iL4 ðtÞ  moutRðtÞ
>
>
: mcd
cell energy exploitation. There are still two remaining small prob- icd ðtÞ ¼ cd ddt ¼ mC1 ðtÞ
R
mCd ðtÞ
d
lems associated with the proposed converter, namely appearance
454 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

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> m ðtÞ ¼ L1 dtL1 ¼ mg ðtÞ  mc1 ðtÞ
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>
> i ðtÞ ¼ C
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>
>
>
mL1 ðtÞ ¼ L1 dtL1 ¼ mL2 ðtÞ ¼ L2 diLdt2 ¼ mg ðtÞ  mC1 ðtÞ modulation scheme for four-switch buck–boost converter. IEEE Trans Power
>
> Electron 2009;24(2):499–509.
>
> diL
> mL3 ðtÞ ¼ L3 dt ¼ mout ðtÞ
3
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>
>
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>
> iC 1 ðtÞ ¼ C 1 dmC
1
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>
> dt Rd [12] Hajizadeh A, Golkar MA, Feliachi A. Voltage control and active power
>
>
>
> management of hybrid fuel-cell/energy-storage power conversion system
>
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>
>
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icd ðtÞ ¼ cd ddt ¼ mC1 ðtÞ
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mCd ðtÞ
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> b0 ¼ RðD12  1Þ
>
> [16] Mingzhi He, Fei Zhang, Jianping Xu, Ping Yang, Tiesheng Yan. High-efficiency
>
> 2 2 2
> b1 ¼ ðL34 þ L12 D34 þ L34 D12  2D12 L34 þ C d RRd  2C d RRd D12 þ C d RRd D12 Þ
>
> two-switch tri-state buck–boost power factor correction converter with fast
>
> 2 dynamic response and low-inductor current ripple. IET Power Electron
>
> b2 ¼ ðC 1 L12 R þ C 2 L34 R þ C d RL12  2C 2 L34 RD12 þ C d Rd L34  2C d Rd L34 D12
>
> 2013;6(8):1544–54.
<
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>
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>
>
>
> [18] Viswanathan K, Oruganti R, Srinivasan D. Dual-mode control of tri-state boost
>
> þC d C 2 L34 RRd Þ
>
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>
> 2005;20(4):790–7.
> b4 ¼ L12 L34 ðC 1 C 2 R þ C d C 2 R þ C 1 C d R þ C 1 C d Rd Þ
>
>
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>
>
> [21] Lee Po-Wa, Lee Y–S, Cheng DK-W, Liu Xiu-Cheng. Steady-state analysis of an
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>
>
> ad34
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