A 50 Hz SC Notch Filter for IoT Applications
Hugo Serra, João Pedro Oliveira, and Nuno Paulino
Centre for Technologies and Systems (CTS) - UNINOVA
Dept. of Electrical Engineering (DEE), Universidade Nova de Lisboa (UNL)
2829-516 Caparica, Portugal
E-mail: hugoaaserra@gmail.com
Abstract—This paper presents a SC 50 Hz notch filter for an
analog to digital acquisition channel in an IoT water management
sensor node. The notch filter is used to attenuate the unwanted
50 Hz interference, allowing to reduce the required effective
resolution of the ADC, which is a ΣΔ modulator with a sampling
frequency of 2 MHz. Due to the large ratio between the sampling
frequency and the pole frequency, which increases the capacitor
values dispersion, charge division branches are used to allow the
delivery of a small charge using a larger capacitor, reducing the
capacitor spread. The factor by which the value of the capacitors
can be increased is controlled by the number of set/reset cycles
that are used in the charge division branches. The maximum
number of cycles is dependent on the time constants of each
node and the gain value of the amplifiers. The notch filter has a
total power dissipation below 300 μW and electrical simulations
show an attenuation of approximately 30 dB in the unwanted
50 Hz signal.
I. I NTRODUCTION
Water management requires determining the quality of the
water at different locations in the water distribution network.
At each location, a Internet of Things (IoT) node is connected
to different sensors, such as temperature, pressure, impedance,
etc. The information from each sensor is typically a voltage
that must be digitized, in order to be processed and uploaded
into a high-level processing center. Most of these sensors
only provide single-ended signals or at best pseudo-differential
signals, most of these signals vary very slowly and can be
considered DC signals. The exception is the measurement
of the water impedance that requires digitizing signals with
frequencies in the kHz range [1]. This requirement results in
an ADC with a signal bandwidth of around 10 kHz.
A typical digitizing channel is comprised of an anti-aliasing
filter (AAF), a gain block and an ADC. When deciding on the
type of ADC and its required performance, it is important to
take into consideration the overall performance of the channel.
In this case, it is important to consider that the sensors are
connected to the IoT node (where the channel is located)
through long cables that can pick up unwanted signals. This
means that the performance of the AAF can be critical for the
system. In order to facilitate the design and reduce the power
dissipation of the AAF, it is possible to increase the sampling
frequency, resulting in reducing the attenuating requirements of
the AAF. Since a sigma delta modulator requires a high over-
sampling ratio (OSR), (which corresponds to a high sampling
This work was supported by the Portuguese Foundation for Science
and Technology under project PEst-OE/EEI/UI0066/2013 and Ph.D. Grant
SFRH/BD/87476/2012, and PROTEUS in the scope of the European Unions
H2020 Programme for research, technological development and demonstration
under grant agreement No. 644852.
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978-1-4673-6853-7/17/$31.00 ©2017 IEEE
frequency), it is a better choice for the ADC topology than
a SAR, because the overall power dissipation of the channel
(AAF + ADC) is lower. Moreover a sigma-delta modulator
can achieve a SNDR higher than 70 dB without requiring
calibration schemes. In the case of the proposed acquisition
channel, the sampling frequency of the modulator is selected
to be Fs = 2 MHz, which allows using simple RC circuit as
the AAF and still obtain more than 40 dB of alias suppression.
II. R EQUIREMENTS FOR A N OTCH F ILTER
The water network frequently shares its location with
power network cables. Considering that the different sen-
sors used for measuring the water quality can be connected
through long cables to the digitizing channel, there will be a
coupling from the power supply signal into the sensors’ cable.
This means that a 50 Hz (EU) or 60 Hz (US) sine wave signal
can be added to the desired signal from the sensor. In some
cases, when the cable from the sensor is close to the power
lines, the amplitude of this unwanted signal can be much larger
than the amplitude of the desired signal. As shown in Fig. 1,
the analog to digital channel has to accommodate the sum of
the amplitudes of the desired signal (AS ) and of the undesired
signal (AB ), while digitizing the desired signal with enough
resolution (SNR) to allows obtaining the desired information
from the sensor.
Vref
AB
50 Hz Vref
Vin n
+ Gain ADC dout
AS
Desired signal
-Vref
Fig. 1. Block diagram of the analog to digital acquisition channel.
In order for the unwanted signal to not cause distortion,
it is necessary to adjust the input gain to have the input
range of the ADC larger than the worst case input amplitude:
Vref > AB . This means that the SNR will be degraded because
the quantization step of the ADC (Vlsb ) will be proportionally
larger when compared to AS . The SNR of the desired signal
at the output of the ADC is given by:
    
A2S 2 A2S
SNR = 10 log 2  2(n−1) ≤ 10 log + 6.02.n + 1.76 (dB) (1)
Vref 2 A2B
assuming that Vref = AB corresponds to the best case scenario.
Equation (1) shows that, if the amplitude of the unwanted
signal is 2 times larger than the amplitude of the desired signal,
the SNR of the desired signal decreases 6 dB (corresponding to
1 bit of resolution). As an example, considering that it is nec- Charge division branch
ФR ФR Ts
essary to acquire the signal from the sensor with 8 bits of Φ1 Φ1
resolution (SNR = 48 dB) and that the unwanted signal has an ФS CS2 ФS
ΦS
ʃʃ
ΦS
CF ʃʃ
amplitude 30 times larger, this means that the ADC must have ΦR ΦR
Ф1 Ф2 ʃʃ
a minimum resolution of at least 8 + 5 = 13 bits, considering Vin - Φ2
Vout ʃʃ
t
some tolerance, the ADC should have at least 14 to 15 bits of Ф2 CS1 Ф1 + (n-1)T (n)T
resolution.
Designing an ADC with a medium resolution (8-11 bits) is Fig. 3. Switched-capacitor integrator using charge division branch.
much simpler than designing an ADC with a high resolution
(13-16 bits). Moreover, the power dissipation of an ADC with Assuming that the amplifier has infinite gain and that
high resolution is much larger than the power dissipation of the charge division branch is not connected to the sampling
an ADC with medium resolution. Analyzing the data from the capacitor CS1 , the circuit’s transfer function is given by:
Boris Murmann survey [2], for ADCs with signal bandwidth  
Φ1 CS1 1
between 2 kHz and 20 kHz (Fig. 2), it is possible to conclude H (z) = (2)
that ADCs with medium resolution have a power dissipation CF z − 1
between 0.1 μW and 100 μW, while ADCs with high resolu- Connecting the charge division branch to the switched
tion have a power dissipation between 50 μW and 1000 μW. network, capacitor CS1 will lose part of its charge (half
1000μ the charge, if CS1 = CS2 ) with each set(ΦS )/reset(ΦR ) cycle.
ISSCC
VLSI Neglecting the influence of the parasitic capacitances, with k
100μ set/reset cycles, the circuit’s transfer function is now given by:
   
Power dissipation (W)

CS1 (k+1) 1 1 CS 1
10μ H Φ1 (z) = = (3)
CF (CS1 + CS2 )k z − 1 2k CF z − 1
CS =CS1 =CS2

1μ
0.1μ
0.01μ
40 50 60 70 80
SNDR (dB)
Fig. 2. Power dissipation of ADCs with a signal bandwidth between 2.5 kHz
and 25 kHz as function of the SNDR (from [2]).
The previous analysis shows that using a high resolution
ADC can result in a power penalty between 50 μW and
900 μW. This means that if a notch filter is used to attenuate
the unwanted 50 Hz signal in the input of the ADC, it is
possible to reduce the resolution of the ADC, and therefore
reduce the power dissipation of the overall analog to digital
input channel. Returning to the previous example, if a notch
filter is capable of attenuating the unwanted signal by 30 dB,
it should be possible to use an ADC with a resolution between
9 to 10 bits instead of a resolution between 14 to 15 bits.
The notch filter should provide at least 30 dB of attenuation
at fp = 50 Hz, this requirement means that it must be imple-
mented using SC circuits because it is not possible to achieve
enough accuracy on the center frequency using continuous time
circuits. The sampling frequency of the SC filter is the same
as the sigma-delta modulator in order to take advantage of the
AAF already in the channel.
III. SC I NTEGRATOR U SING C HARGE D IVISION B RANCH
The large ratio between the sampling frequency Fs and the
pole frequency fp of the notch filter results in a large dispersion
between the values of the capacitors in the SC circuit. In order
to decrease the dispersion, it is required to use SC structures
that deliver a small charge while using a larger capacitor.
The SC integrator [3] shown in Fig. 3 is used to demon-
strate how to increase the capacitance value in switched
networks, using a charge division branch, producing the same
transfer function.
Equation (3) shows that in order to obtain the same transfer
function as in (2), capacitor CS has to be 2k times larger than
CS1 . Using this approach it is possible to reduce the ratio
of CF /CS , which becomes very large when the ratio Fs /fp
increases well beyond the typical 10−100 value.
90 100
This approach works because CS1 is connected to the
amplifier’s virtual ground node during phase Φ2 , i.e., it relies
on this node to decrease the memory effect from CS1 . Note
that, using the charge division branch, the circuit becomes
sensitive to the effects of parasitic capacitances.
IV. F LEISCHER -L AKER SC BANDPASS B IQUAD F ILTER
The SC circuit used to implement the 50 Hz bandpass filter,
shown in Fig. 4(a), is based on the Fleischer-Laker architecture
[4]. Since the filter is implemented in differential configuration,
the buffer with gain −1 is not necessary, and the switched
network with capacitor C5 can be connected to the other side
of the differential circuit, obtaining the same effect.
Assuming that the amplifiers have infinite gain, the circuit’s
transfer function is given by:
Φ1 C1 C4 (z − 1)
HBP (z) = (4)
C3 C5 + C3 C6 (z − 1) + C2 C4 (z − 1)2
Due to the very high ratio of Fs /fp (40.000) and the finite
gain of the amplifiers, when the unity gain buffer GB is not
used, the filter’s central frequency and the zero’s location will
be close by, limiting the low frequency gain (z = 1) of the
filter, which is shown in equation (5), mainly due to the finite
value of G2 and the parasitic capacitance in node v4 .
Φ1 C1 CX G1 (GB − 1)
HBP (1) = (5)
C5 CY (1 + G1 G2 − GB ) − C1 CX (GB − 1)
where,
CX = C2 + C5 + C6 − C2 G1 and CY = C2 + C6 − C2 G1 (6)

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 ФR5 ФR5 VDD VDD
ID1 / 2 ID1 / 2
VDD VDD
ФS5 C5s ФS5 ID2 Vbp M3 M3 Vbp ID2
M5
ФB ФC Vbd M7 VDD VDD M7 Vbd
v5 v6 M5
-1
+ + -
C5 Vo Vi M2 M1 Vi Vi+ M1 M2 Vi- Vo-
ФC ФB
Vx+ Vx-
M6 M6
C6
Vbn M4 M4 Vbn
ФR1 ФR1
ФR3 ФR3
ФS1 C1s ФS1
C2 ФS3 C3s ФS3 Fig. 6. Voltage combiner with source degeneration and DC level shifter.
ФA ФC C4
v1 v2 ФC ФB
Vin - v3 v4 V. PASSIVE SC A DDER
G1 -
ФC C1 ФA + G2
ФB C3 ФC +
Vout BP To remove the 50 Hz component from the input signal, a
Vout LP
GB differential passive SC adder, which single-ended version is
Ts shown in Fig. 7, is used. This structure is similar to the one
ΦA:
ΦB:
used in [6].
ΦC,1: Ф1 Ф2 Ф2
Φ2: Tclk Vout BP Vout notch
C8
ΦS1: C7 Ф1 Ф1 C9
ΦR1:
ΦS3,S5:
Vin
ΦR3,R5:
t Fig. 7. Passive SC adder (single-ended version).
(n-1)T (n)T
Fig. 4. Fleischer-Laker SC filter using charge division branches. Neglecting parasitics, the transfer function of the passive
To avoid using an amplifier with high gain (> 80 dB) to im- SC adder, is given by (7). If the capacitors have the same value,
plement G2 , the virtual ground reference technique described the adder, which behaves as a lowpass filter, has a bandwidth
in [5] is used. This technique uses a unity gain buffer GB to of approximately Fs /10, which can be extended by increasing
improve the feedback factor of the second amplifier, pushing C7 and C8 or by decreasing C9 .
the zero further back into lower frequencies and improving the C7 C8 (VoutBP + Vin )
low frequency gain of the filter (GB = 1 and neglecting the Hnotch (z) = (7)
effect of the parasitics). However, the parasitic capacitance in −C7 C9 + C8 C9 (z − 1) + C7 (C8 + C9 )z
node v4 still impacts the performance of the filter. Note that in order to remove the 50 Hz component from
As shown by the timing diagram in Fig. 4, 6 set/reset the input signal (Vin ), the output of the bandpass filter (VoutBP )
cycles are used to increase the size of capacitors C1 , C3 , must be in phase opposition in relation to the input signal.
and C5 by a factor of 64, allowing the ratio between the
largest and the smallest capacitors to be reduced. Phase ΦC is VI. S IMULATION R ESULTS
four times longer (4×Tclk ) than the other phases to relax the The SC bandpass filter shown in Fig. 4 and the passive SC
bandwidth requirements of amplifier G1 , due to the increase adder shown in Fig. 7 were implemented in a standard 130 nm
in the feedback factor when C1 increases. CMOS technology with a supply voltage VDD = 0.9 V and a
Amplifier’s G1 and G2 are implemented using a simple sampling frequency Fs = 2 MHz.
folded cascode topology, which is shown in Fig. 5. The SC bandpass filter was originally designed from an
VDD VDD VDD VDD VDD VDD VDD ideal standpoint, without the charge division branches, in order
ID ID / 2 ID ID / 2
10
Mb1 Mb0 Mb0 to have a central frequency of 50 Hz, resulting in the sizing
Vcasp Vbp M5 Vbp M0 M5 Vbp
Vbp shown in Table I (Line B). Due to the very high ratio of Fs /fp ,
Vbn Vcasn Vcasp M4 M4 Vcasp the capacitor dispersion (Cmax /Cmin ) is very high and the area
Mb2 Mb3
Mb2 Mb2 Vo- M1 M1 Vo+ occupied by the capacitors (Line A) becomes excessively large.
Vi+ Vi-
Vo+ Vcasn M3 M3 Vcasn
Vbn
Typical SC The SC bandpass filter was then designed with real compo-
Vcm
Common-Mode Vcmfb Vcmfb M2 M2 Vcmfb nents, using the charge division branches shown in Fig. 4, with
Feedback Circuit
Vo-
6 set/reset cycles, allowing the value of capacitors C1 , C3 , and
Fig. 5. Folded cascode amplifier. C5 to be increased 64 times. The values of C1 (gain tunnabil-
The circuit used to implement the unity gain buffer (GB ) is ity) and C2 (notch frequency tunnability) were also adjusted
shown in Fig. 6, where transistors M1 form a differential pair to compensate for the effects of the parasitic capacitances in
with source degeneration (transistors M5 ), used to increase the the circuit and the finite gain value of G1 and G2 .
linearity in the output voltage range. Transistor M2 , which is The switches were implemented using asymmetric trans-
connected in common drain configuration, sets the small signal mission gates to obtain approximately the same ON resis-
impedance of node Vx to 1/gm2 , forming a low gain voltage tance value in both sides of the differential circuit, during
combiner together with transistor M1 . By applying the inverted normal operation. The design used in the transmission gates is
input signal to the gate of M2 , this structure can achieve more shown in Table I. Since node v4 is very sensitive to parasitic
gain without sacrificing the GBW or increasing the bias current capacitances, causing an increase in the low frequency gain
of transistor M1 . The source follower (transistor M6 and M7 ) (z = 1) of the bandpass filter, the transmission gates used in
is used as a DC level shifter to move the output common-mode the C3 and C3s branches were designed to have small parasitic
voltage to the same value as the input. capacitances (small transistors).

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 TABLE I. D ESIGN USED IN THE SC BANDPASS FILTER gain and moves the zero closer to the central frequency. With
Switches in the C1 and C1s branches buffer GB , the filter’s low frequency gain had an improvement
WN1 (μm) LN1 (μm) WP1 (μm) LP1 (μm) Req (kΩ) of almost 50 dB.
2.00 0.12 8.00 0.12 ≈ 1.55
Switches in the C3,5 and C3s,5s branches 0
WN3,5 (μm) LN3,5 (μm) WP3,5 (μm) LP3,5 (μm) Req (kΩ)
0.20 0.12 1.20 0.12 ≈ 9.50 -10
Cmax
C1 (fF) C2 (pF) C3 (fF) C4 (pF) C5 (fF) C6 (pF) (k) -20

Gain (dB)
Cmin
A 285.73 639.497 277.98 506.239 29.10 519.713
≈ 22.0
B 4.47 10.000 4.35 7.916 0.46 8.127 -30
C 324.20 9.100 278.20 7.916 29.10 8.127 ≈ 0.3 X: 50.0
-40 Y: -41.5
A) Original design (capacitors were scaled in order to have C5 = 29.10 fF)
B) Original design (neglecting the minimum capacitor value of the technology) SC bandpass filter without GB
C) Design using charge division branches (C1 = C1s , C3 = C3s , C5 = C5s ) -50 SC bandpass filter with GB
SC notch filter with GB
-60 -3
The design used to implement amplifiers G1 and G2 is 10 10-2 10-1 100 101 102 103 104 105
shown in Table III, for simplicity reasons both use the same Frequency (Hz)
sizing. The amplifiers were designed for an input common- Fig. 8. Frequency response of the SC bandpass and notch filters.
mode voltage of 450 mV, achieving a gain of ≈ 60 dB.
A transient simulation was performed with a 10 kHz
TABLE II. F OLDED CASCODE AMPLIFIER DESIGN VALUES signal and a 50 Hz interference, to test the SC notch filter
W0 (μm) W1 (μm) W2 (μm) W3 (μm) W4 (μm) W5 (μm) performance under normal operation, achieving a 31.5 dB
88.0 81.0 98.0 60.0 64.0 27.0 attenuation in 50 Hz signal. The 10 dB difference between the
L0 (μm) L1 (μm) L2 (μm) L3 (μm) L4 (μm) L5 (μm) PAC and transient simulations is due to the non-linear effects
1.43 0.18 0.79 1.50 0.65 0.93 of the parasitic capacitances, which are not correctly estimated
Wb0 (μm) Wb1 (μm) Wb2 (μm) Wb3 (μm) VDD (V) Vcm (V) in the PAC simulation, which deteriorates the quality of the
8.8 0.6 9.8 1.4 0.90 0.45 50 Hz notch. The SC notch filter has a total power consumption
Lb0 (μm) Lb1 (μm) Lb2 (μm) Lb3 (μm) ID (μA) Power (μW) of 285 μW.
1.43 0.45 0.79 0.77 50.0 110.2
VII. C ONCLUSION
The design used to implement the unity gain buffer GB An architecture for the implementation of a 50 Hz SC
is shown in Table III. With this design, the buffer achieves a notch filter with very high ratio of Fs /fp was presented. Due
gain of 1.00 for a input common-mode voltage of 450 mV. to capacitor dispersion, and taking advantage of the virtual
TABLE III. D ESIGN USED IN THE LOW GAIN VOLTAGE COMBINER ground nodes in the circuit, charge division branches were
WITH SOURCE DEGENERATION AND DC LEVEL SHIFTER used to release part of the charge stored in the capacitors,
using k set/reset cycles, before transferring it to the following
W1 (μm) W2 (μm) W3 (μm) W4 (μm) W5 (μm) W6 (μm) W7 (μm)
6.0 44.0 58.0 44.0 52.0 98.0 84.0
branches, effectively allowing the value of these small capaci-
tors to be increased, in order to still transfer to correct amount
L1 (μm) L2 (μm) L3 (μm) L4 (μm) L5 (μm) L6 (μm) L7 (μm)
1.44 2.04 1.08 0.48 1.44 1.20 1.08
of charge. By increasing the value of the smallest capacitors,
VDD (V) Vcm (V) ID1 (μA) ID2 (μA) Power (μW)
the ratio Cmax /Cmin decreases and all the capacitors in the filter
0.90 0.45 23.0 10.0 63.7 can be scaled down to reduce the overall area. The number of
set/reset cycles that can be used is dependent on the sampling
The passive SC adder was designed using the sizing shown frequency, due to the time constants in each node of the circuit,
in Table IV. The transmission gates were designed in order and by the finite gain value of the amplifiers.
to have small parasitic capacitances in relation to the main
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