LOW NOISE AMPLIFIER FOR RECORDING ENG SIGNALS IN IMPLANTABLE SYSTEMS
Jordi Sacristán, Ma Teresa Osés
CNM-IMB Biomedical Applications Group (GAB)
Campus UAB 08193 Bellaterra, Spain
ABSTRACT
In this paper, a low noise amplifier used to sense ENG signals with
amplitudes greater than 1µVp has been designed and fabricated in
0.7µm CMOS technology. The electrical characterization and re-
sults in acute experiments with rats are presented. The main char-
√rms ), high CMRR (> 90dB), pro-
acteristics are: low noise (5 nV Hz
grammable gain (77dB-103dB), band pass from 100Hz to 5kHz
and tolerance to the input offset greater than ±50mV . In order to
implement the low cut-off frequency of the band pass filter, an ac-
tive resistor of 80M Ω value has been designed with programmable
tuning.
1. INTRODUCTION
Nowadays, information provided by neural signals obtained from
peripheral nervous system (PNS) through natural sensors can be
used in challenging applications in functional electrical stimula-
tion (FES). For example, neural signals can be used in spinal cord
injury (SCI) to detect patient intentions and stimulate the action to
carry out in a natural way in a closed loop FES system, or control
a prosthesis in amputees. Another example is the usage of sensory
information obtained by natural sensors to provide some kind of
physical perception, like heat, softness. Common characteristics
of these neural signals are low signal amplitudes, in the range of
1µVp − 10µVp , and low frequency spectrum typically from 100Hz
to 5000Hz. Both parameters make the design of an IC for record-
ing neural activity a very challenging task.
In this paper the development of an amplifier for recording
neural signals from the PNS using cuff or sieve electrodes will be
presented. The low signal amplitude makes the amplifier noise
one of the most important parameters to be considered in the de-
sign process. At the same time, the low frequency range makes
difficult to obtain an implantable device in an application spe-
cific integrated circuit (ASIC) only using on-chip components [1].
Other specifications to be considered for the amplifier design are:
1) High CMRR (> 90dB) to reduce stimulation interference and
contamination due to activity outside the electrodes, 2) A low fre-
quency range for the bandpass from 100Hz to 5kHz, 3) A high
gain (80dB-100 dB) to accommodate the very low amplitude neu-
ral signals (∼ 1µVp ) to the dynamic range of the analog to digital
converter (ADC), necessary for a digital data transmission in im-
plantable systems. 4) A tolerance to the input offsets greater than
±50mV .
In practice, the impedance of electrodes limits the require-
ments for the amplifier noise. If electrodes cuff o sieve with impedances
around 1.5kΩ or 20kΩ respectively are considered, the thermal
noise due to the electrode will determine the minimum value de-
manded for the amplifier noise. Then, the noise specification for
;‹,((( ,9
the amplifier will be 4.8 nV√rms or 13 nV
Hz
√rms , making possible to
Hz
detect input signals as low as 1µVp or 10µVp . Any input signal of
a lower value will be masked by the electrode noise itself.
2. DESIGN STRUCTURE
Fig. 1 shows a simplified schematic of the full amplifier, where
three main blocks can be distinguished. The first stage is a low
noise differential input/differential output preamplifier. In this stage,
noise is the most restrictive parameter in this sense, the thermal
√ of 1500Ω has been considered
noise due to an equivalent resistor
for the electrode (VET NR = 4kT R).
Vin−
G1
Vin+ DDA G3 Vout
A
β
−
s
Fig. 1: Structure of the full amplifier
The second stage is based on a differential difference amplifier
(DDA) [2], It has two pairs of differential inputs, one used as in-
put signal and in the second two feedback loops are implemented,
one to define the gain stage and the second to implement a filter ca-
pable to eliminate the offset from the first stage. In this amplifier,
no external components are needed to implement the low cut-off
frequency and also it is digitally programmable to four different
values. That amplifier can be used without the previous pream-
plifier in case of the input signals from electrodes are greater than
10µVp .
The last stage consists of an RC high pass filter followed by an
operational amplifier with fixed gain that accommodates the signal
to the full range of the ADC. The filter eliminates any residual
offset and the cut-off frequency is programmable like in the second
stage.
A common and important characteristic of the amplifiers for
the first and second stage is the high input impedance. Moreover,
these stages can be directly coupled because their transfer function
presents a zero at the origin and is not necessary decoupling device
resulting, in a higher CMRR and the input signal is kept equal
to the signal readout from electrodes. In consequence, a better
performance is obtained.
,6&$6

2.1. Pre-Amplifier
The preamplifier proposed here is a differential input-differential
output with decoupled DC signal inside the common node using
an external capacitor. The schematic is shown in Fig. 2 and the
transfer function is given by (1). The amplifier input noise due to
the input transistors [3] has to be smaller than the equivalent ther-
mal noise of electrode. Therefore, as the noise in a MOS transistor
for low frequencies is dominated by the flicker noise, it has been
adopted as a design rule that the flicker and thermal noise have an
equivalent contribution. On one hand, considering that the ther-
mal noise generated by a 1.5kΩ resistor is 5 nV √rms (350nVrms
Hz
integrated), the resulting equivalent resistor for input transistors
MP1,2 is 398Ω. On the other hand, a compromise between area
and power consumption fixed the final equivalent resistor of MP1,2
equal to 425Ω giving a slight higher thermal than flicker noise con-
tributions for a biasing current of 200µA.
Rl gm1,2 s
H(s) = gm1,2 (1)
s+ 2C
C
MP 1 MP 2
Vin+ Vin−
VRef
Rl Rl
Vout− Vout+
Fig. 2: Schemaic for the preamplifier
The common mode capacitor C eliminates the offset at the
inputs, so only differential inputs inside the band are amplified.
The in-band gain is given by G = gm1,2 Rl = 50kΩ
425Ω
or G = 41dB
gm1,2
and the low cut-off frequency fl = 4πC = 85Hz for C =
2.2µF . The OTA in Fig. 2 is used to define the DC component in
the common mode output without introducing any effect in the AC
operation.
2.2. Differential Amplifier Band Pass Filter (DABPF)
The DABPF stage is based on a Differential Difference Ampli-
fier (DDA) [2] with filtering feedback. The schematic diagram is
shown in Fig. 3: it has two differential inputs and a single output
with a transfer function similar to the OTA. Here, one differen-
tial pair is used as the input ports and the second one is devoted
to implement two feedback loops. The negative feedback defines
the amplifier gain giving by A ≡ R2R+R 1
1
. The second feedback
loop is used to introduce a zero at DC and a pole at the low cut-
off frequency, implementing a filter that eliminates the input and
residual offset from DDA. The transfer function for the amplifier
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ˆ ˜
can be obtained considering that Vo = D Vin + Vo ( A 1
− −βs
) ,
1
where β = ARInt CInt and D stand for the integration constant
and the DDA open loop gain, respectively. The resulting transfer
function is:
D As
H(s) =  for D → ∞ (2)
1
1 − D( A + βs ) s + Aβ
Vin+
Vin−
DDA Vo
VRef R1 R2
CInt RInt = Rds
VRef
Fig. 3: Structure of the DABPF stage
The high pass filter in the positive feedback loop is imple-
mented with an ideal negative integrator. The integrator can be
considered ideal because leakage currents are not accumulated in
CInt , since it is negatively fed back by the direct path, across
DDA. In consequence only a small residual offset due to the am-
plifier at the feedback loop remains.
The time constant for a high pass filter at 100Hz requieres
high values for RInt and CInt . An acceptable value for an on chip
capacitor CInt = 20pF has been chosen, so the resistor has to be
80M Ω, which is too high to be integrated. In this design a transis-
tor working in sub threshold has been used as an active resistor. In
next section the design considerations for this implementation will
be presented. The high cut-off frequency is 8.9kHz and the phase
margin of 64o which are fixed by a Miller capacitor of 8pF .
It is important to notice that the equivalent thermal noise pro-
duced by the high resistor of filter which is equal to 83µV rms in
the range of frequencies from 100Hz to 5kHz. Consequently it is
not possible to use this resistor for a filter in the direct loop because
the noise is greater than the signal at the input. Nevertheless the
filter, in the DDA amplifier, is used in the feedback loop then, the
thermal noise at the input is reduced by the amplifier gain resulting
in an equivalent noise of 3µVrms .
The power consumption of this amplifier from a voltage sup-
ply of 5V is 250µW . Also, this second stage can be used directly
for ENG signals around 10µVp with an important reduction in
power consumption because the preamplifier is not necessary. This
amplifier has a high CMRR in contrast with traditional instrumen-
tation amplifiers because problems with mismatching components
do not exist.
For the third stage, a single ended amplifier is selected with an
RC filter at the input. This filter allows the AC coupling, eliminates
the residual offset from the previous stage and also the frequencies
out of band, reducing the noise and optimizing the signal to be
converted by the ADC.
 I IRp
The high cut-off frequency is 7.9kHz and the phase margin is given by (6) where N ≡ Ids 2
nad D ≡ Ids1
− 1, so its value
of 65o which are fixed by a Miller capacitor of 6.6pF . Although
ds1
depends only on design parameters.
the bandpass of the full amplifier was fixed to be from 100Hz to
5kHz, the high and low cut-off frequencies in the individual stages Lr Wp Rp D
need to be a bit shifted in order to obtain the desired bandpass. RInt = (6)
Wr Lp ln N
In Table 1 the most important parameters characterizing the
full system are shown. Although, N and D can take any value, N must be greater
than 1 to avoid Ids → 0 here N = 10 has been chosen. The
D parameter has been introduced to reduce the size of transistors,
2.3. High Value Resistor Implementation if D has a high value then mismatching in the current can be a
This section will follow with the design considerations for imple- problem then D = 1 has been chosen because a reduction of 50%
menting the 80M Ω resistor in the filter in Fig. 3 using a PMOS in area is obtained.
transistor working in the sub-threshold region, as depicted in Fig. Another performance added to the polarization circuit is the
4(a). The transistor has an own polarization circuit that optimizes selection of several Rp values through the use of different switches.
the area, and eliminates second order effects due to temperature, In this way, different values for the resistor is obtained and in con-
voltage reference, and technology desviations. In Fig.4(b), the sequence different cut-off frequency can be selected digitally in
schematic diagram of the circuit to generate the biasing for the the filter implementation. Four different frequencies (see Table 1)
PMOS transistor is shown. have been implemented in this prototype allowing to tune a low
Since PMOS works in sub-threshold region, the expression for cut-off frequency from outside according with the actual require-
the current is given by the (3) [4] where Id0 and VT are the specific ments of the implantable system.
current and thermal potential, respectively.
» −V – 3. IMPLEMENTATION AND RESULTS
W Vgb −Vth sb −Vdv
Ids = Id0 e nVT e nVT − e nVT (3)
L The full amplifier described in Fig. 1 has been implemented in
If Vds < ±25mV and Vsb = 0, then Ids can be approximated an ASIC using a CMOS 0.7µm technology from AMIS. Fig. 5
by: shows a microphotograph of the circuit, the full amplifier requires
j » –ff an area of 1.1mm2 and occupies the bottom side of the IC. All the
W VgsnV−Vth −Vds
Ids ∼
= d0
I e T 1 − 1 − (4) individual blocks have been introduced as separate modules with
L nVT testing purposes.
If all parameters are fixed except Vds then MPr behaves as a
resistor controlled by Vgs , resulting in a resistor value of:
Vgs −Vth
∂Ids Id0 W e nVT 1
= L
= (5)
∂Vds nVT RInt

VRef
Vbp

Rp
RInt

Vbp MP 1 1:1 MP2

VRef
MP r Fig. 5: Photography of full amplifier (FA) and test modules.
Vc
For the characterization of the full system an HP4059 func-
Vc MNk MNk MNk
tion generator, a multimeter HP34401A with rms measurement, a
D:1 1:N
digital oscilloscope DL708E and GPIB communication card have
(a) been used. In Table 1 a relation of the most important parameters
are listed, showing good aggreement between the theoretical val-
ues obtained from Montecarlo simulation and experimental data.
(b) The gain fits very well with the four possible values. A small devi-
ation from the simulated results for the cut-off frequency has been
observed but it is not important because they are in the required
Fig. 4: 4(a) Equivalent PMOS to implement the 80M Ω resistor. range of the ENG signals.
4(b) Autobiasing circuit for subthreshold M OSPr In order to verify the AC response the bode diagram shown
in Fig. 6 has been carried out for a total gain of 80dB and using
Transistors MP1,2 work in sub-threshold and define the con- the four programmable cut-off frequencies. From the graphic, it
trol voltage for MPr which is equal to VGSP 1 . The current for can be seen that the −3dB low cut-off frequencies correspond to
MP1 is Ids1 = nVTRpln N . Finally, the value for the RInt resistor the four values indicated in Table 1. The band pass of the amplifier

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 Parameter Simulated Measured
Gain [dB] 75, 83, 97, 103 76, 80, 96, 102
Low-cutoff Freq. 97, 116, 206, 385 106, 119, 201, 352
[Hz]
CMRR[dB@1KHz] −96dB −94
Equiv. input ref- 4.8 5.1
ered noise[ √nV
Hz

Table 1: Amplifier performance (a)

exhibits a roll-off of 60 dec

dB
for the low cut-off frequency and 40 dec
dB

for the high cut-off frequency.

90

80

70

(b)
60
Amplification[dB]

50 Fig. 7: Experimental transient response. (a) Square

wave at 50Hz. (b) 10µVpp for amplitude at 1kHz.
40

30

20

10
1 2 3 4 5
10 10 10 10 10
Frequency[Hz]

Fig. 6: Experimental bode of full-amplifier

The transient response has been carried out with a square input
of 50Hz to verify the rejection of the offset and those frequencies
below 100Hz, Fig. 7(a). Also a sinusoidal input from the function
generator has been used to obtain the response for low input signal
in the band (10µVpp and 1kHz), in this case the amplifier was
programmed to have a gain of 80dB and the low cut-off frequency Fig. 8: Results for acute experiment with rats
was programmed at 200Hz (Fig. 7(b)).
Finally, this prototype has been used in acute experiments in
5. ACKNOWLEDGMENT
a rat, opto-couplers have been incorporated to isolate the record-
ing circuitry from the measure equipment. In Fig. 8 the action This work has been supported by ESPRIT Cyberhand project IST-
potentials due to motor units activation affer to pain stimulation is 2001-35094 and Spanish CYCIT TIC2000-1398-C03-01.
shown. In this test, the rat’s foot was punctured with a needle and
the response was also recorded in the foot with a needle electrode
placed near the nerve. 6. REFERENCES

[1] Cameron Charles Reis R. Harrison, “A low-power, low-

4. CONCLUSION
In this paper the design implementation and test of an amplifier for
recording of ENG signals has been presented for the development
of implantable systems. The obtained results show good aggree-
ment beteween simulation and expermiental data. Nevertheless,
the compromise adopted for the ratio area/power consumption can
be improved if the input transistors of the preamplifier are designed
to work in sub-threshold region. In this sense, a new design with
this design strategy will be carried out in order to reduce the power
consumption which is imperative in implantable devices.
noise cmos amplifier for neural recording applications,” IEEE
J.Solid-State Circuits, vol. VOL. 38, no. 6, June 2003.
[2] E. Sackinger and . Guggenbuhl, “A versatile building block:
The cmos differential difference amplifier,” IEEE J.Solid-
State Circuits, vol. SC-22, no. 2, pp. 287–294, Apr. 1987.
[3] Douglas R. Holberg Phllip E. Allen, CMOS Analog Circuit
Design, Ted Buchholz, 1987.
[4] Noel R. Strader Randall L. Geiger, Phillip E.Allen, VLSI de-
sign techniques for analog and digital circuits, McGraww-
Hill Electrical Engineering, 1990.

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