IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO.
2, MAY 1997
Use of Test Structures for Characterization
and Modeling of Inter- and Intra-Layer
Capacitances in a CMOS Process
Pascal Nouet, Member, IEEE, and Alain Toulouse
Abstract—In this paper, we present a global approach for inter-
and intralayer capacitance characterization and modeling. Using
an accurate on-chip measurement method, we have characterized
realistic test patterns, i.e., test patterns consistent with capacitive
couplings encountered in a layout. These reference values have
allowed us to point out some limitations of current models
and to propose new simple analytical models suitable for small
dimension capacitive patterns. This paper emphasizes inter- and
intralayer modeling.
I. INTRODUCTION
C MOS DIGITAL integrated circuits can be defined as a
set of voltage controlled current generators that charge
and discharge capacitive loads. In the past, capacitive loads
used to be essentially intrinsic or extrinsic MOS transistor
capacitances. As scale reduction cannot be applied in the
same amount for interconnections as for MOS transistors, it
is now necessary to perform accurate interconnect capacitance
extraction before delay or power consumption simulations [1],
[2]. In other words, the accuracy of performance evaluation of
an IC design is more and more dependent on the knowledge of
interconnect parasitics [3], [4]. Wiring capacitances drastically
affect internal delays especially with the scale reduction of
active devices (i.e., transistors) that is going to increase the
relative importance of interconnect capacitances.
Post-layout extractors such as DivaTM from Cadence [5]
currently use two-dimensional (2-D) models and foundries are
providing parameters for such “standard” models by measuring
large dimension capacitors or a set of small capacitors con-
nected in parallel. We have developed an original approach
that consists of:
1) implementing realistic interconnect patterns on a test
chip;
2) extracting expected capacitances from layout using
foundry’s models and parameters;
3) measuring pattern capacitances with our on-chip mea-
surement method;
4) extracting post-measurement custom parameters to fit
capacitances with standard models;
5) developing improved models when fitting is not possible
with the standard one.
Manuscript received July 8, 1996; revised November 14, 1996
The authors are with the Laboratoire d’Informatique, de Robotique et
de Microélectronique de Montpellier, LIRMM-U.M.R. C5506, Université
Montpellier II/CNRS, 34392 Montpellier Cedex 5, France.
Publisher Item Identifier S 0894-6507(97)02877-7.
0894–6507/97$10.00  1997 IEEE
233
Fig. 1. Typical interconnection network. Capacitive coupling involves either
two adjacent lines of the same layer or two crossing tracks of different layers.
In comparison with analytical or numerical simulation ap-
proaches [6]–[8], our strategy does not need any information
about the technological process such as shapes of layer cross-
sections, vertical dimensions, or oxide dielectric constant.
The work described in this paper is based on on-chip
measurement of single capacitors with small dimensions. In
Section II, we first establish requirements for the modeling of
interconnect capacitances such as coupling between crossing
or parallel tracks that are the most frequently encountered
in a layout. In Section III, we discuss various measurement
methods and we conclude that on-chip techniques are the more
interesting ones. Among them, our method presents unique
advantages in terms of accuracy. In Sections IV and V, both
test chip and test structure are described and discussed. Finally,
in Section VI, experimental results are given and standard
models are discussed. As a result, a new simple model is
proposed for small dimension cross-over capacitances.
II. REQUIREMENTS FOR ACCURATE
EXTRACTION OF INTERCONNECT CAPACITANCES
When extracting parasitics from a layout, each capacitance
must be calculated as the decomposition of a few elementary
capacitances connected in parallel. However, CAD tools for
layout generation generally route each interconnect layer in a
single dimension. This increases the regularity of interconnec-
tion networks, and the number of realistic elementary patterns
is strongly reduced. In Fig. 1, an example of automatically
generated interconnection network is given. Two families of
parasitic capacitances can be observed.
First, interlayer capacitances involve two different layers.
When two tracks are crossing each other, capacitive coupling
234 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 2, MAY 1997

appears. This parasitic increases the capacitive load of the becomes more and more important. Physical modeling is
electrical node, and this mainly leads to an increase of delays currently based on the plate capacitor equation where oxide
and dynamic power consumption. thickness is equal to the separation between facing edges. As
Second, intralayer capacitances concern the coupling be- the thickness of a layer is a technological parameter but not a
tween two adjacent tracks of the same layer. This parasitic is design parameter, intralayer capacitances are calculated with
mainly effective in long interconnection buses with minimum the following equation:
separation between tracks. For long buses, logic levels may be
altered by the switching of a neighboring line.
The problem of parasitic capacitance evaluation can be length (4)
simplified by a correct physical modeling of each elementary
pattern. Then, for a given technology, a set of parameters
where and length are, respectively, the separation between
are calculated to fit chosen models with few measured ca-
both adjacent edges and the total facing length of them.
pacitances (called test patterns). To be representative of all
(in aF) is a function of two technological parameters, the layer
capacitances in a layout and not only of themselves, these
thickness and the oxide dielectric constant. As an analogy with
patterns have to be carefully designed. In the following,
resistance of tracks, this parameter is a capacitance per square
standard models for post-layout extraction of interconnect
of separation. (in aF m sets the maximum separation
capacitances are presented and discussed. It must be noted
for calculation of coupling; when the calculated coupling is
that several foundries, such as Digital Equipment Corp., have
negative, is omitted.
already proposed more complex models [8].

A. Standard Model for Interlayer Capacitances C. A Case Study: Design of Test Patterns
Dedicated to the Plate Capacitor Model
The simplest model for interlayer capacitances is the plate
capacitor one. Edges of both plates are coincident and phys- To determine parameters for a given physical model, it is
ical modeling is achieved by the decomposition of the total necessary to measure a few bench values. As an example,
capacitance in two terms we report how to design test patterns to extract parameters
for the plate capacitor model (1). As two parameters
Area Perimeter (1) and must be determined, two patterns are needed to
solve a set of two equations with two unknowns. First of
where and represent, respectively, the capacitance all, measured capacitances must be high enough to neglect
per area unit and the capacitance per perimeter unit. capacitive coupling between one plate and the line connecting
For two crossing tracks, with both layers called and it the other plate to an external terminal (direct measurement) or
is necessary to take into account fringing effects of layer an internal node (on-chip measurement). Second, test pattern
edge inside layer track that are higher than capacitive designers must be fully aware that each capacitance will be
coupling of two coincident edges It becomes measured with a given error and, as a consequence, model
(2) parameters will be calculated with an induced uncertainty
that is a function of measurement uncertainties and design
where is the capacitance per unit of length of layer edge parameters such as area and perimeter of both test patterns
inside layer and are then, respectively, a function and From two measured capacitances
of the heights of layers and and parameters are calculated as
Finally, the standard model for interlayer capacitances must
fit both (1) and (2) to represent either plate capacitors or
crossing tracks. It becomes

(3) (5)

where is the total length of coincident edges for the

considered pair of layers and is the total length of layer Assuming independent measurement errors on both mea-
inside layer For two crossing wires, is twice the width sured values, worst case errors for the calculated parameters
of layer Finally, for a given pattern, the whole perimeter of are given by:
the area “layer over layer ” corresponds to the sum of the
three terms and with

B. Standard Model for Intralayer Capacitances (6)

The reduction of dimensions in very large scale integra-
tion (VLSI) design is mostly effective in terms of area. with
Indeed, thickness of interconnection layers remains quasicon-
stant while separation between adjacent tracks is reduced. As (7)
a consequence, capacitive coupling between adjacent lines
NOUET AND TOULOUSE: USE OF TEST STRUCTURES FOR CHARACTERIZATION AND MODELING
Fig. 2. On-chip measurement of capacitances: from electrical principle (1), (2) to CMOS implementation (3).
It is obvious that test pattern design must overcome error
amplification phenomenon, i.e., and must be equal to zero
or infinite. To reduce the number of solutions, we make the
realistic assumption that both measured capacitances are in the
same range. Then, one solution is that and
In other words, one pattern must exhibit a high perimeter and
a small area while the other one is mostly sensitive to the
capacitance per area unit.
As general rules, the following must be kept in mind.
1) The minimum number of test patterns needed for a
physical model is equal to the number of calculated
parameters.
2) Each test pattern must be designed to be mostly sensitive
to one of the parameters.
3) Each parameter must strongly influence one of the test
pattern capacitance.
III. ON-CHIP MEASUREMENTS
VERSUS DIRECT MEASUREMENT
Numerous methods have been proposed to measure constant
capacitances. They can be divided into three groups.
1) Direct measurement of a parallel network of devices:
Hundreds of devices are connected and the total capaci-
tance (in the 10 pF range) is directly measured [9], [10].
Measured values correspond only to the average of the
entire population.
2) On-chip measurement methods: An on-chip sensor cir-
cuit is used to determine small physical magnitudes
(in the 10 fF range). It is possible to characterize an
elementary device but a reference capacitance [11]–[14]
and/or a reference test structure [15] are necessary. A
matching error is then obtained when calibrating the
test structure.
3) Measurement of ring oscillator frequency or propagation
time in a string of inverters [16], [17]: Each inverter
is loaded with a large capacitance and the oscillation
frequency is then strongly dependent on the capacitance
magnitude. However, the measured parameter (time)
only depends on the average value of the measured
235
physical magnitude (capacitance). On the other hand,
a reference oscillator is required to calibrate the mea-
surement and implementation on silicon is strongly area
consuming.
The selection process must take into account the available
surface, the desired accuracy, and the type of study (scattering
on a wafer, monitoring, modeling, ). Direct measurement or
ring oscillators are currently preferred for process monitoring.
This is mainly due to the fact that experimental set up is more
complicated for on-chip measurement methods. Nevertheless,
the needs of characterization and modeling make on-chip
methods the most promising.
1) Due to small capacitance sensitivity (fF against pF), a
significant gain is obtained in terms of silicon cost.
2) Scattering studies can only be performed if a single
device with small dimensions can be measured.
3) Some features such as small dimension effects can be
masked by the connection in parallel of a high number
of devices.
IV. TEST CHIP DESCRIPTION
For several years [18], the authors have been developing
an original test structure to improve accuracy of on-chip
capacitance measurement. The test structure uses the derivative
property of the studied capacitor The electrical principle
(Fig. 2) is as follows:
1) First, a time-dependent linear voltage variation is used to
generate a constant current in the unknown capacitance.
This current is given as a function of the input voltage
slope by
(8)
time
2) Then, if a CR circuit is used, the generated current
leads to an on-chip static voltage. It must be noted that
parasitic capacitances such as those in parallel with
increase the time constant but have no effect on the
generated current magnitude.
3) Finally, CMOS implementation can be obtained by
replacing the resistor by a saturated NMOS transistor
236
Fig. 3. Electrical principle of the test structure for on-chip measurement of
small capacitances.
When is lower than the threshold voltage,
acts as a capacitive load and is increasing due
to capacitive coupling. A steady state is reached when
the entire generated current is flowing through the MOS
channel. This steady voltage is also a function of the
generated current.
We use an open-loop operational amplifier as a current com-
parator (Fig. 3). Actually it operates as a voltage comparator
but the diode-connected MOS transistors convert the input
current into a voltage. A constant dc current is applied on
the Iin external terminal to set a reference on-chip voltage on
the noninverting input of the Op. Amp. Depending on
the logic level, two operation modes are possible, static
and dynamic.
The static mode allows test structure calibration. The control
transistor acts as a closed switch while a slow ramp of
dc current is applied on the external terminal. A set of
versus Istat transfer characteristics are then recorded for
various constant currents on the external terminal. The
amplifier element has been designed to optimize silicon cost
[19]. As on-chip node voltage variations are weak, output
voltage linearity versus Istat is obtained on a tunable range.
Tuning is obtained via dc current value.
The dynamic mode is performed by connecting to
while a saw-tooth voltage is applied on Using an estimated
value of the reference current can be deduced from the
previous transfer characteristics. is then determined from
measured values of the input voltage slope, output pseudo-
static voltage and input reference current.
Compared to other on-chip techniques, the advances of our
method are the following:
1) Matching errors are strongly reduced: Indeed, no refer-
ence element is used and calibration is performed on the
same test structure as measurement.
2) Measured values are free of parasitic capacitance influ-
ence: Capacitance under test is serially connected to the
test structure and parasitics connected between input or
on-chip node and ground do not alter the pseudo-static
state.
3) Silicon cost is reasonable: As several capacitances can
be connected to the same on-chip node, the number of
Op. Amps. is strongly reduced.
A 2.5 m test chip [19] has been realized in a 0.8 m
dual metal layer CMOS technology from European Silicon
Structures (ES2). To reduce the silicon cost, a multiplexing
ability has been used to measure 32 capacitances with only
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 2, MAY 1997
Fig. 4. Transfer characteristics of the test structure.
four Op. Amps. These capacitances are connected between
eight external terminals and one of the operational amplifier
inputs. Each capacitance is measured by connecting seven
external terminals to ground while applying the saw-tooth
voltage to the eighth one.
V. EXPERIMENTAL STUDY
A digital oscilloscope is used to measure both input signal
slope and steady-state output voltage. The input saw-tooth
voltage is applied with a function generator and the dc voltages
and currents with a dc parameter analyzer (such as HP4145 or
HP 4156), all instruments being controlled by a computer.
A. Static Behavior
First, each test structure is calibrated. A constant dc current
is applied on the positive static input and the output
voltage is then a function of the current applied on the
inverting static input
In Fig. 4, two transfer characteristics are given to demon-
strate the ability of the test structure to be tuned on different
current ranges. It must be pointed out that the operational
amplifier is not offset compensated [19]. As a consequence,
transfer characteristics are shifted but capacitance measure-
ment accuracy is not affected owing to the calibration step
that is performed before each measurement.
B. Dynamic Behavior
It has been demonstrated [20] that the time needed to
saturate the input transistor drastically increases when the
measured capacitance is small compared to the total capac-
itance of the on-chip node. Since seven input capacitors are
connected between on-chip and ground nodes when measuring
the eighth one, capacitor multiplexing increases on-chip node
capacitance. To improve the test structure response time and
to reach more quickly the output voltage steady state, we have
chosen to saturate as soon as the input signal variation
begins.
In Fig. 5, the dynamic behavior of the test structure is
illustrated. The control transistor is used to initialize the on-
chip node to by connecting the input terminal to
and by applying a low logic level pulse on the control transistor
NOUET AND TOULOUSE: USE OF TEST STRUCTURES FOR CHARACTERIZATION AND MODELING
TABLE I
INTERLAYER CAPACITANCE CHARACTERIZATION. MEASURED VALUES (Cm) ARE COMPARED WITH EXTRACTED VALUES (Cext )
Fig. 5. Dynamic behavior of the test structure. (a) Saw-tooth input voltage.
(b) Initialization pulse. (c) Output signal.
gate. is then strongly saturated as soon as the input slope
begins and the quasi static state is reached more quickly.
As both input signals and are generated with
the same function generator, the experimental setup is very
simple. Indeed, is connected to the trigger output of the
function generator and logic levels are automatically generated
synchronously with the saw-tooth voltage. Curve (c) has been
obtained with of about 0.5 pF. Owing to the precharge step,
the response time of the test structure is nearly independent
of the measured capacitance magnitude. Then, similar graphs
are obtained in the 0.5–500 fF range. This experimental
procedure overcomes previous limitations of the test structure
when the unknown capacitance is small compared to the input
capacitance of the current sensor and the way is then open for
evaluation of capacitances as small as few hundreds of aF.
C. Measurement Accuracy
Measurement Accuracy can be evaluated by scanning all
major error sources. As is equal to over input voltage
slope (called it becomes
(9)
1) Slope Measurement Error: This term depends on the ac-
curacy of the oscilloscope measurement mode. In our case (HP
54 501A) it is:
237
The study of current determination uncertainty must be
split into two terms. The first one represents the error
occurring when the input current is deduced from the matching
of in both calibration and measurement steps. The second
corresponds to the input current uncertainty in the
calibration mode.
2) Matching Error: Uncertainty on measurement
leads to an error on the input current determination that
depends on the slope of the transfer characteristic
as
(10)
Assuming a constant error on the voltage measurement
the error is minimized when
(referred to as the matching error term) is as small as possible.
With the present test structure, the matching error term can be
as small as V nA).
3) Current Control Error: is given by apparatus spec-
ifications for a given input current magnitude (less than 1% at
10 nA for an HP 4156).
Consequently, if the voltage measurement uncertainty is
assumed to be in the 20 mV range, the uncertainty on the
current determination (0.4%) can be neglected and the Worst
Case Estimation (WCE) error is always better than 5%.
Resolution is about 0.1% of the measured value. It is fixed
by the dc current source resolution. Due to relative error
magnitudes, the resolution is not a limiting factor for this
technique.
VI. CHARACTERIZATION AND MODELLING
OF INTERCONNECT CAPACITANCES
Our strategy consists in measuring capacitance of realistic
interconnection patterns, i.e., patterns with dimensions similar
to those encountered in a layout, then, using measured values
as reference values we discuss physical models and parameters
given by the foundry to a standard customer.
A. Inter-Layer Capacitances
Experimental measurements are given in Table I, where pat-
tern dimensions are given in accordance with the parameters
of the standard model (3). For each pair of layers (Polysili-
con/Metal 1, Polysilicon/Metal 2, and Metal 1/Metal 2), layer
238 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 2, MAY 1997
TABLE II
EXTRACTED PARAMETERS AND AVERAGE ERROR
2 corresponds to the upper one. Pattern #3 corresponds to
the crossing of two tracks of minimum width (0.8 m for
polysilicon and 1.2 m for metal) while patterns #4 and #5
correspond, respectively, to 10 m and 20 m crossing lines.
Extracted capacitances have been directly obtained
from post-layout extraction with the DivaTM tool [5]. The aver-
age discrepancy between measured and extracted capacitances
is about 40%. Overestimations are consistent with the fact
that foundry parameters correspond to the worst case data
in order to obtain the slowest behavior of a design. Gener-
ally, slow and fast foundry values demonstrate a scattering
of 10% compared to typical values. However, the strong
underestimation for the minimum dimension pattern must
be investigated. This pattern is the most often encountered
in a real design (see Section II) and cumulative effects of
thousands of under-estimated capacitances may lead to wrong
performance evaluations such as delays or power consumption.
Parameter extraction for the plate capacitor model, the
standard model, and a new model for small dimension effects
will now be discussed.
1) Parameter Extraction for the Plate Capacitor Model
(PCM): Two patterns are used for each layer pair. Pattern #1,
which is strongly sensitive to the capacitance per perimeter
unit (from 30% up to 60% of the total capacitance depending
on the layer pair), is constituted of two stacked lines (1.2
400 m ) and the perimeter to area (P/A) ratio is equal to
1.67. Pattern #2 is a 100 100 m square plate capacitor
that directly depends on the capacitance per area unit (more
than 95% of the capacitance). In this last case, P/A is equal
to 0.04.
Using (1), and are easily deduced from a set of two
equations with two unknowns. Limitations of this model for
a realistic interconnection network, i.e., for a small dimension
cross-over, is demonstrated on Fig. 6 where normalized capac-
itances (measured capacitance over crossing area) are reported
versus the P/A ratio. Dots represents the measured values, with
the pattern number inside the circle, while the continuous line
represents calculated values for the PCM. It must be noted that
the normalized capacitance of pattern #3 has not been correctly
reported on this graph due to its high magnitude (573 aF/ m ).
As mentioned in Section II-A, PCM underestimates capaci-
tances when the tracks are extended outside the crossing area.
2) Parameter Extraction for the Standard Model: The
Standard Model (3) takes into account fringing effects outside
FOR ALL STUDIED MODELS
Fig. 6. Polysilicon/Metal1 interlayer capacitances: Limitation of the plate
capacitor model (PCM) for interlayer capacitances of small dimensions.
the crossing area. Two additional parameters and
are then necessary. However, among our test patterns, none
of them can allow to distinguish the effect of layer edge
inside layer from the effect of layer edge inside layer
Consequently, we have used an average effect of fringing
defined as
(11)
This parameter is sufficient for a correct modeling of
realistic patterns where both layer widths are in the same range.
To extract parameters for this simplified standard model, at
least three test patterns are necessary. Using #1, #2, and #5,
we have determined a set of three parameters for each pair of
layers (Table II).
Average error for our set of test patterns is reduced from
about 22% for the PCM down to 10% for the standard
model. However, pattern #3 is always strongly underestimated
(Fig. 7). It is clearly demonstrated that the standard model
is not suitable to calculate the capacitive coupling between
two crossing tracks of minimum widths. This can be easily
understood if the standard model equation is extrapolated
down to widths equal to zero. The calculated capacitance is
then equal to zero. Now, the real capacitance could not reduce
to zero and a constant capacitance due to the corner of the
crossing edges must be taken into account.
3) A New Model for Small Dimension Effects: To over-
come this limitation, we propose a new modeling of these
NOUET AND TOULOUSE: USE OF TEST STRUCTURES FOR CHARACTERIZATION AND MODELING
TABLE III
INTRALAYER CAPACITANCE CHARACTERIZATION. MEASURED VALUES (Cm) ARE COMPARED WITH
EXTRACTED VALUES (Cext) FOR EACH TEST PATTERN. RELATIVE ERRORS ARE ALSO REPORTED
Fig. 7. Under-estimation of pattern #3 capacitance calculated with the Plate
Capacitor Model (grey bars) or the Standard Model (black bars).
Fig. 8. Cross-over test pattern. Edge effects outside the crossing area are
modeled by a constant capacitance CCR :
small dimension capacitors by use of the following equation:
(12)
where is a constant capacitance representing the offset
effect of a corner. For a typical crossing of conductors, four
corners are then obtained. On Fig. 8, represents the
capacitive coupling between the grey part of track edges.
Parameters are then extracted to optimize the least squares
of the relative error between modeled and measured values
for the five available patterns. As a result, all calculated
capacitances are very close to the measured values. The highest
error is about 1.24% for pattern #5 of the P/M1 pair.
4) Discussion: In Table II, extracted parameters, i.e., pa-
rameters allowing the best fit between measured and modeled
capacitances, are reported. Average error for the five test
patterns is also given. For each pair of layers, we have
extracted parameters for the Plate Capacitor Model (column 2),
the Standard Model (column 3) and the New Model (column
239
4). Typical parameters corresponding to foundry data are given
as a reference (column 1).
One can observe the quasiperfect matching between both
surface and edge dependent terms extracted
for each model. This clearly states that the extra-parameter
of our model for small dimension effects (12) is not a fit
parameter but a real physical parameter representing the three-
dimensional (3-D) effect of conductor capacitive coupling
outside the crossing area. It must be noted that this effect
can not be observed with 2-D numerical simulations. As the
proposed model is built by adding a constant offset to the
standard model, it can be easily implemented in a post-layout
extractor.
An other validation of our approach has been carried out by
performing external measurement on a 300 300 m Metal
1/Polysilicon plate capacitor. Capacitance has been measured
on 8 different test chips and the average value (4.27 pF)
exhibits a maximal scattering of about 0.15 pF. The modeled
capacitance [4.45 pF based on (12)] fits the average value
of measured capacitances to within 4%. This is consistent
with uncertainties on both external and on-chip capacitance
measurements.
Our five test patterns have exhibited several limitations that
must be corrected to increase representativity of extracted
parameters.
1) Patterns #1, #2, and #3 are, respectively, mainly sen-
sitive to the capacitance per perimeter unit (coincident
edges, the capacitance per area unit and
the corner effect Geometry of these patterns
is quite perfect even if pattern #1 could be improved
by increasing the length of both stacked lines to be
consistent with Section II-C.
2) Patterns #4 and #5 must be designed to allow the
extraction of and independently.
B. Intra-Layer Capacitance Modeling
To characterize line-to-line capacitances, we have used nine
patterns defined by design parameters given in the standard
model (4). Track length (400 m) and width (1.2 m) are the
same for each pattern while separation varies from 1.2
m up to 4 m.
Experimental results are reported in Table III together
with post-layout extracted capacitances. These values have
been obtained with both the standard model and parameters
provided by the foundry. Discrepancies between measured
and expected capacitances are, at least for both polysilicon
and metal 1 layers, huge. It is nonsense to perform low-
240
INFLUENCE OF THE EXTRACTION STRATEGY
Fig. 9. Intra-layer capacitance for polysilicon layer. Measured capacitances
2 
( ) are compared with extracted ( ) and modeled (continuous and dashed
lines) data.
level electrical simulation with such approximations in the
evaluation of parasitic capacitances.
On Fig. 9, experimental and expected data are reported
and compared with the standard model. Two pairs of custom
parameters have been used.
1) The first pair (dashed line) is defined by setting to
zero and by calculating to obtain a null error for the
minimum separation between track edges.
2) The second pair (continuous line) has been determined to
optimize least squares between measured and calculated
values.
For each layer, a third parameter pair can be determined by
fixing the minimal separation from which the capacitance is
omitted. This solution has been chosen by the foundry with
a maximal separation for capacitance evaluation of 10 m.
We have also calculated both parameters accordingly with this
rule to fit the maximum capacitance with a null error. It is
demonstrated in Table IV that this extraction technique is not
the more accurate. However, it can be useful, for a layout
extractor, to limit the number of internode capacitances. For
each layer, columns 1 to 4 represent, respectively, typical
parameters (foundry given) and our three sets of custom
parameters. The average error (relative scattering between
measured and modeled data) for each parameter pair is also
given.
It is demonstrated that the standard model is sufficient to
represent line-to-line capacitances with a good accuracy. The
choice of the extraction strategy, i.e., one or two parameters,
will depend on designer constraints. A cost efficient solution
could be the characterization of a single test pattern with
separation equal to that recommended in long buses. For local
interconnection networks, the pitch is generally set to the
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 2, MAY 1997
TABLE IV
ON THE MODEL ACCURACY
minimum allowed, however intralayer capacitances are then
small enough to tolerate few percent of error.
VII. CONCLUSION
An original approach for characterization of parasitic ca-
pacitances has been presented. We first defined requirements
for an accurate extraction of inter- and intralayer capacitances.
On the one hand, realistic benchmark values must be measured
on test patterns and, on the other hand, test patterns must be
carefully designed to allow an accurate extraction of model
parameters.
Then, we have presented various methodologies to perform
capacitance measurements. On-chip methods have been stated
as the most powerful to characterize small dimension effects.
One major advantage of on-chip measurement versus direct
external measurement is a drastic reduction of silicon cost: as
an example, the length of a pattern needed to measure line-
to-line capacitances is four hundred micrometers in our case
while a meander as long as one hundred millimeters is used
for a direct external measurement [10].
Major advances of our test structure are:
1) absolute determination (no reference elements);
2) pseudo-static behavior (no errors due to stray capaci-
tances);
3) strong reduction of matching errors (the calibration step
is achieved on the same device than the measurement
step).
Experimental results have demonstrated our ability to mea-
sure capacitances in the 100 aF range with an accuracy better
than 5%. Owing to the high sensitivity of our measurement
method, we have introduced small patterns for the modeling of
small dimension effects. Based on these benchmark values, we
first established limitations of the standard model for interlayer
capacitances. Then, we have proposed a new model able
to accurately represent realistic capacitances, i.e., capacitive
coupling of the crossing between two minimal width tracks.
Our strategy has been validated by an external measurement
of a large capacitance that fits the modeled value to within
4%. Discrepancies between custom and standard parameters
are currently studied in collaboration with ES2-Atmel. Most
surprising results are those obtained on intralayer capacitances
where foundry parameters lead to a strong under-estimation of
capacitances (up to 72%).
Further developments are currently under investigation.
They concern:
1) a new test structure for process monitoring [21];
2) the use of numerical simulation to reduce the number
of required patterns for processes with more than two
layers of metal.
NOUET AND TOULOUSE: USE OF TEST STRUCTURES FOR CHARACTERIZATION AND MODELING
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Pascal Nouet (M’94) received the M.S. and
Ph.D. degrees in electrical engineering from the
University of Montpellier, France, in 1987 and
1991, respectively.
From 1987 to 1991, his research focused on
electron-beam controllability of CMOS circuits.
Since 1992, he has been a Associate Professor at
the University of Montpellier and a Researcher
at LIRMM (Laboratory for Computer Sciences,
Robotics and Microelectronics) where he is head of
the Test & Characterization group. He is currently
involved in the fields of vlsi circuits design and test and more particularly
on electron-beam contactless testing and elementary device modeling and
simulation.
Alain Toulouse received the M.S. degree in elec-
trical engineering (microelectronics) from the Uni-
versity of Montpellier, France, in 1992. Since 1994,
he has been a Ph.D. student at the Laboratory for
Computer Sciences, Robotics and Microelectronics
(LIRMM), University of Montpellier, working on
process characterization, more precisely on MOS-
FET and interconnect modeling and simulation.
From 1993 to 1994, he was with LIRMM working
on codesign and particularly on the communica-
tion’s protocols of DSP.