th

14 International Conference C-V CHARACTERIZATION OF NONLINEAR CAPACITORS

USING CBCM METHOD

T. SUTORY, Z. KOLKA
MIXED DESIGN BRNO UNIVERSITY OF TECHNOLOGY, CZECH REPUBLIC

MIXDES 2007 KEYWORDS: Charge-based capacitance measurements, MOS

Ciechocinek, POLAND characterization, Test structures
21 – 23 June 2007

ABSTRACT: The paper deals with a modification of CBCM (Charge-Based Capacitance Measurements) for nonlinear
capacitance characterization. The method is characterized by high resolution although it is based on equipment found in
any average laboratory. CBCM was originally developed for linear interconnect measurements. The proposed modification
uses two DC swept sources to measure the whole nonlinear Q-v characteristic in both polarities without the necessity to
switch the measured object. A test-chip implementing the method was designed and manufactured in 0.35Pm CMOS
process. Verification against known capacitances proved the method correctness and accuracy. It was successfully used for
MOSCAPs characterization in full operating voltage range.

INTRODUCTION
There are several methods for measuring small on-chip
interconnect or device capacitances in the femtofarad
range. They differ in principles, in demands on
measuring instruments, and in accuracy and resolution.
Recently, the CBCM method (Charge-Based
Capacitance Measurements) has found extensive use
[1]. The method is characterized by high resolution
although it is based on equipment found in any average
laboratory. CBCM was originally developed for linear
interconnect measurements. Sub-femtofarad resolution
has been reported [3]. Next chapters show a
modification of the method to nonlinear capacitance
characterization. The test structures developed serve for
on-chip MOSFET gate capacitance measurements in the
0.35-Pm CMOS technology to support the design of
linearized capacitors using standard MOSFET gates.
STANDARD CBCM METHOD
The CBCM method introduced in [1] has recently
gained considerable popularity. The most important
property consists in its resolution, which allows for
example measuring the capacitance of neighboring on-
chip metal interconnects in the femtofarad range. In
contrast to other methods for small capacitances it does
not need a reference on-chip capacitor. The accuracy of
such capacitors is critical for the overall accuracy of the
measurement. Moreover, it is necessary to integrate
several capacitors for individual ranges of measurement
to maintain acceptable accuracy.
The only equipment needed for the CBCM method is an
accurate ammeter for the measurement of DC supply
current. Fig. 1 shows the principle of the classical
version of CBCM.
Fig. 1: Classical version of CBCM method
The test structure consists of a pair of NMOS and
PMOS transistors connected in a “pseudo” inverter
configuration, each of them has its own gate input. The
pseudo inverter structure on the left is used as reference
to achieve the highest resolution. The structure on the
left is identical to the one on the right in every manner
except that it does not include the target capacitance Cx
to be characterized. The left and right structures are
both driven by two non-overlapping signals. These can
be either generated off-chip or on-chip. The purpose of
these non-overlapping waveforms is to ensure that only
one of the two transistors on either the left or the right
side is conducting current at any given time. Thus,
short-circuit current from Vdd to ground is eliminated.
When the PMOS transistor turns on, it will draw charge
from Vdd to charge up the target capacitance measured.
This amount of charge will subsequently be discharged
through the NMOS transistor into ground. An ammeter
can be placed at the source of the P-MOSFET (or,
alternatively, at the source of the N-MOSFET) to
measure this charging current. The actual waveform of
this charging current is not important - only its DC or
average current value needs to be measured [3]. The
difference between the two DC current values is used to
extract the measured target capacitance Cx as given by

Copyright © 2007 by Department of Microelectronics & Computer Science, Technical University of Lodz 501
 I  I ´ C x ˜ Vdd ˜ f (1) The following paragraph presents a modified CBCM
method for the measurement of nonlinear capacitors.
where f is the switching frequency, while currents I and
I’ are introduced in Fig. 1. MODIFIED CBCM METHOD
It is obvious from (1) that the currents and thus the
resolution of the method can be increased by means of The proposed modification of the CBCM method is
increasing Vdd and the frequency. Vdd is limited by the applicable to measurements of floating devices. Two
technology and the maximum frequency is determined DC sources are used to measure the whole nonlinear
by the on-resistance of switching transistors. The characteristic in both polarities without the necessity to
capacitance under test must be completely charged and switch the device under test (Cx). One source is swept
discharged during one period. Thus the switching while the other is kept constant, and vice versa. For
transients should be shorter than the period. These each point of the characteristic a minimal voltage
transients can be sped-up by increasing the switching amplitude and thereby a minimum DC current is
transistor width, i.e. by decreasing their on-resistance. guaranteed. The principal schematic of the proposed test
This can be done only in a limited range because the structure is shown in fig. 2.
transistor enlargement increases the gate capacitances
and thus increases the undesirable charge injection from
driver circuitry to the device under test. If the two
structures were ideally matched, the charge injection
would be completely subtracted in (1). Unfortunately,
they are not identical in principle. The measured
capacitor is connected to the right structure. Thus we
observe different waveforms of voltages and currents
during transients. Because of nonlinearity the effect of
the same gate capacitance will be different for the left
and right switches. It can be eliminated partially by
means of charge-compensated switches with NMOS
and PMOS transistors driven by mutually inverted Fig. 2: Modified CBCM method
signals [4].
The resolution limit of the method resides mainly in the The waveforms of driving signals and other important
mismatch of the drain junction and overlap capacitances quantities are shown in fig. 3.
between the left and right test structures of Fig. 1. The
measured DC current for the test structure with and
without the target interconnect capacitance is given by
I C x  C´ ˜ Vdd ˜ f (2a)
I ´ C´˜Vdd ˜ f (2b)
where Cx is the unknown capacitance to be measured,
and C’ is the MOSFET gate to drain overlap
capacitance plus drain junction capacitance plus any
other parasitic capacitances. If the two structures were
perfectly matched, the term would be completely
subtracted and would not impose a resolution limit. In
reality, there is a mismatch between the parasitic
capacitances, due to Weff and Leff matching. This value is
uniquely determined by the process technology.
In order to minimize this error, the W/L sizes of the
NMOS and PMOS transistors should be drawn with
dimensions that are optimal for achieving precise
matching characteristics [3].
The CBCM method is normally used to characterize
linear capacitances, e.g. interconnect capacitances. The
simple version of the method is not well suited for the
characterization of nonlinear capacitors such as
MOSFET gate capacitances. Nonlinear capacitors are
characterized by the C-v or Q-v curves. The standard
CBCM allows Vdd sweeping but for low voltages its
resolution decreases and becomes unacceptable. This is
especially critical for minimum-feature transistors,
where it is desirable to use high Vdd to obtain a
reasonable current.
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Fig. 3: Waveforms of signals in modified CBCM method
The basic principle of CBCM with the main (right) and
compensation (left) switches as shown in fig. 1 is the
same also for the modified method. The DC source Vdd
was renamed Vdd1. The main difference is on the
negative terminal of the measured object. The ground
connection is replaced by a switch and the node can be
additionally connected to another DC regulated source
Vdd2 by a bidirectional switch.
One period of controlling signals can be divided into
four non-overlapping phases, fig. 3.
During phase 1 the measured capacitor is charged to a
negative voltage (seen on its terminals) from the source
Vdd2 through the switches L and S. During phase 2, L is
switched off and S remains switched on. Activating the
switch H in phase 3 causes charging the capacitor to the
voltage Vdd1-Vdd2. The charge drawn during 2o3
transient is counted by the ammeter. The voltage
changes for Vdd1. During the last phase S is switched off
and the capacitor is charged to Vdd1 through the switch These logical signals are generated by the control
D. The voltage changes for Vdd2 and the charge drawn is computer.
again counted by the ammeter.
The capacitor voltage varies during one period from
Vdd2 to Vdd1 and the charge variation can be determined
from the measured current as
Vdd 1
I  I'
'Q(Vdd 2 , Vdd 1 )
f ³ C (v)dv .
Vdd 2
(3)

The dynamic capacitance C(v) can be determined from

the reconstructed Q-v characteristic of the capacitor.
Formula (3) gives only the value of charge variance.
Let us start the reconstruction of Q-v characteristic for
negative voltages from Vdd2 = 0. The voltage variation is
then Vdd1 and the charge variation is 'Q(0,Vdd1). For
zero voltage the charge must be zero too, i.e. Q(0) = 0.
This gives a fixed point in the characteristic. The
change of charge due to the sweeping of Vdd2 is
Fig. 5. Block diagram of test-chip
considered relative to this point. Finally we obtain
Q Vdd 2 Vdd1 const 'Q0, Vdd 1   'QVdd 2 , Vdd 1  (4) Clock signal CLK from an external clock generator
determines the switching frequency. First, the signal is
and similarly for the positive voltage split into two paths and phase shifted. Then, two signals
QVdd 1 Vdd 2 'QVdd 2 , Vdd 1   'QVdd 2 ,0  .
const
Thus the device can be characterized in both polarities
by means of sweeping one source while the other is kept
constant, fig. 4. Both static and dynamic capacitances
can be determined from Q(v).
Fig. 4: Reconstruction of Q-v characteristic
TEST-CHIP DESIGN
The modified CBCM method was implemented in a
test-chip to verify its functionality and to characterize
nonlinear MOS-gate capacitors and compensation
structures. The chip was manufactured in the AMIS
I3T80 0.35 Pm process.
The test-chip consists of several test-cells, whose
principal schematic is shown in Fig. 2. Each cell is
connected to a device under test (MOS capacitor, metal-
metal capacitor or external device). The block diagram
of the whole chip is shown in fig. 5.
The supply terminals of all test-cells are connected
together and lead out from the chip to pads Vdd1, Vdd1’
and Vdd2. Fig. 6 shows details of power supply and
biasing of the test-cells. To allow the measurement of
only one capacitor all test-cells have an enabling input.
The selection of activated structure is determined by a
shift register controlled via SCLK and SDATA signals.
(5) are generated for each path by a non-overlap generator.
All four non-overlap signals are distributed to all test-
cells. Non-overlap signals are necessary to avoid the
flow of short current. Fig. 6 shows in detail the test-chip
power supply system. Vdd1, Vdd1’ and Vdd2 pins are
powered from swept power supplies according to the
modified method principle. A sensitive ammeter A
measures the currents Idd1 or Idd1’ according to the
position of switch SW.
Fig. 6. Schematic diagram of test-chip power supply
Since the power supply voltages vary from 0 to 3.3 V,
the correct driving voltages for MOSFET switches H, L,
D and S are obtained using the level-shifters LS
supplied from constant-voltage sources relative to Vdd1
and Vdd2. The control signals for switches are
generated in a small digital unit supplied from VDD.
The test-cell topology is universal. It is just the
switching sequence generated in the digital unit that
determines the actual measuring method. Besides the
modified CBCM it is possible to generate sequences for
parasitic capacitance measurement [5], [6] classical
CBCM and CBCM with a floating capacitance. These
additional methods were implemented for verification
purposes and as a backup solution.
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There are 64 test-cells for 64 capacitors to be
characterized. Only one structure is enabled during the
characterization. The others are disabled. Such a
relatively high number of cells can produce significant
leakage currents especially at high temperatures. A
technique of equipotential shielding is used. The
disabled cells are biased to Vdd1 to minimize the
leakage current of the supply voltage switches, fig. 7.

Fig. 9. Bench-board

MEASUREMENT RESULTS
One test-cell was dedicated to measuring the external
devices. Table 1 shows the results for three capacitors,
whose capacitance was verified by an LCR meter.
Fig. 7. Test-cell enabling circuitry
TABLE 1. External capacitor measurement
The chip was manufactured in the AMIS I3T80 0.35Pm Cref Cmeas
technology. Dies were assembled in dual in-line (measured (measured
Cnom by RLC by Error
ceramic prototype package with 40 pads. The package
meter) MCBCM)
was selected for easy plugging-in to the bench-board
through the zero insert-force socket and for opportunity pF pF pF %
to probe the chip easily for potential debug purposes. 100 pF 99.77 98.96 -0.8
The 64 test structures include linear metal-metal 22 pF 22.00 22.17 0.8
capacitors for method verification, MOS gate capacitors 10 pF 9.938 10.03 0.9
and structures for their linearization, internal test
structures and one structure for external capacitor The IC pad capacity is about 5pF, i.e. 50% of the
measurement. smallest capacitor. Nevertheless, it was compensated by
the compensating structure. The clock frequency
depends on the capacitance measured, i.e. on switching
transients duration. For values from Table 1 it was from
2kHz to 4kHz.
Integrated linear metal-metal capacitors were used to
verify the method linearity for smaller capacitances. The
test structures were prepared as 1, 4, 10, and 20 unit
capacitors. Although the capacitors are subject to
process variations, Table 2 shows a very good
agreement between the expected and the actually
measured values. The values of Cmon were determined
by statistical fit to linear equation C nom aN  b ,
where N is the number of units.
Fig. 8. Top layout and die photograph of test-chip

Fig. 9 shows a bench-board with a socket for test-chip. TABLE 2. Metal-metal capacitor measurement
The bench-board is connected to PC via USB and
serves for the supply, configuration, and biasing of the Units [-] 1 4 10 20
test-chip. The supply current at Vdd1 is measured by a Cnom [pF] 0,9857 3,9230 9,7976 19,5886
sensitive Agilent 3458A ammeter. Both the power Cmeas [pF] 0,9840 3,9237 9,7999 19,5878
supply and the clock generator are controlled from PC Error [%] -0,17 <0.1 <0.1 <0.1
via GPIB. As the test-chip contains minimum circuitry,
the capacitor characterization requires sweeping and The main purpose of developing the method was to
measuring many analog parameters. Thus computer characterize nonlinear MOS gate capacitors. Such
control is a necessity. capacitors provide a higher specific capacitance per unit
area and do not require additional masks, but the

504
nonlinearity must be carefully compensated. Fig. 10
shows a measured Q-v characteristic of 1Pm x 1Pm
NMOS transistor. The clock generator frequency was
set to 10 MHz.
Fig. 10. Q-v characteristic of MOS gate
C-v characteristic in fig. 11 was obtained from Q-v
characteristic using numerical derivation.
Fig. 11. Nonlinear MOS gate capacitance
CONCLUSIONS
A modification of the CBCM method for nonlinear
capacitance characterization was proposed. Just two DC
sources are used to measure the whole nonlinear
characteristic in both polarities without the necessity to
switch the measured object. A test-chip implementing
the method was designed and manufactured in the
0.35Pm CMOS process. Verification against known
capacitances proved the method to be correct. It was
successfully used for MOSCAPs characterization in the
full operating range.
THE AUTHORS
Tomas Sutory and Zdenek Kolka are with the
Department of Radio Electronics, Brno University of
Technology, Purkynova 118, 612 00 Brno, Czech
Republic.
E-mail: xsutor00@stud.feec.vutbr.cz
ACKNOWLEDGEMENTS
Research described in the paper was financially
supported by the Czech Grant Agency under projects
No. 102/05/0771 and No. 102/05/0277, and by the
Czech Ministry of Education under research program
No. MSM0021630513. The test-chip was developed
and manufactured in cooperation with the AMI
Semiconductor Czech company.
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