IEEE International Conference on Computer, Communication and Control (IC4-2015).

Ultra Low Power Multiplexer design using Variation

in CMOS Inverter
Nidhi Maheshwari1,Prithviraj Singh Chauhan2 Debendra Kumar Panda3
Mewar University Medicaps Institute of Technology and Management
Chittorgarh, India Indore, India
nids.maheshwari17@gmail.com1, prithvi_15@yahoo.co.in2 debendrakumar.panda@gmail.com3

Abstract—Low power VLSI demands for the development of Fig. 2(a) and (b) respectively show the circuit representation
promptly design methodologies to reduce the power consumption and truth table of a basic 2-to-1 multiplexer.
or power dissipation up to a level. To meet the growing demand,
we propose a new low power multiplexer cell by reducing the
MOS Transistor count that reduces the serious threshold loss
problem. In the proposed circuit we use CMOS technique for
designing of ultra low power multiplexer because in CMOS
techniques there is almost zero static power dissipation. In
conventional multiplexer there are 12 number of transistors
which consumes more power as compare to proposed multiplexer
which include only 8 number of transistor in CMOS form,
considerably increases the speed and decreases the power when
compared to the conventional multiplexer. Also proposed circuit
consumes less power as compare to dynamic multiplexer.

Keywords—CMOS; Static & Dynamic Multiplexer; low power;

static power dissipation

I. INTRODUCTION
Fig.1: The schematic diagram, Boolean equation and the truth table of a 2:1
multiplexer with inputs A and B, select input S and the output Z
The increasing prominence of portable systems and need to
limit power consumption has led to rapid and innovative
developments in low power VLSI design during recent
years[1]. The driving forces behind these developments are
portable device applications requiring low power consumption
and high throughputdue to their small chip size with large
density of components, increased complexity and high
frequencies[2].
A multiplexer or MUX ordata selector is a combinational
circuit with more than one input line, one output line and more
than one selection line. MUX selects several analog or digital
input signals and forward the selected input into a single
output line. A multiplexer of 2n inputs has n selected lines, are
used to select which input line is send to the output [1-2].
There are some multiplexer IC’s that provide complementary
outputs. The multiplexers in IC form almost invariably have
an ENABLE or STROBE input, which needs to be active for
the multiplexer and be able to perform its intended function
[3].
A multiplexer selects binary information present on any one of
the input lines, depending upon the logic status of selection (c)
inputs, and routes it to the output line. If there are n selection Fig.2:(a) 2-to-1 multiplexer circuit representation, (b) 2-to-1 multiplexer truth
lines, then the number of maximum possible input lines is 2n table and (c) 2-to-1 multiplexer
and the multiplexer is referred to as a 2n-to-1 multiplexer or
2n×1 multiplexer[4].
II. CMOS INVERTER
 IEEE International Conference on Computer, Communication and Control (IC4-2015).
In Fig. 3, the input voltage is connected to the gate terminals
of both nMOS and pMOS transistors. Thus, both transistors
are driven directly by the input signal, Vin. The substrate of
nMOS transistor is connected to the ground, while the
substrate of pMOS transistor is connected to the power supply
voltage, VDD, in order to reverse-bias the source and drain
junctions. Since VSB= 0 for both devices, there will be no
substrate-bias effect for either device[5]. It can be seen from
the circuit diagram in Fig. 3 that
VGSn= Vif
VDS=Vot (1)
and also,
VGS,P =-(VDD- Vif)
VDS,P=-(VDD-Vut) (2)
We will start our analysis by considering two simple cases.
When the input voltage is smaller than the nMOS threshold
voltage, i.e., when Vi <Vtn,nMOS transistor is cut-off. At the
same time, the pMOS transistor is on and operating in linear
region. Since the drain currents of both transistors are
approximately equal to zero (except for small leakage
currents), i.e.,
IDn=IDp
the drain-to-source voltage ofpMOS transistor is also equal to
zero, and the output voltage VOHis equal to the power supply
voltage.
Vout=VOH=VDD(3)
Fig.3: (a) CMOS inverter circuit (b) Simplified view of CMOS inverter
consisting of two complementary non-ideal switches
On the other hand, when input voltage exceeds (VDD + VT);the
pMOS transistor is turned off. In this case, the nMOS
transistor is operating in linear region, but its drain-to-source
voltage is equal to zero because condition (2) is satisfied.
Consequently,output voltage of the circuit is
Vout=VOL=0
Next, we examine the operating modes of nMOS and pMOS
transistors as functions of the input and output voltages. The
nMOS transistor operates in saturation if VIN>VTon and if the
following condition is satisfied.
VDSn≥VGSn-VTon
Vout≥Vin -VTon
III. PROPOSED DESIGN
For a digital circuit, the most essential parameters are
power & delay. The circuit having an optimized power and
minimum delay is best suitable for many applications, thus for
designing an low power circuit CMOS technique is best
suitable because it has almost zero static power dissipation. Its
implementation and working principle is given as:
For CMOS inverter, its working principle states as
whenever the input is low means having voltage less than
threshold voltage (less than nMOS and greater than pMOS)
then pMOS will be in ON condition and behave like a
resistance so that current will flow w.r.t. the resistance and
represent an output voltage which will be lies in logic 1 level
and thus inverter inverted its output and similarly
complemented operation is repeated for nMOS.
With the operation in the threshold voltage of pMOS&nMOS,
CMOS inverter can be converted in to NAND, NOR and NOT
gate.
From the circuit, it is conclude that a multiplexer can also be
design using only 8 numbers of transistors which are arrange
in CMOS form. From the gate level view of 2:1 MUX it is
seen that only 4 gates are used in which one is simple inverter
and other threeare 2-input NAND gate and our proposal is to
design these 2-input NAND gate using 2 MOSFET connected
in CMOS style.
Fig.4: Gate analysis of Multilexer
Fig. 5: Proposed Design using MOSFET
The NAND gate can be design using CMOS logic by variation
in the threshold voltage of CMOS inverter circuit. Set the
(4)
threshold voltage of pMOS as low and set the threshold
voltage of nMOS as high so that output will be high,till there
is 70-75% of input logic level and become low when the input
voltage rises above this level.
 IEEE International Conference on Computer, Communication and Control (IC4-2015).

The capacitor value can be change according to the logic

swing required and thus from the calculation of capacitor
value as:
C=qV
i.e., as the capacitance value vary the corresponding variation
in voltage value and this value is in logic swing level.

IV. SIMULATION RESULTS

The conventional multiplexer contains 12 number of
transistors inany logic function, the complementary CMOS is
realized by nMOS pull-down and pMOS pull-up networks
connected between gate, output and power lines[2]. Input Fig.8: Schematic design of proposed 2:1 multiplexer
signals are connected to transistor gates only.
Schematic of conventional 2:1 multiplexer and their The ultra low power proposed design using CMOS is shown
simulation results are shown in Fig.6 with supply voltage as in Fig. 8 and its simulation result for supply voltage VDD=1V&
VDD=1V and analysis for 0ns to 100ns duration . for duration 0ns to 100ns is shown in Fig. 9.

Fig.9: Simulation result of 2:1 proposed multiplexer

On the basis of power and delay, analysis is done on 45nm

technology and for supply voltage from 0.6v to 1.5v; power
dissipation result in mWis given in Table-I and delay analysis
for supply voltage from 0.6v to 1.5v is given in Table-II.
Fig.6: Schematic of conventional 2:1 multiplexer
TABLE I
Supply Dissipation Power
Voltage Conventional Proposed
0.6V 4.14 1.02
0.8 V 4.19 1.05
1.0 V 4.27 1.08
1.2 V 4.35 1.11
1.5 V 4.49 1.21

TABLE II
Supply Delay Analysis
Voltage Conventional Proposed
0.6 V 5.81 8.54
0.8 V 5.74 8.06
1.0 V 5.66 7.82
Fig.7: Simulation result of 2:1 conventional multiplexer 1.2 V 5.45 7.57
1.5 V 5.31 7.12
 IEEE International Conference on Computer, Communication and Control (IC4-2015).

V. CONCLUSION
From the above result, it is concluded that the power
dissipation in the proposed circuit is approximately 75.19%
lessthan static (conventional design) circuit but have 57.17%
more delay as compare to static circuitand have approximately
85.01% delay as compare to dynamic circuit.

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