Sri. L. GuruKumar, Asst. Prof., UNIT-III Low Power VLSI Design[E.C.E.

UNIT – III
CMOS & BICMOS LOGIC GATES
1. Introduction
The design considerations for a simple inverter circuit were presented in the previous chapter.
In this chapter, the design of the inverter will be extended to address the synthesis of arbitrary
digital gates such as NOR, NAND and XOR. The focus will be on combinational logic (or non-
regenerative) circuits which may poses the property that at any point in time, the output of the
circuit is related to its current input signals by some Boolean expression (assuming that the
transients through the logic gates have settled). No intentional connection between outputs and
inputs is present. In another class of circuits, known as sequential or regenerative circuits to be
discussed in a later chapter, the output is not only a function of the current input data, but also of
previous values of the input signals (Figure 3.1). This is accomplished by connecting one or more
outputs intentionally back to some inputs. Consequently, the circuit “remembers” past events and
has a sense of history. A sequential circuit includes a combinational logic portion and a module
that holds the state. Example circuits are registers, counters, oscillators, and memory

Figure 3.1 High level classification of logic circuits.

There are numerous circuit styles to implement a given logic function. As with the inverter, the
common design metrics by which a gate is evaluated include area, speed, energy and power.
Depending on the application, the emphasis will be on different metrics (e.g., in high performance
processor, the switching speed of digital circuits is the primary metric while in a battery operated
circuit it is the energy dissipation). In addition to these metrics, robustness to noise is also a very
important consideration. We will see that certain logic styles (e.g., Dynamic logic) can significantly
improve performance, but can be more sensitive to noise. Recently, power dissipation has also
become a very important requirement and significant emphasis is placed on understanding the
sources of power and approaches to deal with power.

2. MOSFET Approximations
MOSFETs can be approximated as either open or short circuits between drain and source.
A benefit of mapping a whole range of voltages to a single logical value is that it allows us to make
aggressive approximations in circuit analysis. For example, in order to see whether a logical value
is 1, we do not need check that the corresponding voltage is exactly VDD, just that it is
approximately VDD. Extending this reasoning leads to a useful set of logic circuit approximations
for NMOS and PMOS transistors.

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Table 3.1: MOSFET logic circuit symbols and approximations.

The logic circuit symbol for an NMOS transistor (Table 3.1) is slightly different to its analog circuit
symbol. In a logic circuit, an NMOS transistor is always drawn with the drain terminal at the top
and the source terminal at the bottom. In contrast, the logic circuit symbol for a PMOS transistor
is always drawn with the source terminal at the top and the drain terminal at the bottom. The
PMOS transistor symbol includes a bubble at the gate terminal that represents logical inversion
(to be explained below). Note also that the input A labeled at the gate terminal of each MOSFET
in Table 1 is a logical value. When A=0, the voltage at the gate terminal is close to ground; when
A=1, the gate terminal voltage is close to VDD.
The approximations in Table 3.1 replace each MOSFET's drain-source connection with an open
or short circuit depending on the type of MOSFET (NMOS or PMOS) and the logical value A. These
substitutions are justified by the way that a MOSFET's gate-body connection behaves like a
capacitor controlling its drain-source connection. To give a specific example, an NMOS transistor
with A=0 has gate voltage close to ground, and consequently its drain-source connection is open.
When A=1, the NMOS transistor's gate voltage is close to VDD, and so it has a connected drain-
source connection. The corresponding PMOS transistor substitutions are reversed with respect
to the value of A. Abstractly, you can imagine that the PMOS transistor first inverts A (from 0 to
1, or from 1 to 0) and then behaves the same way as an NMOS transistor. This imaginary logical
inversion is represented by the bubble in the PMOS transistor's logic circuit symbol.
2.1 Static CMOS Design
The most widely used logic style is static complementary CMOS. The static CMOS style is really an
extension of the static CMOS inverter to multiple inputs. The primary advantage of the CMOS
structure is robustness (i.e, low sensitivity to noise), good performance, and low power
consumption (with no static power consumption). As we willsee, most of those properties are
carried over to large fan-in logic gates implemented using the same circuit topology. The
complementary CMOS circuit style falls under a broad class of logic circuits called static circuits
in which at every point in time (except during the switching transients), each gate output is
connected to either VDD or Vss via a low-resistance path. Also, the outputs of the gates assume at
all times the value of the Boolean function implemented by the circuit (ignoring, once again, the
transient effects during switching periods). This is in contrast to the dynamic circuit class, that

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relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes.
The latter approach has the advantage that the resulting gate is simpler and faster. On the other
hand, its design and operation are more involved than those of its static counterpart, due to an
increased sensitivity to noise. In this section, we sequentially address the design of various static
circuit flavors including complementary CMOS, ratioed logic (Pseudo-NMOS and DCVSL), and
passtransistor logic. The issues of scaling to lower power supply voltages and threshold voltages
will also be dealt with. Complementary CMOS. A static CMOS gate is a combination of two
networks, called the Pull-Up Network (PUN) and the Pull-Down Network (PDN) (Figure 3.2). The
figure shows a generic ‘N’ input logic gate where all inputs are distributed to both the pull-up and
pull-down networks. The function of the PUN is to provide a connection between the output and
VDD anytime with the output of the logic gate to be 1 (based on the inputs). Similarly, the function
of the PDN is to connect the output to VSS when the output of the logic gate is meant to be 0. The
PUN and PDN networks are constructed in a mutually exclusive fashion such that one and only
one of the networks is conducting in steady state. In this way, once the transients have settled, a
path always exists between VDD and the output ‘F’, realizing a high output (“one”), or, alternatively,
between VSS and ‘F’ for a low output (“zero”). This is equivalent to stating that the output node is
always a low-impedance node in steady state. In constructing the PDN and PUN networks, the
following observations should be kept in mind:

Figure 3.2 Complementary logic gate as a combination of a PUN (Pull-Up Network) and a PDN (Pull-Down Network).

A transistor can be thought of as a switch controlled by its gate signal. An NMOS switch is on when
the controlling signal is high and is off when the controlling signal is low. A PMOS transistor acts
as an inverse switch that is on when the controlling signal is low and off when the controlling
signal is high. • The PDN is constructed using NMOS devices, while PMOS transistors are used in
the PUN. The primary reason for this choice is that NMOS transistors produce “strong zeros,” and
PMOS devices generate “strong ones”. To illustrate this, consider the examples shown in Figure
3.3. In Figure 3.3a, the output capacitance is initially charged to V DD. Two possible discharge
scenario’s are shown. An NMOS device pulls the output all the way down to GND, while a PMOS
lowers the output no further than |VTp| — the PMOS turns off at that point, and stops contributing
discharge current. NMOS transistors are hence the preferred devices in the PDN. Similarly, two
alternative approaches to charging up a capacitor are shown in Figure 3.3b, with the output load
initially at GND. A PMOS switch succeeds in charging the output all the way to VDD, while the NMOS
device fails to raise the output above VDD-VTn. This explains why PMOS transistors are
preferentially used in a PUN.

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Figure 3.3. Examples illustrating why an NMOS should be used as a pulldown

transistor and PMOS should be used as a pull-up device.

A set of construction rules can be derived to construct logic functions (Figure 3.4). NMOS devices
connected in series corresponds to an AND function. With all the inputs high, the series
combination conducts and the value at one end of the chain is transfered to the other end.
Similarly, NMOS transistors connected in parallel represent an OR function. A conducting path
exists between the output and input terminal if at least one of the inpurs is high. Using similar
arguments, construction rules for PMOS networks can be formulated. A series connection of
PMOS conducts if bothinputs are low, representing a NOR function 𝐴̅ . 𝐵̅ = ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 while PMOS
̅ ̅ ̅̅̅̅̅
transistors in parallel implement a NAND 𝐴 + 𝐵 = 𝐴. 𝐵.

Figure 3.4. NMOS logic rules - series devices implement an AND, and parallel devices implement an OR.

Using De Morgan’s theorems ( ̅̅̅̅̅̅̅̅

𝐴 + 𝐵 = 𝐴̅ . 𝐵̅, ̅̅̅̅̅
𝐴. 𝐵 = 𝐴̅ + 𝐵̅), it can be shown that the pull-up
and pull-down networks of a complementary CMOS structure are dual networks. This means that
a parallel connection of transistors in the pull-up network corresponds to a series connection of
the corresponding devices in the pull-down network, and vice versa. Therefore, to construct a
CMOS gate, one of the networks (e.g., PDN) is implemented using combinations of series and
parallel devices. The other network (i.e., PUN) is obtained using duality principle by walking the
hierarchy, replacing series subnets with parallel subnets, and parallel subnets with series
subnets. The complete CMOS gate is constructed by combining the PDN with the PUN.
• The complementary gate is naturally inverting, implementing only functions such as NAND,
NOR, and XNOR. The realization of a non-inverting Boolean function (such as AND OR, or XOR) in
a single stage is not possible, and requires the addition of an extra inverter stage.
• The number of transistors required to implement an N-input logic gate is 2N.
Digital logic is the mathematical manipulation of zeroes and ones. (Other names for the logical
values 0 and 1 are: low and high; false and true; and off and on.) Virtually all computing today is
performed by digital logic circuits built out of MOSFETs. But MOSFETs (like other electronic
devices) operate on voltages and currents, which are analog quantities. We bridge the gap
between analog and digital by interpreting ranges of voltages as logical values.

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Figure 3.5: Mapping from voltages to logical values.

Voltages between ground and a certain threshold represent the logical value 0. Voltages between
a higher threshold and VDD represent the logical value 1. The threshold levels are design choices.
If a voltage falls in the gap between the defined logical ranges, the result is undefined and there
must be an error in the logic circuit that produced it.
2.2 CMOS LOGIC CIRCUITS
CMOS logic circuits consist of complementary arrangements of NMOS and PMOS transistors.
Complementary metal-oxide-semiconductor (CMOS) technology encompasses a design method
and a set of processes for building reliable and power-efficient digital logic circuits out of NMOS
and PMOS transistors. A CMOS circuit is reliable because its design guarantees that its output is
always shorted to either ground or VDD but not both at the same time. As a consequence, the
design also ensures that VDD is never shorted to ground through Z, which makes CMOS circuits
power-efficient. We now use several examples to illustrate how the NMOS and PMOS transistors
are arranged to provide these guarantees.

Figure 3.6: One-input Not logic circuit.

This circuit (called a CMOS inverter or a NOT logic circuit) takes as input a logical input A and
outputs the opposite logical value Z. Note that the PMOS transistor connects VDD to Z and the
NMOS transistor connects Z to ground. We validate that this circuit inverts the value of A by
checking each input case (i.e. A=0 and A=1) separately in Table 3.2.

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Table 3.2: Operation of a NOT logic circuit given its 2 possible inputs.

2.2.1 CMOS NAND Gate

Figure 3.7: Two-input logic circuit.

This circuit (called a NAND logic circuit) takes two logical inputs A and B. (We draw each of these
inputs at two different locations to simplify the diagram.) Note that the PMOS transistors
(connecting VDD to Z) are in parallel, while the NMOS transistors (connecting Z to ground) are in
series. These complementary configurations of NMOS and PMOS transistors guarantee that Z is
always shorted to either ground or VDD but not both at the same time, as verified in the 4 cases
shown in Table 3.3.

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Table 3.3: Operation of a two-input NAND logic circuit given its 4 possible combinations of inputs.

2.2.2 CMOS NOR Gate Circuit

Figure 3.8: Two-input logic circuit.

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Table 3.4: Operation of a two-input NOR logic circuit given its 4 possible combinations of inputs.

This circuit (called a NOR logic circuit) takes two logical inputs A and B. (We draw each of these
inputs at two different locations to simplify the diagram.) Note that the PMOS transistors
(connecting VDD to Z) are in series, while the NMOS transistors (connecting Z to ground) are in
parallel. These complementary configurations of NMOS and PMOS transistors guarantee that Z is
always shorted to either ground or VDD but not both at the same time, as verified in the 4 cases
shown in Table 3.4.

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2.2.3 COMBINING CMOS LOGIC CIRCUITS

Complex CMOS logic circuits can be analyzed by combining the truth tables of their components.
CMOS AND logic circuit.
CMOS logic circuits can be combined to create more complex circuits, which in turn can be
combined to create even more sophisticated structures.

Figure 3.9: Cascaded CMOS AND logic circuit.

This circuit is the concatenation of the NAND logic circuit in Fig. 3 .7and the NOT logic circuit
in Fig. 3.6. We derive the overall truth table by using Table 3.3 to track inputs A and B to the
intermediate output Y, and then using Table 3.2 to track Y to the output Z. The circuit is called an
AND logic circuit because it turns out that Z=1 if and only if A=1 and B=1.

A B Y Z
0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 5: Truth table for the 2-input AND logic circuit in Fig. 7
‘CMOS OR’ logic circuit.

Figure 3.10: Cascaded ‘CMOS OR’ logic circuit.

This circuit is the concatenation of the NOR logic circuit in Fig. 3.8 and the NOT logic circuit in 3.6.
We derive the overall truth table by using Table 3.4 to track inputs A and B to the intermediate
output Y, and then using Table 3.2 to track Y to the output Z. The circuit is called an OR logic circuit
because it turns out that Z=0 if and only if A=0 and B=0.

A B Y Z
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1

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Ex 1: Implement a two input XOR in CMOS

Sol: 𝐹 = 𝐴. 𝐵̅ + 𝐴̅. 𝐵 = 𝐴 ⊕ 𝐵
F is not complemented and some of the inputs are complemented. We need to do some logic
transformations
̿̿̿̿̿̿̿̿̿̿̿̿̿̿̿
𝐹 = (𝐴. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐵̅ + 𝐴̅. 𝐵) (Expand the 1st complement) --> 𝐹 = (𝐴 ̅ + B) (A + 𝐵̅)

Ex. 2) Implement the following function in CMOS using minimum number of logic levels

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Ex 3) Implement the following function in CMOS using minimum number of logic levels

𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐷 + 𝐴. (𝐵 + 𝐶)

3. BiCMOS or CMBL (Complementary MOS Bipolar Logic Configuration)

BiCMOS is a logic family that combines Bipolar and CMOS devices into single integrated circuits

• Higher speed
• Lower power dissipation
• Higher packing densities
Note that CMOS has an advantage over bipolar in the areas of lower power dissipation, larger
noise margins, and greater packing densities, while bipolar has advantages over CMOS in faster
switching speed and larger current capability

Advantages:

• Lower power dissipation than bipolar

• Improved speed in comparison to CMOS
• Larger current drive than CMOS
Disadvantages:

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• Higher cost
• Larger fabrication time (more mask steps)

3.1 BiCMOS Inverters

3.1.1 Resistive Shunts

• Has full logic swing (0 to Vdd) by the passive resistors R1, R2. However, since uses
resistors, it is not practical
• VOH = Vdd (by R1, M1)
• VOL = 0 (by R1, M2, R2)
• “bleeder resistors” R1 and R2 are added

3.1.2 Active Shunts

Each BJTs have a MOSFET in parallel and does not provide full rail-to-rail swing

• VOH = Vdd – VBEon(Q1)

• VOL = VBEon(Q2)

3.1.3 R-Type BiCMOS

• R1 and R2 form the bleeding path and provide full railto-rail swing
• VOH = Vdd
• VOL = 0

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3.1.4 R-Type (Active) BiCMOS

M3 and M4 must be chosen to be in triode region

Disadvantages

Current ratio in BJT is reduced

3.2 BiCMOS Gates
The basic operation of this gate is described by considering the MOSFETs first, realizing that the
BJTs perform as output buffers
3.2.1 Working of BICMOS NAND GATE

There are many logical families such as RTL, DTL, ECL, CMOS etc.
All have their advantages and disadvantages. However, in the past decade, CMOS is ruling the
electronics field because of its SIZE and POWER.
CMOS(Complementary metal oxide semiconductor) has ZERO static power dissipation. However,
The switching speed of CMOS is very low compared to BJT, and also CMOS cannot drive large
current to the load. In order to drive large current to the load, the size of MOS needs to be
significantly increased.

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This is the two input BICMOS NAND gate. It consists of

1) 2 PMOS PA and PB
2) 4 NMOS, NA1, NB1, NA3, NB3
3) Two BJT's QP and Q0

NAND GATE Logic

VA VB Vout
0 0 1
0 1 1
1 0 1
1 1 0

Case 1 : Both A and B are low.

If both the inputs VA and VB(Refer the circuit) are low(0). PA and PB will be ON and the base of QA
will be high. THus the top BJT(QA) will be ON which pulls the output UP . If there is a capacitive
load. The output current will be almost 101 times the base current i.e it will be 101IB(Assuming
beta of transistor is 100). (if there was no BJT, the output current would be just IB).
Note: PA, PB, NA1 and NB1 are used for logical purposes(Just like in CMOS)
What is the purpose of N2, NB3 and NA3?
For high switching speeds of the BJT's, we need to remove the base charge from the transistor. In
order to remove the charge from the base of the transistor we need a mechanism, that can be
achieved by using these 3 NMOS.
Why to remove the Base charge anyway?
If we do not remove the base charge, the transistor will be in ON state and takes a lot of time to
go to the OFF state. If we do not remove the base charge, the whole purpose of BICMOS is lost.

N2 MOS is getting input from the base of QA transistor. Since the base of QA is HIGH(say 5v), it will
on N2 MOS. Since N2 is ON, it will pull the base charge out of Q0 transistor. So, if both the inputs
are low, QA is ON and Q0 is OFF. Output is high and output current is large. High switching speed.
Case 2 : A and B are high

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NB3 and NA3 NMOS make sure that QA is in OFF state. PA and PB are OFF. NB1, NA1 will be ON. The
output is discharged via NB1, NA1 and Q0.(High Speed). N2 will be effectively out of circuit in this
case. So, Q0 is ON and QP is OFF.
Note: I have discussed 2 cases. You can correlate with the other 2 inputs.
Disadvantages of BICMOS
1) Fabrication cost is high
2) Due to VBE(Base to emitter voltage, 0.7v approximately) of BJT's , desirable performance
is not obtained when the BICMOS gates are operated at lesser voltages (3V, 2.4V) etc.

3.2.2 BICMOS NOR GATE

This is the schematic of BICMOS NOR Gate.

NOR Gate Logic

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

1) When both A and B are 0. Both the PMOS will be ON. The base of Q1 will be VDD , say 5v. The
base of Q1 is also connected to the GATE of bottom NMOS. So, bottom NMOS is ON and it removes
the base charge of Q2, if any and makes sure that Q2 is OFF. when A=0, B=0, Q1 is ON and Q2 is
OFF.

BICMOS NOR GATE has characteristics of both CMOS and BJT’s. CMOS have ZERO STATIC POWER
DISSIPATION and BJT's have HIGH TRANSCONDUCTANCE (High speed logic families). Also, BJT's
have large current driving capability.
2) For other permutations of input. For other inputs, the BASE charge of Q1 is removed by the 2
NMOS. The bottom NMOS is off and the output is pulled to Zero.

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Note: CMOS is by far, the best logic family. CMOS have zero static power dissipation, but BJT's
are still imperious in terms of Speed. ( ECL , still stands top as the high speed logic family). BJT's
also have a large current driving capability, which MOSFET doesn't have. In order to have same
current driving capability of that of BJT's , MOSFET SIZE needs to be significantly increased.

In order to incorporate both the advantages of CMOS and BJTs, BICMOS has been
invented(Discovered, more aptly). Still, it involves lot of mess to fabricate BICMOS. Nevertheless,
BICMOS is one of the important logic family.

3.3 BiCMOS Drivers

BJTs are used to drive output nodes. There are four types of drivers
Common Collector NPN-PNP
Gated Diode
Emitter Follower
Modified Gated Diode
In each circuit, MOSFETs are used as switches to supply base current to the BJTs
3.3.1 Common Collector NPN-PNP (Collectors are in Common)
➢ A = 0, NMOS is off and PMOS is on
➢ NPN to be cutoff and PNP to be in saturation
➢ Y = Vdd – VEC(sat) = VOH
➢ A = Vdd, NMOS turns on and PMOS turns off
➢ PNP = Off , NPN = Sat. Y = VCE(sat) = VOL

Swing is less than rail-to-rail

PNP and NPN saturate, the switching speed from output low to high is reduced
If PNP and NPN are replaced with schottky BJTs, this switching time is improved
Static power dissipation is also exist
3.3.2 Gated Diode

• It is an improved driver
• Each MOSFET acts as a switch between the base and collector of the BJTs. When the
switch is on, the corresponding BJT becomes a diode

A= 0 => M1=off , M2=on, Q2=active, Y= Vdd-VBEON

A = Vdd => M1=on, M2=off , Q1=active, Y= VBEON

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3.3.3 Modified Gated Diode

o This circuit has two additional NMOS transistors ++(M2,M3) that provide a
discharge path for the base current of the output BJTs
o M2 discharges Q2 when output High
o M3 discharges Q1 when output Low
Note: Output is inverted of Input

3.3.4 Emitter Follower

Emitter Follower-Each MOSFET operates as an inverter

• Has no body effect (why=?)

• Each MOSFET-BJT pair can be merged into a compact structure that uses less chip
area (using common region for the base of the BJT and drain of the MOSFET)

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Static CMOS Pseudo- Dynamic logic Pass Transistor

NMOS Logic
Easy to design Simple and fast Potentially fast and compact Attractive for some
specific circuits
Robust in presence of Reduced noise Difficult to design • e.g., MUX, XOR-
noise margin (monotonicity,leakage,noise, dominated logic like
More amenable to Static power clocking, etc.) adders
voltage scaling dissipation
Expensive in terms of
performance and area

3.4 BiCMOS Applications

• Modern BiCMOS, invented by Intel, hit the market in 1992.

• Ever-increasing clock frequencies on motherboards of PC’s and workstations may
require that the VLSI / ULSI chips be made in BiCMOS. (Witness the Intel, AMD, and Cyrix
mP chips.)
• Central Processing Units (CPU’s) of “minisupercomputers” can be implemented in
BiCMOS, with packing density and dissipation advantages over ECL. (e.g., the Cray
Research “Baby Cray” J916 Computer)
• TTL will soldier on in motherboard SSI and MSI applications, where BiCMOS does not
boast an advantage.
• But … the BiCMOS party may be over when supply voltages drop below 1.8 V. BJT’s have
a fixed turn-on voltage; MOSFET thresholds can be reduced to at least 0.3V for room
temperature operation.
The Problem with BiCMOS

• For standard BiCMOS, the logic swing is VDD - 2VBEA.

• Supply voltages are continually being reduced, because
P = CLVDD2
• When VDD is reduced to 1.8V, standard BiCMOS will provide a logic swing of only 0.4V; this
isn’t acceptable! We can provide shunt elements which increase the voltage swing of BiCMOS,
but…
• Turning off the BJT’s isn’t the answer! If the supply voltage is 1.8V, the BJT’s can only conduct
for
0.7V ≤ Vout ≤ 1.1V
• In this case the BJT’s can not effectively boost the switching speed.
3.5 Comparison between CMOS Technology and Bipolar Technology

CMOS Technology Bipolar Technology

• Low Static power dissipation • High power dissipation
• High input impedance • Low Input Impedance
• Scalable threshold voltage • Low volatage swing Logic
• Hign Noise margin • Low packing density
• High packing density • High gm (gm α eVin )
• Low gm (gm α Vin ) • High Drive current
• Low out put drive current • High Speed
• High gain
• Low out put resistance

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3.6 Performance Evaluation

• Self cap of CMOS leads to slow circuits

• Bipolar transistor parasitics don’t scale as badly as CMOS

• But BiCMOS consumes more power

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