50 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO.

1, FEBRUARY 2006

Interconnect Capacitance Characterization Using

Charge-Injection-Induced Error-Free (CIEF)
Charge-Based Capacitance Measurement (CBCM)
Yao-Wen Chang, Hsin-Wen Chang, Tao-Cheng Lu, Ya-Chin King, Wenchi Ting, Yen-Hui Joseph Ku, and
Chih-Yuan Lu, Fellow, IEEE

Abstract—In this work, we describe a novel operation of
charge-injection-induced error-free charge-based capacitance
measurement (CIEF CBCM) method. This method has the sim-
plest test structure among various CBCM methods by using only
one N/PMOS pair. CIEF CBCM has the advantage of being free
from charge-injection-induced errors and of efficient layout area
usage. It is very suitable for industrial applications for large
amounts of accurate capacitance characterizations with a limited
layout area. Besides, CIEF CBCM is also implemented for inves-
tigating the impact of floating dummy metal fills on interconnect
capacitance directly from silicon data.
Index Terms—Capacitance measurement, charge-based ca-
pacitance measurement (CBCM), charge injection, interconnect
capacitance.
I. INTRODUCTION
HARGE-BASED capacitance measurement (CBCM) was
C first proposed in 1996 to characterize on-chip interconnect
capacitance with sub-femto-farad resolution [1]. It receives
more and more attentions because the intermetal capacitances
have become a significant factor in the design of fast chips.
Accurate characterization and modeling of interconnect ca-
pacitance are essential now for successful circuit design [2],
[3]. Following the concept of CBCM, the single pattern driver
(SPD) method [4] was proposed, which is free from errors
caused by mismatch issues and allows all the coupling capaci-
tance extractions. However, errors from charge injection always
exist and limit the resolution of CBCM methods [4]. To reduce
the impact of charge injection, an improved CBCM scheme [5]
employing pass gates was proposed. The errors resulting from
charge injection are suppressed but still exist. Following that, an
improved CBCM method, charge-injection-induced error-free
(CIEF) CBCM method was proposed [6]. It is completely free
from the errors induced by charge injection and more suitable
for the extractions of interconnect capacitances.
In this paper, the operation of CIEF CBCM and its special
advantage of freedom from the charge-injection-induced er-
Manuscript received July 19, 2005; revised October 10, 2005.
Y.-W. Chang is with the Macronix International Co., Ltd. no. 16, Hsinchu
300, Taiwan, R.O.C and also with the Institute of Electronics Eng., National
Tsing-Hua University, Hsinchu 300, Taiwan, R.O.C. (e-mail: wenchang@mxic.
com.tw).
H.-W. Chang, T.-C. Lu, W. Ting, Y.-H. J. Ku, and C.-Y. Lu are with the
Macronix International Co., Ltd. no. 16, Hsinchu 300, Taiwan, R.O.C.
Y.-C. King is with the Institute of Electronics Eng., National Tsing-Hua Uni-
versity, Hsinchu, Taiwan 300, R.O.C.
Digital Object Identifier 10.1109/TSM.2005.863228
rors are first discussed. Next, its efficient layout structure is
demonstrated, making CIEF CBCM very suitable for indus-
trial applications. Large amounts of experimental results for
backend process monitoring within a limited layout area can
be achieved. In the fourth section, the example exploring the
impact of dummy metal fills in CMP process on interconnect
capacitances is demonstrated [7]. The final section includes
in-depth discussion on the optimization of the chip performance
and minimization of the crosstalk by suitable dummy pattern
design.
II. OPERATION OF CIEF CBCM
The test structure of CIEF CBCM comprises an N/PMOS pair
in a pseudoinverter configuration and they are driven by two
nonoverlapping signals and , as shown in Fig. 1. The
capacitance under test is placed between the output of
the inverter and one probe pad, to which a controlled pulse or a
fixed bias voltage can be directly applied. The capacitance can
be extracted by the two-step operations of CIEF CBCM. At the
first step, we force the probe pad to ground. At this step, not only
the capacitance under test, but also all the parasitic capacitances
at the output node are charged and discharged between
and ground repeatedly. The charging current through pMOS
is expressed as
(1)
where is the frequency of the nonoverlapping clock signals.
At the second step, we apply a controlled pulse to the probe
pad as shown in Fig. 1. The pulse rises up from ground to
before pMOS is turned on. When pMOS is turned on ,
the output node is pulled up to . There will be no charges at
both sides of because there is no voltage drop on it. Next,
before nMOS is turned on to discharge the output node to
ground, the controlled pulse falls down to ground to keep no
charges at both sides of the capacitance. Thus, only the current
that charges up the parasitic capacitances is recorded as
(2)
Under such operations, can then be extracted by sub-
tracting from as shown in (3)
(3)

0894-6507/$20.00 © 2006 IEEE

CHANG et al.: INTERCONNECT CAPACITANCE CHARACTERIZATION USING CIEF CBCM 51

Fig. 1. The proposed CIEF CBCM structure and the bias setup in two-step measurement. The dashed line shows the applied bias at the probe pad in the first step
and the solid line shows the applied bias in the second step.

Fig. 2. The simulated charge-injection-induced errors versus C for the

conventional CBCM, SPD, and CIEF CBCM.

In conventional CBCM operations, charge injection, which

always occurs at the transition when the MOSFET transistors
are turned off [8], will cause the inevitable errors and limits the
resolution of conventional CBCM methods. There will be un-
wanted flowing-back currents during the turnoff transitions and
the currents depend on the capacitance at the output node of
the pseudoinverter. In conventional CBCM and SPD, the ca-
pacitances are not the same at each operation step. Therefore,
the flowing-back currents are different, which then induces the
errors. We emulate the operations of conventional CBCM and
SPD methods in SPICE simulator and Fig. 2 shows the simu-
lated errors that result from charge injection. It shows that the
errors increase with the decreasing capacitance under test. But
in CIEF CBCM operation, the capacitance at the output node is
Fig. 3. (a) The layout arrangement of CIEF CBCM for single capacitance ex-
always the same at two steps. The only difference is the bias traction. In total, 20 capacitances can be extracted by sharing one pseudoinverter
applied to the pad is ground at the first step and at the in one 24-pad spine. (b) The layout arrangement of CIEF CBCM with multielec-
second step when pMOS switches off. It makes no difference on trode pattern. There are three intermetal capacitances can be extracted in one
multielectrode pattern. Eighteen sets of pseudoinverters driving the same mul-
charge injection behavior because they both are dc bias during tielectrode structures are put in one 24-pad spine and, in total, 54 capacitances
this phase. As a result, the charge-injection-induced currents can can be extracted.
be completely canceled out so that no errors will be generated.
Ideally, CIEF CBCM shows the perfect results and is with accuracy as small as picoampere under the measurement
completely free from the errors induced by charge injection. system, attofarad resolution can be achieved when CIEF CBCM
However, in practice, the limitation of the measurement system is operated under frequency of megahertz range. Besides, there
would limit the resolution of the method. If we can get current might be additional errors due to the small differences in the
52 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006

Fig. 4. Diagram of CIEF CBCM structure driving a multielectrode pattern. The pattern has three M1 lines sandwiched by M2 and poly plates. The central M1
line is driven by the pseudoinverter of CIEF CBCM, and the neighboring M1 lines, the top M2 plate, and the bottom poly plate are connected to the probe pads
respectively.

potentials on both sides of in the second step, which can

be eliminated by careful calibrations of the added pulse.

III. EFFICIENT LAYOUT STRUCTURE AND

EXPERIMENTAL RESULTS
CIEF CBCM, using only one pair of pseudoinverters, is the
simplest one among various CBCM methods. With the pseu-
doinverter shared, only one probe pad is needed for each ad-
ditional capacitance characterization as shown in Fig. 3(a). By
CIEF CBCM, we can extract 20 different interconnect capaci-
tances in one 24-pad spine. The conventional CBCM and SPD
both need additional two probe pads for each additional ca-
pacitance. CIEF CBCM occupies the least layout area and is
Fig. 5. The measured coupling capacitances of the central M1 lines to the
the most efficient method for interconnect characterization and neighboring M1 lines, to the top M2 plate, and to the bottom Poly plate, versus
process monitor. . overlapped length with fixed spacing of 0.32 m
the
The efficiency can be further enhanced when CIEF CBCM
is used to characterize the cross-coupling capacitances in mul-
tielectrode structure. That is, the structure has more than two
electrodes and there is more than one intermetal capacitance
that can be extracted. Fig. 4 shows our experimental multielec-
trode structure under CIEF CBCM connection fabricated by
three-metal-layer 0.13- m Flash technology. The structure has
three M1 lines sandwiched by M2 and poly plates. The width of
M1 lines is designed as 0.32 m and the spacing between M1
lines ranges from 0.32 to 5 m. Besides, the overlapped length
is changed from 5 to 50 m. The central M1 line is driven by the
pseudoinverter of CIEF CBCM, and the neighboring M1 lines,
the top M2 plate, and the bottom poly plate are connected to the
probe pads, respectively. Thus, three intermetal capacitances in Fig. 6. The measured coupling capacitances of the central M1 lines to the
the same structure by CIEF CBCM operations can be extracted. neighboring M1 lines, to the top M2 plate, and to the bottom Poly plate, versus
They are the coupling capacitances from the central M1 line to the spacing with fixed overlapped length of 50 m.
the neighboring M1 lines, to the top M2 plate, and to the bottom
poly plate respectively. Except three common pads for , Fig. 5 shows these three capacitances versus the overlapped
and ground, if we arrange multiple CIEF CBCM structures as length with fixed spacing of 0.32 m; and Fig. 6 shows these
shown in Fig. 3(b) by connecting all neighboring M1 lines to capacitances versus the spacing with fixed overlapped length of
pad E1, all M2 plates to pad E2, and all poly plates to pad E3, 50 m. Fig. 5 indicates that all these capacitances show good lin-
in total 18 sets of pseudoinverters driving the similar multielec- earity with the overlapped length and there are always positive
trode structures can be put in one 24-pad spine. A total of 54 y-intercepts, which should come from the fringing capacitors at
capacitances from only one spine can be extracted. It is very ef- edges of the parallel lines. In Fig. 6, the coupling capacitance
ficient and suitable for industrial applications to collect a large to the neighboring M1 lines decreases with increasing spacing.
amount of silicon data without occupying a large layout area. But the capacitances to the top M2 plate and to the bottom poly
CHANG et al.: INTERCONNECT CAPACITANCE CHARACTERIZATION USING CIEF CBCM
Fig. 7. Structure having three parallel M2 lines above one poly line
with dummy M1-fills filled. The width/length/spacing of the M2 lines are
5 m=150 m=1 m. The poly line is right below the central M2 with the
same size.
Fig. 8. Three different dummy-fill patterns with each block having dimen-
sion of 5 m by 10 m. (a) Basket-weave type. (b) Perpendicular alignment
with dummy-fills right under the central M2 line. (c) Perpendicular alignment
without dummy-fills under the central M2 line.
plate increase inversely with increasing spacing. All these ca-
pacitances are extracted from the test patterns in one spine only.
IV. INVESTIGATION INTO THE IMPACT OF FLOATING
DUMMY-FILLS ON INTERCONNECT CAPACITANCE
With the help of CIEF CBCM, we can characterize the
interconnect capacitances directly from silicon when increas-
ingly complex backend process is adapted, which could not be
implemented easily in the past. Next, the impact of floating
dummy-fills on interconnect capacitances is investigated using
CIEF CBCM. In the chemical–mechanical polishing (CMP)
process, in order to control the uniformity of interlayer di-
electrics, the dummy-fills have always been used [9], [10]
and they would affect the interconnect capacitances more or
less [10]–[12]. It may result in a speed performance different
from designer’s expectation. Fig. 7 shows our experimental
structures with three parallel M2 lines above one poly line,
which are fabricated by the same three-metal-layer 0.13- m
Flash technology. All these four conductor lines are 5- m wide
and 150- m long. The spacing between M2 lines is 1 m.
Among these conductors, three different patterns of floating
dummy M1-fills are filled as shown in Fig. 8(a)–(c). Each block
53
Fig. 9. SEM picture of the backend profile. This is the region with dummy-M1
fill. The thickness of M1 is 7600 
A; the thickness of IMD (including M1) is
14 500 A; and the thickness of M2 is 6500 A.
Fig. 10. Measured and simulated overlapping capacitances of the structures
with different dummy-fill patterns.
of dummy fill is 5 m by 10 m. Pattern A is the basket-weave
type, which is the suggested pattern to minimize the variations
of the capacitances coming from floating dummy-fills [10]
and is the default pattern in this process. Pattern B and C are
both the cases of perpendicular alignment. In pattern B, one
line of M1-fills are directly under the middle M2 line; but in
pattern C, oppositely, there are no M1-fills under the middle
M2 line. In addition, the structure without any dummy M1-fill
is also added and compared. The thickness of intermetal di-
electric (IMD) between M1 and M2 layers can be gotten from
a scanning electron microscope (SEM) picture (Fig. 9) for
simulation purpose. The thickness of IMD layer is the same
with or without dummy-fills because it is only a small region
to block the filling of dummy-fills. Fig. 10 shows the extracted
overlapping capacitances of the central M2 line to the poly line
and Fig. 11 shows coupling capacitances to the neighboring M2
lines. Also shown in the figures are the simulated interconnect
capacitances by Raphael [13]. The simulation results correlate
to the measurement well and show the same trends among
structures with different dummy-fill patterns.
Fig. 12 shows the capacitance differences of coupling capaci-
tance, overlapping capacitance, and the total capacitance, which
is the sum of the former two components. The capacitances in
the structures with pattern B, pattern C dummy-fills, and without
dummy-fills are compared to those in the structure with pattern
54 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006
Fig. 11. Measured and simulated coupling capacitances of the structures with
different dummy-fill patterns.
Fig. 12. Capacitance changes of the structures with pattern B, C, and no
dummy-fills, compared to that with pattern A.
A dummy-fills. We can find that when there are no dummy-fills,
the total capacitance and coupling capacitance are lower by 10%
and 20%, respectively. In other words, if the impact of floating
dummy-fills is not considered in the circuit design, designers
may seriously underestimate the delay and crosstalk. When pat-
tern B dummy-fills are used instead of pattern A, the overlap-
ping capacitance increases by about 28% because the dummy
M1-fills are right below the central M2 line and enhance the ca-
pacitance increment. At the same time, the coupling capacitance
drops off more than 10% is observed.
V. DISCUSSION
The above characterization results suggest that the floating
dummy-fills indeed play an important role on interconnect
capacitance. And it seems that the improvement of the circuit
performance can be expected by choosing suitable dummy-fill
pattern. Through simulations of the same structures with dif-
ferent M2 widths from 1 to 5 m, and spacing from 0.5 to
2.5 m, we can demonstrate the effects in more details. Com-
pared to the structure with pattern A, both total capacitances
and coupling capacitances can be effectively reduced by
blocking the filling of the dummy-fills as shown in Fig. 13(a)
and (b). And the capacitance reductions enlarge with increasing
M2 width and spacing. Thus, if blocking the insertion of
dummy-fills within a limited region is allowed, it is the most
effective way to reduce the interconnect capacitances and
enhance the circuit speed. If blocking the filling of dummy-fills
is not allowed, pattern B dummy-fills may be also effective to
reduce the coupling capacitances as shown in Fig. 14(a). It may
Fig. 13. Simulated capacitance changes of: (a) coupling capacitances and
(b) total capacitances in the structure without dummy-fills, compared to those
in the structure with pattern A dummy-fills. Simulations are done using the
structures with different M2 widths from 1 to 5 m, and spacing from 0.5 to
2.5 m.
Fig. 14. Simulated capacitance changes of: (a) coupling capacitances and (b)
total capacitances in the structure with pattern B dummy-fills, compared to those
in the structure with pattern A dummy-fills. Simulations are done under the
structures with different M2 widths from 1 to 5 m, and spacing from 0.5 to
2.5 m.
be helpful if there is a signal line very sensitive to the crosstalk
from neighboring conductor line. The cost is only slight total
capacitance increment as shown in Fig. 14(b). Nevertheless,
when the M2 lines are as narrow as 1 m, the neighboring
M2 lines are almost right above the dummy-fills. The floating
dummy-fills would redirect some of the electric force lines
back to the neighboring M2 lines rather than direct almost all
the electric force lines to the bottom poly line. As a result, the
overlapping capacitances do not increase as expected and the
coupling capacitance reductions are not so significant.
VI. CONCLUSION
In this work, we describe the operation of CIEF CBCM
method and its special advantage of freedom from the errors
induced by charge injection. Also, its superb efficiency for
large amounts of capacitance characterizations within a limited
layout area is demonstrated. Both benefits make CIEF CBCM
the best solution for industrial applications to characterize
the interconnect capacitances under different environments or
to monitor the variations of backend process. Also, with the
help of CIEF CBCM, a complete investigation of the impact
of the floating dummy-fills on interconnect capacitances is
CHANG et al.: INTERCONNECT CAPACITANCE CHARACTERIZATION USING CIEF CBCM
performed. It is confirmed directly from silicon that the impact
is very significant and it could play an important role for
successful circuit designs. To optimize the chip performance
and minimize the crosstalk, dummy pattern design should be
carefully considered combining the circuit functionality and
interconnection routing environment.
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[13] Raphael Reference Manual, Avant! Corp..
Yao-Wen Chang was born in Kaohsiung, Taiwan,
R.O.C., in 1972. He received the B.S and M.S. de-
grees in electrical engineering from National Taiwan
University, Taipei, Taiwan, R.O.C., in 1994 and
1996, respectively. He is currently working toward
the Ph.D. degree at National Tsing-Hua University,
Hsinchu, Taiwan, R.O.C.
In 1998, he joined Macronix International Co. Ltd.
(MXIC), Hsinchu, and has been with the Device En-
gineering Department, where he has engaged in MOS
device characterization and modeling, interconnect
capacitance characterization, high-voltage device modeling, and RF CMOS de-
vice modeling.
55
Hsin-Wen Chang was born in Taichung, Taiwan,
R.O.C., in 1976. She received the B.S. degree in
physics from National Normal University, Taipei,
Taiwan, R.O.C., in 1998, and the M.S. degree
in physics from National Tsing-Hua University,
Hsinchu, Taiwan, R.O.C., in 2002.
In 2002, she joined Macronix International Co.,
Ltd. (MXIC), Hsinchu, Taiwan, R.O.C., and has been
with the Device Engineering Department, where she
has engaged in MOS device characterization and
modeling, interconnect capacitance characterization,
and high-voltage device modeling.
Tao-Cheng Lu was born in Taiwan in 1967. He
received the B.S., M.S., and Ph.D. degrees in elec-
trical engineering from National Taiwan University,
Taipei, Taiwan, R.O.C., in 1989, 1991, and 1993
respectively.
He joined the Macronix International Co., Ltd. in
1995, Hsinchu, Taiwan, R.O.C., where he engaged
in the simulation and modeling of CMOS and
nonvolatile memory devices. From 1997 to 1999,
he set up the electrostatic discharge (ESD) group
in the device department and became the manager
of the device department in 2000. Currently, he is the Deputy Director of
the Device Technology Division and is in charge of process/device simula-
tion, device modeling, ESD/latchup, and nonvolatile memory device design,
including the development of nitride trapping storage flash devices. He has
published more than 40 papers in technical journals and conferences and has
authored and coauthored more than 70 U.S. patents. His research interests
include device/flash cell reliability and scaling, device modeling, interconnect
capacitance measurement and modeling, and on-chip ESD protection.
Ya-Chin King was born in Taiwan. She received the
B.S. degree in electrical engineering from National
Taiwan University, Taipei, Taiwan, R.O.C., in 1992,
and the M.S. degree in electrical engineering and
the Ph.D. degree in thin oxide technology and novel
quasi-nonvolatile memory from the University of
California, Berkeley, in 1994 and 1999, respectively.
She joined the faculty of National Tsing-Hua Uni-
versity (NTHU), Hsinchu, Taiwan, R.O.C., in 1999.
She is currently an Associate Professor in the Elec-
trical Engineering Department, NTHU. Her research
topics include advance gate dielectric, CMOS image sensor, and nonvolatile
memory design.
Wenchi Ting received the Ph.D. degree in electrical engineering from the Uni-
versity of Texas, Austin.
He is currently a Senior Director at Macronix International Company,
Hsinchu, Taiwan, R.O.C., focusing on developing silicon-nitride trapping
based nonvolatile memory processes. His research interests include developing
SRAM, EPROM, EEPROM, Flash, and embedded Flash technologies.
Yen-Hui Joseph Ku received the B.S. degree in
electrical engineering from National Cheng-Kung
University, Tainan, Taiwan, R.O.C., in 1979, and the
M.S. and Ph.D. degrees in electrical and computer
engineering from the University of Texas, Austin, in
1983 and 1988, respectively. His research was on the
self-aligned silicide and shallow junction formation
for deep submicrometer device application.
In 1987, he joined Rapro Technology, Fremont,
CA, as a cofounder with the responsibility on
RTPCVD reactor design and process development.
56 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 19, NO. 1, FEBRUARY 2006
From 1991 to 1992, he was with Paradigm Technology, San Jose, CA, where he
worked on 0.35-m 4-Mb SRAM technology development. In 1992, he joined
LSI Logic, Santa Clara, CA, where he worked on the advanced logic technology
development and served as integration manager of the R&D Division until
1997. He later joined the Technology Development Division of the MXIC,
Hsinchu, Taiwan, R.O.C. He currently leads the Technology Development
Center and is responsible for the development of advanced nonvolatile memory
and embedded SOC technologies. He has published more than 40 papers in
technical journals and conferences.
Chih-Yuan Lu (M’78–SM’84–F’95) received the
B.S. degree from National Taiwan University, Taipei,
Taiwan, R.O.C., in 1972 and the Ph.D. degree in
physics from Columbia University, New York, in
1977.
He was a Professor at National Chiao-Tung
University and with AT&T Bell Labs from 1984
to 1989. He later joined ERSO/ITRI in 1989 as a
Deputy General Director responsible for the MOEA
grand Submicron Project. This project successfully
developed Taiwan first 8-in manufacturing tech-
nology with high-density DRAM/SRAM. In 1994, he became the cofounder
of Vanguard International Semiconductor Corporation, which is a spin-off
memory IC company from ITRI’s Submicron Project. He was the Vice Presi-
dent of Operations, Vice President of R&D, and later President from 1994 to
1999. He is now the Chairman and CEO of Ardentec Corp., Hsinchu, Taiwan,
R.O.C., a very large scale integration (VLSI) testing service company; and also
serves Macronix International, Hsinchu, as a Senior Vice President/CTO. He
led MXIC’s technology development team to successfully achieve the state
of the art nonvolatile memory technology and now responsible for MXIC’s
overall memory operation. He has published more than 100 papers and has
been granted 123 international patents.
Dr. Lu is a Fellow of the American Physical Society. He was granted the
highest honor prize—the National Science and Technology Achievement Award
by the Prime Minister of Taiwan, due to his leadership and achievement in
the Submicron Project. He also received the IEEE Millennium Medal and the
most prestigious semiconductor R&D award in Taiwan from Pan Wen Yuan
Foundation.