Proc. IEEE 1994 Int.

Conference on Microelectronic Test Structures,Vol7, March 1994 130

New Test Structures for On-Chip Absolute and Accurate
Measurement of Capacitances in a CMOS Process

A. Khalkhal, P. Girard and P. Nouet

Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM)
U.M.R. 9928 UNIVERSITE MONTPELLIER I1 / CNRS
161 Rue ADA, 34392 MONTPELLIER Cedex 5, FRANCE.
Tel: (+33) 67.41.85.27 Fax: (+33) 67.41.85.00 E-mail: nouet@lirmm.fr

Abstract - A new on-chip capacitance measurement technique is PRINCIPLE

presented. Since no reference devices are required, it allows the
absolute determination of constant capacitances and matching
errors are greatly reduced. The test structure can be easily scaled to
any CMOS process and can be used with unstable or not totally
characterized processes. Experimental results show an accuracy
better than 5 % and a resolution of about .1 % for capacitances
varying from 4 up to 135 E.
OF THE METHOD
In order to measure On-Chip capacitances, we use the derivative
properties of a capacitor: when a voltage varying linearly with time
(V, = a . ( t - to )) is applied to a capacitor C,a constant current
equal to Ii, = a.& is induced, where a is the slope of the input
voltage. An integrated CurrentNoltage (IN) converter is used to
detect the induced current (Figure 1).

If Ri, and G, are respectively the input resistance and the input
capacitance (including any stray capacitances at the On-Chip node)
of the converter, the input current is given by:
INTRODUCTION

Design simulation requires a precise knowledge of elementary

device parameters. Especially for high speed CMOS circuits,
inter-layer stray capacitances can drastically reduce the final circuit
performances.
Direct measurement of capacitances generally leads to the study
of either a large network of devices connected in parallel or a large
dimension device. Consequently, experimental data are only a
statistical information on the average behavior of the considered
population [l].
Up to now, on-chip measurement techniques require a reference
element (generally a capacitor [2,3,4]) or a reference test structure
(without the studied device[5]). Both of these approaches lead to
matching errors which can only be evaluated in a statistical way.
The new technique presented in this paper allows the absolute
determination of capacitances. The electrical principle and
implementation on silicon are first presented. Next, the
experimental set-up is described and experimental results are given
and discussed. We conclude with a brief recall of the interest of this
method.
The time constant of this circuit is z = R, (C, + C,). This time
constant is independent of the stray capacitance due to external
wiring. For t > to + 7 z, a pseudo-static state is reached.
Assuming that the transfer characteristic of the converter
(Vout=f(Iin))is known, the capacitance can be deduced from the
measurement of both output voltage magnitude (V& and input
voltage slope (a).
Since the total amount of stray capacitances drastically affects
the time required to establish the pseudo-static state on the
insulated node, the induced current has to be sensed with particular
care. With a stronglydisymmetricsawtooth-shaped input signal, the
period (T) must be chosen in order to eliminate the effect of Gn,i.e.
T > 10.1. Then, the pseudo-staticvalue of the current only depends
on the capacitance serially connected between the input of the
converter and the input of the test structure.
IMPLEMENTATION
ON SILICON
Test Structures have been designed using a Dual Layer Metal 1.5
pm N well CMOS industrial process. They could be easily
implemented in any other CMOS process.

Studied Capacitors
In order to validate the previous principle, eight test structures
have been used to characterize constant or biasing dependent
capacitances.

Y Ci, ; Ri, < I

Constant capacitors (test structures 1to 5 in Table 1) are built
between first metal layer and polysilicon layer. Several geometrical
dimensions have been used to obtain various magnitudes of the
perimeter-to-area ratio. Biasing dependent capacitances ( test
structures 6 to 8) are MOS transistor gate-to-bulk ones with a
Figure 1: Basic principle of the new capacitancemeasurement different width-to-length ratio. Table 1recalls the characteristics of
technique. each capacitor.
94CH3380-3
131

I I Metal 1 Polysilicon Gate 1 Bulk

characteristic (calibration step) and to measure the induced current
(measurement step).

The whole Test Structure (Figure 3) is connected with at least two

I I I U
1 and the converter output) must be dedicated to a single test
Table 1: Implemented capacitor dimensions.
external input terminals. The first one is a static input (Istat,)used to
calibrate the converter and the second one is a dynamic input (Idyn.)
used to induce the pseudo-static current. A control input (Ictr[)
selects one of the two modes of operation, i.e. the converter
calibration and the capacitance measurement mode, via a MOS
transistor used as a transmission gate. Among the external
terminals of the test structures, only two of them (the static input
l I J
structure. The others can be common to all test structures of a chip
(or a PCM).

The Current I Voltage Converter

SET-UP
EXPERIMENTAL
The Open-Loop On-Chip Current to Voltage converter has been
designed with the following constraints: Experiments have been carried out with the following
equipment:
- the converterhas to be process tolerantand the same converteris used
for differentcapacitances(it can be tuned whatever the MOS parame- - Semiconductor Parameter Analyzer (HP 4145B) to provide accurate
ters and the induced current magnitude), current sources,
- the output must be able to drive a 100 pF - 1 MSZ load for frequencies - PulseFunction Generator (HP 8116A),
up to 100 kHz (input signal period up to 10 ps). - Oscilloscope (HP 54501A).

vdd2 Vdd vdd

After an estimated value of C, has been used to determine the
input signal V,, (i.e. the slope a = -
AV ) and the corresponding
T T T At
current (I,, = a Cx), capacitance measurements are achieved in
two main steps.

Calibration Step
During this step, the transmission gate is kept in the on-state and
a DC current is injected in the converter via the static input (Istat,).
-
- -
Figure 2: On-chip CurrentNoltage converter (with MOS transistor
dimensions WL).

To achieve these features, a double power supply and a buffered Istat.

output have been used (Figure 2). With suitable Vd&7values(Vdd is
5 volts) the converter transfer characteristic can be tuned on input
currents in the 1, 10 or 100 nA range (see Experimental Set-Up I-v
section). converter -,-
I Gout i Rout ,
-
- -
A
- A
-
- -
-
A

Figure 4:Electrical diagram of the Test Structure during the

calibration step.

On Figure 4, the electrical modelling of the Test Structure during

this step is given. represents the total capacitance of the
converter input node. Since IOis a DC current generator, the
magnitude of this capacitance does not affect the transfer
characteristic of the converter.

This step allows vda tuning and transfer characteristic (

Figure 3: Electrical diagram of the whole Test Structure.
The whole Test Structure
For the purpose of accuracy (reduction of matching errors), the
same converter must be used to determine the transfer
Vout=f(Iin)) recording. The experimental procedure is as follows:
IOis first injected in the converter via the static input and Vdd2 is
adjusted in order to obtain a mid range magnitude ofVOut(from 1up
to 4 Volt), then, Vdd2 is kept constant and the transfer characteristic
is recorded with input current sweeping (Figure 5). It is shown that
the same converter can be easily adapted in a large range of currents
(from 1 up to 100 "A) using different values of Vdd2.
 132

vout (v) needed to reach the pseudo-static state, the slope of the input signal
is negative.

E I E l
00 0.5 1.o 1.5 Ii, (nA)
EXPERIMENTAL

Results and dispersions

RESULTS

49
vout (v)
The study of constant capacitances has been led on five metal -
polysilicon capacitors with different geometrical dimensions (test
2 structure 1 up to 5 in Table 1). Experimental results reported on
Table 2 correspond to more than one hundred measurements for
each capacitance. The average measured value (C,), typical
0 50 100 150 Ii,(nA)
variation from average value (AC,), scattering factor (-)ACx and
Figure 5: Experimental transfer characteristics (Voutvs. Ii,) of the W
cx
relative variation between measured and expected values
converter in the 1 and 100 nA range.
c x -c
( c e) are given for each test structure with:
,
Measurement Step

vdd2
'I
where n is the number of measurements and C,(i) the measured
value at round i.

i Cs
7

iCi,
converter -,-
CO,, i %ut
2,
* *
I I

-
* - L
I

1
I

Figure 6: Electrical diagram of the Test Structure during the 2 95.8 73.8 1.7 2.3 - 23
'
measurement step.
I
3 1.63 5.88 .14 2.38 I - 22.9
I
The transmission gate is kept in the off-state and the current is 4 5.48 4.23 .08 1.89 - 22.8
injected in the converter via the dynamic input (Idy.) and C, 5 167.45 129.1 3.3 2.56 - 22.9
(Figure 6). The pseudo-static value of Vout( when
dt
= 0 ) is 5 Table 2: Metal - Polysilicon capacitances.Comparison between
measured. Then, using the previously determined transfer expected (C,) and measured (C,) values.
characteristic, it leads to the determination of IO and C, = 4. On the one hand, this table allows us to conclude on the good
accuracy of the method (the scattering factor is very low). On the
other hand, the reduction of about 23 % between expected and
measured capacitances shows that up to now, interconnection
capacitances have not been very well characterized. This is
;
-5
particularly annoyingwhen processing post-layout simulations (the
electrical description of the circuit is extracted from the layout and
all parasitic elements are taken into account) of high frequency
0 100 200 Time(ps) Integrated Circuits.
vout (VI
In the followingsections,we first discuss accuracy and resolution.
Then, modelling of such a capacitance is proposed.

59
00 100 200 Time(p)
Figure 7: Input and output waveforms are reported versus time.
Discussion on Accuracy and Resolution
Measurement errors are due to three main error sources: the
matching error, the current control error and the slope
measurement error. These errors can be estimated in order to
conclude on the accuracy of the method.
On Figure 7, typical input and output waveforms are reported in
the case of a 6 fF metal - polysilicon capacitance with an input signal Matching error: if the output voltage (Vout)can be measured
slope of .1 V / p when the output is loaded with 10 pF - 10 M a
(probing system of an oscilloscope). Due to the sign of the current with an accuracy of &AV it comes AI, =2
% x AV, where is
dVmt a 0
133
the slope of the transfer characteristic at IO (input current transfer characteristic is equal to 1pA which corresponds to .01 fF
magnitude). Assuming that the voltage measurement accuracy is variation of the capacitance.
constant, this error is determined for each transfer characteristic.
As an example, Figure 8 reports the transfer characteristic in the 1 Due to the relative error magnitudes, the resolution is not a
limiting factor for this technique.
nA range and -
dvout - 1115 MQ is obtained.
dI0
Parameter Extraction
On Table 2, expected values have been determined using typical
parameters given by the foundry and the following model:

C, = Area x C, + Perimeter X C,
-.- where C, and C, are respectively capacitances per area unit
0.9 0.95 1.oo 1.05 I;, (d) (fF/pm2) and per perimeter unit (fF/pm).
Figure 8: Transfer characteristic of the converter at 1 nA input Based on our experiments, new parameters can be determined to
current. characterize Metal - Polysilicon capacitances. For each test
structure we report (Figure 9) the ratio C versus This
Current control error : AI2 is given by apparatus specifications Area Area .
and is related to IOand to the current source accuracy (+.6 % at 100 variation correspond to a straight line described by the following
nA with HP 4145B). relation:

Slope measurement error: This error is related to the -

C, = c, + Perimeter
oscilloscope used to measure the slope. In our case (HP54501A)it Area Area
comes + = 2.1%. C, and C, are then determined using a linear interpolation:

The first two terms affect the current determination and the third C, = .0377 f .0014 fF/pm2
one the slope determination. It comes:
C, = . W 3 7 f .0055 fF/pm

The following table report the accuracy obtained with input

currents in the 1,100 and lo00 nA range. Some assumptions have
been made, i.e. AV = f20 mV and % = 2.1%.
-k’
Perimetei
Area
0.036 i i * I

0 0.1 0.2 0.3 0.4 (pm-1)

C
m, (d) f.018 1.4 f 12 Figure 9: metal - polysilicon capacitances.Parameter extraction from
experimental results.
f.016 f .6 f 6
Incertitudes are given by the term AC, of Table 2. The high
relative incertitude obtained on C, could be greatly reduced if a
capacitor with a high geometrical ratio (= 1 pr*)has
Area
been studied. The characterization of such a capacitance can be
achieved with two capacitors with geometrical ratio of about .1 and
1pm-’. A third capacitor with a .5 pn-lratio could be useful to verify
the linearity.
Table 3: metal - polysilicon capacitances.Estimation of the relative
measurement error. Biasing dependent capacitances
Relative Measurement Errors are always higher than the At this time, no significantresults have been obtained on biasing
scattering factors report on Table 2 which is consistent with dependent capacitances, i.e. MOS transistor gates in our case. This
statistical and measurement guidelines. The accuracy of measured first study of the method has been realized with a very simple
values is better than 5 %. current detector which is not fast enough to study capacitance
variation with bias (we are now working to implement a faster
Resolutionis fixed by the current source (.1%for HP 4145 B). As current detector). Consequently, the capacitance of the MOS
an example, if a 10 fF capacitance is measured with a 1nA current transistor gate can be studied only in the strong inversion or
and a .1 V / p input signal slope, the minimum current step on the accumulation zone.

For these capacitances it seems that the method previously
proposed using a reference capacitance [4] is more suitable. Since
the reference capacitance can be accurately determined with the
presented measurement technique, a precise knowledge of the
MOS transistor gate could be obtained.
CONCLUSIONS
A new approach for measurement of constant capacitances has
been presented. The major advances are: absolute determination
(no reference elements), pseudo-static behavior (no perturbation
due to stray capacitances) and a strong reduction of matching errors
(the calibration step is achieved on the same device as the
measurement step). Moreover, working conditions of the test
structure are independent of the MOS transistor parameters
(transfer characteristics are scaleable with VddZ). Consequently,
these test structures are particularly well suited for the early
characterization stages of a new process. Resolution of .1 % and
accuracy better than 5 % have been obtained with standard
equipment for capacitance magnitude down to a few fF.
Since an elementary device can be studied, this method is
particularly suitable for spatial scattering studies on a wafer and
statistical characterization of oxide thickness. Moreover, it is
particularly convenient to determine the reference capacitance
used in methods dedicated to biasing dependent capacitances [4].
134
VFERENCES
[l] P. Vitanov, ‘IDimitova and I. Eisele, “Direct capacitance
measurements of small geometry MOS transistors”,
Microelectronics Journal, Vol. 22 (1991), Nos. 7-8, pp. 77-89.
[2] H. Iwai, J.E. Oristian, J.T. Walker and R.W. Dutton, “A
scaleable technique for the measurement of intrinsic MOS
capacitance with atto-Farad resolution”, IEEE Trans. on El.
Dev., Vol. ED-32, No. 2, pp. 344-356, February 1985.
[3] J.J. Paulos and D.A. Antoniadis, “Measurement of
minimum-geometry MOS transistor capacitances”, IEEE
Trans. on El. Dev., Vol. ED-32, No. 2, pp. 357-363, February
1985.
[4] P. Girard, P. Nouet, A. Khalkhal and EM. Roche, “Evaluations of
leakage currents and capacitanceson elementary CMOS devices”,
IEEE IntemationalConferenceon MicroelectronicTest Structures
(ICMTS’93), Sitges, Barcelone, Espagne, March 22-25, 1993, pp.
289-292.
[5] B. Laquai, H. Richter and B. Hofflinger, “A new method and
teststructure for easy determination of fento-Farad on-chip
capacitances in a MOS process”,IEEE IntemationalConference on
Microelectronic Test Structures (ICMTS.92). San Diego. CA,
USA, March 16-19, 1992, pp. 62-66.