High PSRR Nano-Watt MOS-Only Threshold Voltage

Monitor Circuit

Jhon A. Gomez C. Hamilton Klimach Eric Fabris

NSCAD Microeletrônica
PGMicro - UFRGS
Porto Alegre, RS, Brazil
jhon.caicedo@ufrgs.br hamilton.klimach@ufrgs.br
Electrical Engineering Dept. NSCAD Microeletrônica
UFRGS Electrical Engineering Dept.
Porto Alegre, RS, Brazil UFRGS
Porto Alegre, RS, Brazil
eric.fabris@ufrgs.br
Oscar E. Mattia
mmWave group, imec
ETRO, Vrij Universiteit Brussel
Brussel, Belgium
oscar.elisio.mattia@imec.be

ABSTRACT General Terms

This work presents a high PSRR nano-watt resistorless thresh-
old voltage (VT 0 ) monitor circuit that can be used in tem-
perature sensors, voltage and current references, radiation
dosimeters and other applications such as fabrication pro-
cess monitoring and verification. In this circuit design the
MOS transistors operate in subthreshold and near-threshold
regimes, the circuit analysis is based on a current-voltage
relationship derived from a continuous physical MOSFET
model, valid from weak to strong inversion. The bias con-
dition is established from the equilibrium between two self-
cascode cells operating at different inversion levels, and the
high PSRR results from a high gain feedback path. The cir-
cuit is MOSFET-only, and can be implemented in any stan-
dard digital CMOS process. Post-layout simulations show
that it operates with less than 1 V of power supply, con-
suming only tens of nW, and resulting in a VT 0 error lower
than 1%, when compared to its modeling value, for a −40
to +125◦ C temperature range. A very high rejection to
VDD variation is achieved in this design, with PSRR lower
than -63.9 dB at 100 Hz, and a line sensitivity lower than
252 ppm/V was found for a supply range from 1 V to 3 V.
Monte-Carlo simulations are presented to evaluate the fab-
rication variability sensitivity, presenting a maximum error
of 4% for a 3σ spread range. The circuit area is very small,
around 0.0047 mm2 including the start-up stage.
Categories and Subject Descriptors
B.4 [Very Large Scale Integration Design]: Analog and
Mixed-Signal Circuits
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SBCCI ’15, August 31-September 04, 2015, Salvador, Brazil
c 2015 ACM. ISBN 978-1-4503-3763-2/15/08...$15.00
DOI: http://dx.doi.org/10.1145/2800986.2801009
Design, Theory, Performance.
Keywords
Threshold Voltage, CMOS, PSRR, Inversion Level.
1. INTRODUCTION
A threshold voltage monitor is a circuit that ideally de-
livers the estimated VT 0 value as a voltage at its output, for
a given temperature range, without external biases, para-
metric setups, curve fitting or any subsequent calculation.
It can be used in temperature sensors, voltage and current
references, radiation dosimeters and other applications since
the MOSFET VT 0 dependence on the operation conditions
is a very well modeled aspect. Also, it can be used for fab-
rication process monitoring and verification, since VT 0 is a
key parameter for the transistor behavior and modeling.
Through the years, many threshold voltage monitor topolo-
gies have been proposed. Early works [3, 5, 7, 13, 15] were
focused on the strong inversion quadratic MOSFET model
for the drain current, being limited to a specific condition of
operation and presenting high power consumption. In [12]
the proposed circuit is based on the channel conductance-to-
current ratio (gch /id ) methodology and a MOSFET model
that is continuous from weak to strong inversion was used [4].
For its proper design, the circuit in [12] requires a good es-
timation of the specific current, that is a process related
modeling parameter, to correctly bias the transistor. Recent
works [8, 9] use the same transistor model, but the devices
are biased in a process independent condition, resulting that
these circuits do not need any previous estimation to deliver
the VT 0 value. These last works, however, do not achieve
good results regarding some important performance charac-
teristics like Power Supply Rejection Ratio (PSRR) or line
sensitivity (LS), much needed features of a circuit that would
be a part of a system.
In this paper we present a high PSRR and low LS self-
biased circuit topology, that allows the direct extraction of
the threshold voltage for wide temperature and power sup-
ply voltage ranges, with small error. Its design methodol-

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ogy is based on the Unified Current Control Model (UICM)
model [4], a MOSFET model that is continuous from weak to
strong inversion and from triode to saturation regions. It oc-
cupies a small silicon area, consumes just tens of nanoWatts,
and can be implemented in standard digital CMOS process,
since it only uses MOS transistors (does not need any resis-
tor).
The text is organized as follows: section 2 presents the
necessary equations for the UICM MOSFET model, while
section 3 presents the threshold voltage monitor concept,
the PSRR improvement and the start-up stage. In section
4 the circuit design is detailed, while section 5 contains the
relevant simulation results of the circuit implemented in a
0.13 μm CMOS processes, including Monte Carlo variability
analysis. Finally, in section 6 the main conclusions of the
paper are drawn.
2. UICM MOSFET MODEL
The transistors used in the proposed circuit operate both
under weak and moderate inversion levels, meaning that the
circuit analysis requires a model that describes continuously
all operation regions, as done in the UICM MOSFET model
[4]. In this model the drain current ID of a long-channel
device is expressed as
ID = IF − IR = SISQ (if − ir )
where IF and IR are the forward and reverse currents, S =
W/L is the aspect ratio, W being the width and L the length
of the transistor. if and ir are the forward and reverse in-
version coefficients, related to the source and drain inversion
charge densities, while ISQ is the sheet normalization tran-

sistor current ISQ = 12 nμCox φ2t , where n is the subthreshold
slope factor, μ is the channel effective mobility (both slightly
dependent on the gate voltage VG ), Cox 
is the gate capac-
itance per unit area, and φt is the thermal voltage. The
relationship between the inversion levels if and ir and the
terminal voltages is given by
 
VP − VS(D)
= F (if (r) ) = 1 + if (r) −2+ln( 1 + if (r) −1)
φt
(2)
where VS and VD are the source and drain voltages (all ter-
minal voltages are referenced to the transistor bulk voltage),
and VP is the pinch-off voltage, approximated by
VG − VT 0
VP  (3)
n of M1 and M2 . Remembering that if 2 = ir1 , allows us to
being VT 0 the threshold voltage for zero bulk bias. The
UICM is a bulk (or substrate) referenced model and all ter-
minal voltages are given using this terminal as a reference.
In this model the threshold voltage has a universal physical
meaning, defined by the condition where the drift (square
root term) and diffusion (logarithmic term) components of
the drain current in (2) have equivalent magnitude. In the
forward saturation condition, IF  IR in (1), and conse-
quently ID  IF = SISQ if .
3. CIRCUIT DESCRIPTION
3.1 VT 0 Monitor Circuit
The threshold voltage monitor circuit, shown in Fig. 1,
was introduced in [9] and it is based on a self-biased current
source topology proposed in [2]. Its DC operating point is
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established by the equilibrium condition of the proportional-
to-absolute-temperature (PTAT) voltages generated by two
self-cascode (SC) cells that are clamped together. One of
the SC cells operates in moderate inversion (M1,2 ), while the
other SC cell operates in weak inversion (M3,4 ). Transistors
M5 -M10 act as a voltage-following current mirror [6], making
all the currents equal to IX and forcing VX1,2 = VX3,4 .











   








       

Figure 1: VT 0 monitor circuit basic topology.
(1) The voltage at the intermediate node of a self-cascode cell
has been already shown to be a PTAT voltage, whenever
both transistors operate at constant inversion levels [10], and
the absolute value of the PTAT voltage (and its derivative)
can be adjusted by the inversion levels of the transistors.
Additionally, the upper transistors in a SC cell (M2,4 in Fig.
1) have to be in saturation, whereas the lower transistors
M1,3 are in triode. The use of (1), (2) and (3) demonstrates
that
VX1,2 = φt [F (if 1 ) − F (if 2 )] (4)
VX3,4 = φt [F (if 3 ) − F (if 4 )] (5)
where VX1,2 and VX3,4 are ideally PTAT for any inversion
level, as long as if 1−4 are kept constant over temperature.
From (2) and (3), one can see that a NMOSFET with
grounded source and with a gate voltage VG equal to the
threshold voltage VT 0 operates under a constant forward in-
version level equal to 3 (if = 3). Suppose that M1 operates
under such condition, being in the moderate inversion re-
gion. The current IX is defined based on the inversion levels
write
ID1 = S1 ISQ (3 − if 2 ) = ID2 + ID5 = 2IX (6)
where if 2 defines the voltage VX1,2 according to (4). The
inversion levels if 3−4 can then be defined to make VX1,2 =
VX3,4 , and the circuit operates in equilibrium.
3.2 PSRR and Line Sensitive improvement
The basic topology shown in Fig. 1 exhibits a high sen-
sitivity to changes in the supply voltage (VDD ), resulting in
a poor LS and PSRR, due to the limited output impedance
of the current mirror, formed by the M7 -M10 transistors. A
possible solution to increase its output impedance would be
the use of cascode current sources, rather than single tran-
sistors, but the transistor stacking would increase the mini-
mum operating supply voltage. A better option is to aggre-
gate an Operational Amplifier (OA) [1] that add a high gain
feedback path resulting an effective increase in the output
impedance of the mirror without increasing the minimum
supply voltage.
Fig. 2 shows the VT 0 monitor circuit with the OA con-
nected. Note that M7 is no longer diode-connected, so its
drain can move to the same voltage of the drain of M2 .
The OA compares the drain voltage of M2 with the drain
voltage of M5 and force them to be approximately equal, ad-
justing the current mirror bias. Fig. 3 shows the low volt-
age pseudo-differential amplifier that was used, where the
PMOS transistors form a current mirror while the NMOS
ones operate as a differential amplifier. When both inputs
are equal, both branches of the mirror are in equilibrium. If
the inputs are not equal, this imbalance causes the amplifier
output to swing up or down providing the desired action.









 







Figure 2: VT 0 monitor topology with improved LS
and PSRR.









Figure 3: Pseudo-Differential Amplifier.
3.3 Start-up Circuit
As the VT 0 monitor circuit is a self-biased structure it
presents two DC stability operation points, one in the de-
sired bias condition in which the SCs has the same PTAT
voltage, and another when the current in all branches are
zero. Start-up circuit that can prevent the zero-current con-
dition is necessary.
Fig. 4 shows the topology with the start-up circuit. Note
that M11 and M12 are turned off when the circuit is in normal
operation because of the loaded CL capacitance, resulting
in a zero extra current consumption, which is a desirable
characteristic in nano-Watt circuits.
The start-up circuit works as follows: supposing the capaci-
tor CL discharged, when the VDD voltage starts to increase,
M12 drives a current into the SC M1,2 initializing the circuit,
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and simultaneously M11 delivers a current into the capaci-
tor CL , charging it and eventually moving M11,12 to the
cut-off state.

















  










Figure 4: VT 0 monitor with Start-Up circuit and im-


proved LS and PSRR
4. CIRCUIT DESIGN
In the previous analysis it was supposed for simplicity the

 same current in all branches of the current mirror, and now
in the design section it is convenient that these currents IX
are defined as a fraction of the specific current, according to
the transistor current model being used herein. IX is then

 normalized as follows:
IX = ISQ /A (7)
where A is a design constant factor that can be used to deter-
mine the power consumption of the whole circuit (ITOTAL =
4IX ). We also define another design constant B = if 2 /if 3 ,
that sets the ratio between the inversion levels of the tran-
sistors of each SC cell.
Since our objective is to set the gate-source voltage of M1
to be equal to VT 0 , we must chose if 1 = 3, and then VX,12
is determined solely from if 2 , according to (4). Then the
forward inversion level of M3 can be defined by the design
constant B, and finally the ratio if 4 /if 3 can be adjusted to
make VX3,4 equal to VX1,2 , that is a condition presented in
section III.
As a design example we choose if 2 = 0.5, A = 10 and
B = 5, leading to VX1,2 = VX3,4 = 58mV and if 3 = 0.1.
Once VX3,4 and if 3 are known the value of if 4 = 0.001
is easily obtained, and the sizing of the transistors can be
determined from (1) and (6).
A design technique that can be used to improve the circuit
behavior is the implementation of the main transistors (M1 -
M4 ) through the parallel and series composition of unitary
devices, that are assumed to have the same process char-
acteristics (VT 0 , ISQ , n, and so on). Using the common-
centroid layout strategy also helps to improve the circuit,
since a regular layout and the use of dummy devices can
minimize the mismatch of the threshold voltage. The sizes of
M1 -M4 becomes that of Table 1 for the design example pre-
viously showed and using a unitary transistor of W = 2μm
and L = 5μm.
The OA design requires a relationship between the ad-
ditional area and power consumption which needs to be con-
sidered. In this design we consider that an additional 10%
of current consumption is adequate. Observe that the in-
version level of the input transistors of the OA are set to 3,
 4
Table 1: Sizing of M1 -M4 . 500 UICM
Vout 2

Difference [mV]
A = 10, B = 5 M1 M2 M3 M4 480

VT0 [mV]
W (μm) 2 2 5*2 20*2 460 0

L (μm) 5*5 2*5 5 5 440 -2

2
Area (μm ) 50 20 50 200 420
-4
400
-50 0 50 100 -50 0 50 100
since their sources are grounded and their gate voltages are


equal to VT 0 . Once we know the current and the inversion Temperature [°C]
level (if ) it is easy to size the transistors. Table 2 presents
the sizing of the auxiliary structures as the OA, start-up and Figure 6: (a) VT 0 value and (b) difference from the
current sources. monitor circuit (Vout) and from the gm /id model
(UICM) vs temperature
Table 2: Sizing of the auxiliary structures.
M5-6 M7-10 M11 M12 M13-14 M15-16 voltage with an absolute error lower than 1% for the -40 to
W (μm) 10*4 6.25*4 0.5 0.5 0.4 0.76 125 ◦ C temperature range.
 
L (μm) 10 5 1 2 45*2 1.3 Vout − VU ICM
(%) = 100 × (8)
2 VU ICM
Area (μm ) 400 125 0.5 1 36 1

1
5. SIMULATIONS RESULTS
0.5
The results presented here are for Cadence Virtuoso post-
layout simulations of our design implemented in IBM 130 nm
Error [%]

process. The layout takes into consideration the good layout 0

matching practices such as common-centroid placement and
dummy structures. The occupied silicon area is 0.0047 mm2 , -0.5
as shown in Fig. 5.
The MOSFETs used in this implementation are standard -1
I/O type, that present higher threshold voltage and also al- -40 -20 0 20 40 60 80 100 120
low a higher VDD voltage (VDDmax ) than the core transis- Temperature [°C]
tors in this CMOS process. Fig. 6(a) presents the VT 0 varia-
tion over temperature estimated by the (gm /id ) method [12] Figure 7: Percentual error in the VT 0 monitored
(labeled UICM), and simulated in the VT 0 monitor circuit value over temperature
of Fig. 4 (labeled Vout). As one can see the two lines are
very close. Fig. 6(b) presents the difference between the VT 0 Fig. 8 shows the Power Supply Rejection Ratio (PSRR)
from the circuit (Vout) and the one estimated analytically of the output, resulting -64 dB from 0 Hz to almost 1 kHz
by the UICM model, resulting a maximum deviation around and for VDD = 1.2 V, which is almost double of the result
5 mV (1%). obtained in previous works.
The error calculation is defined by (8) and presented in
Fig. 7. The monitor circuit tracks the modeling threshold

















    


Figure 8: PSRR of the output over frequency



The circuit consumes only 57 nW at room temperature

Figure 5: Complete Circuit Layout for VDD = 1.2 V, and reaches a maximum of 70 nW at

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125 ◦ C. Fig. 9 presents the VT 0 output value and the cur- individually in each run - Fig. 11 (middle histograms). Both
rent consumption over the supply voltage. The maximum effects are also taken into account in a full variability anal-
line sensitivity is around 250 ppm/V, while the current con- ysis, shown in Fig. 11 (bottom histograms). The results
sumption sensitivity is 378 pA/V, both at 27 ◦ C and for a presented are for VDD = 1.2 V and under three different
supply voltage range from 1 V to 3 V. temperatures: -40, +27 and +125 ◦ C.
-40 °C 27 °C 125 °C
471 57.5 200 200 200
VT0 μ=-4.08mV μ=-3.33mV μ=3.13mV

Process
σ=0.43mV σ=0.48mV σ=0.75mV
100 100 100
Current

Current [nA]
VT0 [mV]

0 0 0
-20 0 20 -20 0 20 -20 0 20
470.5 57 200 200 200
μ=-3.96mV

Mismatch
μ=-3.27mV μ=3mV
σ=5.31mV σ=5.02mV σ=5.13mV
100 100 100

0 0 0
-20 0 20 -20 0 20 -10 0 10 20
470 56.5 200 200 200

Proc.+Mism.
1 1.5 2 2.5 3 μ=-4.14mV μ=-3.35mV μ=2.9mV
σ=5.48mV σ=5.25mV σ=5.28mV
100 100 100
Supply Voltage [V]
0 0 0
-20 -10 0 10 -20 -10 0 10 -20 0 20
Figure 9: VT 0 monitored and Current consumption Error [mV]

vs VDD voltage
Figure 11: Monte Carlo simulations for Process
The start-up behavior was simulated for the corner pro- (top), Mismatch (middle) and both variability ef-
cess cases and presented in Fig. 10, resulting a settling time fects (bottom)
of less than 25 ms in the worst case at 125 ◦ C, which is
acceptable for our proof of concept. As shown in the design methodology, the circuit perfor-
mance depends only on geometrical factors, being less sen-
sitive to process than to mismatch variations, which affect
600 the currents balance and therefore the circuit behavior. One
can verify the different sensitivities when comparing the
maximum spread that results from MC results: (±3σ) =
400 −4.08 ± 1.29 mV for process, that is significantly less than
VT0 [mV]

(±3σ) = −3.96 ± 15.93 mV for mismatch. Finally a max-

200
0
0 10 20 30 40
Time [ms]
Figure 10: Settling time for the corner process cases
Table 3 presents a comparison of recently published thresh-
old voltage monitors. One of the great advantages of our
topology is the very low line sensitivity and high PSRR, pro-
viding low error and comparable power consumption, work-
ing in a wide range of temperature and voltage. Except for
the current consumption that depends on ISQ and varies
from one process to another, similar results can be obtained
in other technologies, and we soon expect to tape out the
proposed circuit.
Slow imum total error in the worst condition, combining process
and mismatch analysis, yields (±3σ) = −4.14 ± 16.44 mV
Typic
Fast that falls within ±20 mV or 4.25% for the whole operating
temperature range.
50 60
6. CONCLUSION
A resistorless self-biased threshold voltage (VT 0 ) monitor
consuming only tens of nW was herein proposed and de-
signed in CMOS. The circuit works over the -40 to +125 ◦ C
temperature and 1 to 3 V supply voltage range with an error
lower than 1%, presenting -64 dB of PSRR and 252 ppm/V
of line sensitivity. Post-Layout and Monte Carlo simulations
for an IBM 130 nm process support the design robustness to
process and mismatch variations. A maximum error of ±20
mV or 4.25% was found for the worst case over the entire op-
erating temperature range, including fabrication variability
effects. The total occupied silicon area is 0.0047 mm2 .

5.1 Fabrication Variability Effects Acknowledgment

The impact of the fabrication variability effects on the out-
put VT 0 value was analysed using Monte Carlo (MC) simula-
tions, where local mismatch effects and average process vari-
ations were simulated separately with 400 runs each. Fig. 11
shows the MC histograms for the error of the extracted VT 0
from circuit simulations, with respect to the theoretical VT 0
obtained from the analytical model, as this model does not
take variations and mismatches into account. For average
process MC all transistors have their parameters changed
equally in each run - Fig. 11 (top histograms). For local
mismatch MC, the parameters of each transistor are varied
The authors also thank the IC-Brazil Program for CAD tools
and MOSIS for silicon prototyping.
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 Table 3: Comparison of recent VT 0 monitor circuits
Characteristic This Work [9] [8] [13] [14] [11] [3] Units

PSRR @100 Hz -63.9 -38.9 -30 --- --- --- --- dB

Line Sensitive 252 3600 46000 480 2562 8000 554 ppm/V
◦
Temperature Range -40 to 125 -40 to 125 -40 to 125 0 to 100 0 to 100 20 to 80 -50 to 100 C
Supply Range 0.97 to 3 0.6 to 1.8 0.6 to 1.2 1 to 3.6 1.9 to 2.1 2 to 2.5 3.5 to 6.5 V
Max. Error 1 1.64 1.3 --- 11 4.3 4.9 %
Power Consumption 57 23 23 50000 290000 387500 --- nW
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