4086 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO.

12, DECEMBER 2018

A High-Precision Resistor-Less CMOS

Compensated Bandgap Reference Based on
Successive Voltage-Step Compensation
Xin Ming , Member, IEEE, Li Hu, Yang-Li Xin, Xuan Zhang, Di Gao, and Bo Zhang, Member, IEEE

Abstract— A curvature-compensated resistor-less bandgap
reference (BGR), which is fabricated in 0.5-μm CMOS process,
is proposed in this paper. The BGR utilizes successive voltage-
step compensation to produce a temperature-insensitive voltage
reference (VR), including one VGS step for first-order compen-
sation and another one for higher order curvature correction.
Moreover, a supply noise bypassing technique is adopted to
achieve good power supply rejection performance up to high
frequency. Experimental results demonstrate that this BGR is
able to produce a VR of 1.196 V with a temperature coefficient
of 3.98 ppm/°C at 3.6-V supply voltage. A power-supply noise
attenuation of −84 dB@100 Hz and −37 dB@100 kHz are easily
achieved, and the line regulation is better than 0.19 mV/V when
supply voltage varies from 2.1 to 5 V. The proposed reference
occupies an active area of 356 μm × 150 μm and consumes a
quiescent current of 38 μA.
Index Terms— Bandgap reference, thermal nonlinearity,
resistor-less, voltage step compensation, high PSR.
I. I NTRODUCTION
H IGH precision voltage reference is a key block in data
converters and power management ICs, which should
not be influenced by process corners, supply noises and
temperature variations [1]. Aiming at reducing TC under
a wide temperature variation range, conventional high-order
curvature compensation is normally achieved with the help
of resistors [2]–[8]. However, for low-current, subthreshold
operations with nanowatt power consumption (i.e. ultra-low
power LSIs), the high resistance requires a large chip area to
be implemented, which makes VRs without resistors become a
more suitable way. Moreover, resistor-less design is preferred
in a standard digital CMOS technology due to the lack of a
quality resistor or low-sheet resistance. These kinds of VRs are
therefore beneficial for area reduction, mask reduction, avail-
able resistor quality and reducing susceptibility to substrate
noise coupling.
Manuscript received December 30, 2017; revised April 10, 2018 and
April 26, 2018; accepted April 29, 2018. Date of publication May 22,
2018; date of current version October 23, 2018. This work was supported
in part by the National Natural Science Foundation of China under Grant
61404020 and in part by the Guangdong Natural Science Foundation of China
under Grant 2014A030310407. This paper was recommended by Associate
Editor Philip K. Mok. (Corresponding author: Xin Ming.)
The authors are with State Key Laboratory of Electronic Thin Films and
Integrated Devices, University of Electronic Science and Technology of China,
Chengdu 610054, China (e-mail: mingxin@uestc.edu.cn).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2018.2834468
1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Recently, low-power resistor-less approaches are reported
to solve the issues mentioned above. For example, resistor-
less VRs with nanowatt power consumption are presented
in [9]–[11]. Since the compensation theory depends on
threshold voltage of MOS transistors, the VRs are easily
affected by variation of process parameters, which is not
a good option for high-precision VR applications. Another
approach is by using BGR circuit without resistors [12]–[15].
For example, a CMOS VR, utilizing ratioed transistors along
with the inverse function method to generate a constant
gain for first-order temperature compensation, is proposed
in [12]. A CMOS sub-bandgap reference is reported in [13] to
abandon op-amps under low-voltage operation. One solution
for nanowatt CMOS LSIs, which consists of an ultra-low
power current reference, a bipolar transistor with negative
temperature dependence, and PTAT voltage generators, has
been developed in [14]. Recently, the novel all-MOSFET low-
power high-PSR VRs for SoC applications at MHz frequency
are proposed in [16] and [17]. However, most of these reported
architectures face a poor thermal coefficient if temperature
changes wildly because it is hard to achieve high-order
compensations for lack of resistors.
An advanced resistor-less curvature-corrected BGR, called
voltage step compensation, is presented in this paper to solve
this problem. The idea is based on generating successive VGS
voltages with different temperature characteristics, which are
used to cancel thermal nonlinearity of the diode voltage step
by step. As a result, the TC is greatly improved. Moreover,
high PSR performance is also achieved with the help of SNBT,
ensuring the voltage accuracy over power supply variation.
The organization of this paper is as follows. Section II
explains the concept of performance enhancement for the
proposed BGR. Section III shows implementation scheme
of the circuit utilizing 0.5μm CMOS process technology.
Section IV presents relevant experimental results and finally,
Section V concludes the paper to prove the superiority.
II. P ROPOSED C URVATURE -C OMPENSATED
R ESISTOR -L ESS BGR
Fig. 1(a) shows concept of the proposed resistor-less BGR
with high-order temperature compensation called VSC. It is
based on voltage-mode topology, consisting of current refer-
ences with different TC, bipolar transistors, and different
VGS step structures. So the final output VREF2 can be

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MING et al.: HIGH-PRECISION RESISTOR-LESS CMOS COMPENSATED BGR 4087

Fig. 2. Simulated current references with different TC.

Fig. 1. Architecture of proposed resistor-less BGR circuit (a) concept of
curvature compensation (b) circuit configuration (c) current reference circuits
with different TC.
given by
 larger TC and nonlinearity compared to IP since threshold
V R E F 2 = V B E + VG S1,PT AT  f irst −order

+ VG S2,nonlinear high−order
where VGS1 step (VSC I) is achieved by a PTAT voltage
generator for partial first-order compensation and VGS2
step (VSC II) works in the subthreshold region with bias
currents of different TC, containing a temperature-dependent
nonlinearity that efficiently cancels logarithmic temperature
dependence of the PN junction voltage VBE . The particular
working principles of the circuit are stated below.
expressed as
μn Cox (W/L)27   2
IP = 1+ 1+(W/L)6 /(W/L)7 (VT ln N )2
2(W/L)6
= δ1 μn Cox (VT )2 = σ T 2−n = σ T 0.5 (2)
I N = δ2 μn Cox VT2 H N (T ) = δ2 μn Cox · (β − αV T T )2 (3)
where
(W/L)27   2
δ1 = 1 + 1 + (W/L)6 /(W/L)7 (ln N )2 (4)
2 (W/L)6
σ = μo Cox (k/q)2 δ1 (5)
(W/L)211   2
δ2 = 1 + 1 + (W/L)10 /(W/L)11 (6)
2(W/L)10
The parameter N is equal to IS3 /IS2 for Q2 and Q3 , k is the
Boltzmann’s constant, n is the electron mobility temperature
exponent with a typical value of 1.5, δ1 and δ2 is a temperature
independent constant (i.e. δ1 = 12.6, δ2 = 0.96 in the design).
αVT is TC of the threshold voltage VTHN at temperature T0 ,
and β = VTHN (T0 ) + αVT T0 . Moreover, advanced negative
feedback technique is applied to restrict channel length modu-
lation (CLM) effect of PMOS current mirrors (i.e. feedback
with Q1 and M1 -M4 for bias current IP ), improving the supply
insensitivity [18].
The simulated temperature characteristics of IP and IN
current reference are shown in Fig. 2 to verify validity of the
theory. As given by equations (2) and (3), these currents have
opposite temperature characteristics and current IN exhibits
voltage VTHN gains a larger TC than thermal voltage VT .
(1) The traditional ways to achieve V PT AT is by using a current
conveyor [19] or a differential pair with a current mirror [14].
However, all these methods mentioned above suffer from poor
power supply rejection ability without negative feedback tech-
niques (i.e. −45.1 dB at 10 Hz in [12]). In this paper, a high
PSR BGR architecture for the first-order temperature compen-
sation is proposed. As shown in Fig. 1(b), the PTAT voltage
generator is constructed by M17 -M21 . Assuming μn = 2μp ,
VTH17 = VTH18 and CLM is neglected for long-channel
devices, the first-order BGR can be given by

A. First-Order Temperature Compensation V R E F 1 = V B E + VG S1|VSG17−VSG18 = V B E + A1 VT (7)

As shown in Fig. 1(c), the resistor-less current references where
utilize MOS resistors R O N to generate bias currents [15],    
where IP with positive TC and IN with negative TC are A1 = 2δ1 λ3 /(W/L) M17 − 1/(W/L) M18 (8)

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4088 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 12, DECEMBER 2018
By properly designing (W/L)M17 and (W/L)M18 , a first-
order compensated reference is achieved. Compared to the
structure presented in [12], it is much simpler and occupies
less chip area, since one differential pair is avoided. Moreover,
the tail current λ1 IP is set a little larger than total current
(I19 +I20 ) and the additional current (= λ1 IP −λ3 IP −IP ) flows
through M21 . This forms a negative feedback loop constructed
by M17 , M19 and M21 , which is a two-pole system with
only one low-frequency pole at the drain of M19 . Therefore,
VREF1 is less affected by supply voltage ripple and a higher
PSR performance is ensured. For example, if node voltage
VF is increased by VDD fluctuation, Vgs21 will be increased
accordingly, leading to a larger IM21 and pulling VF down to
the original state.
B. High-Order Curvature Compensation
The proposed curvature compensation strategy is illustrated
on the right part of Fig. 1(a) and detailed circuit scheme is
shown in VSC II of Fig. 1(b). The goal is to generate a voltage
that has a similar logarithmic temperature dependence of diode
voltage (T ln T ). It is composed of a differential pair biased
with two current reference of different TC (i.e. IP and IN ).
The transistors M23 and M24 stay in the subthreshold region
and match well, where (W/L)M23 is made equal to (W/L)M24 .
When VDS of a MOS transistor is larger than roughly 4VT ,
the subthreshold current I is expressed as [16]
   
W VSG − |VT H P |
I  I0 exp (9)
L ηVT
where I0 (= μ p Cox (η − 1)VT2 ) is a characteristic current, η is
subthreshold slope factor and VTHP is the threshold voltage
of PMOS. Based on equation (9), the nonlinear differential
voltage (VGS2 = VREF2 –VREF1 ) can be given by
T is a partially first-order compensated VR and VGS2 gains
VG S2 = ηVT ln (λ2 I P /I N ) = A2 VT + 2ηVT ln (10)
1 − θT
where
A2 = η [ln (λ2 δ1 /δ2 ) + 2 ln (k/qβ)] (11)
αV T αV T
θ (T0 ) = = 1 (12)
β (T0 ) VT H N (T0 ) + αV T T0
As a result, the term within the logarithm has a positive
concave relationship with respect to temperature, as presented
in equation (10). In order to predict the compensation quanti-
ties accurately, the temperature characteristic of VBE with bias
current I P should be carefully analyzed, which is shown below

V B E (T ) = VT ln I P T −ε E exp VG0 /VT
= VG0 + VT ln (σ E) − (ε − 0.5) VT ln T (13)
where VG0 is bandgap voltage of silicon extrapolated at 0 K,
and E is a temperature-independent constant. The parameter ε
changes according to different IC processes [20]. Combining
equations (7), (10) and (13), the reference VREF2 can be
given by
V R E F 2 = VG0 + [ln (σ E) + A1 + A2 ] VT
− (ε − 0.5) VT ln T + 2ηVT ln T /1 − θ T (14)
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Based on Taylor series expansion ln(1 + x) ≈ x − x2 /2,
equation (14) can be simplified as follows
V R E F 2  VG0 + [ln (σ E) + A1 + A2 ] VT − (ε − 0.5 − 2η)
2ηk ηk
× VT ln T + θ (T0 ) · T 2 + θ (T0 )2 · T 3
q q
(15)
We take the derivative of VREF2 with respect to temperature,
finding the required values of A1 and A2 to give zero TC at T0 .

∂ V R E F 2  k k
0= = [ln (σ E)+ A1 + A2 ]− (ε−0.5−2η)
∂ T T=T0 q q
k 4ηk 3ηk
− (ε−0.5−2η) ln T0 + θ (T0 ) T0 + θ (T0 )2 T02
q q q
(16)
A1 + A2
= (ε−0.5−2η) (1+ln T0 )
−ηθ (T0 ) T0 [4+3θ (T0 ) T0 ]−ln (σ E) (17)
Based on the above analysis, the compensation precision
are mainly determined by A1 , A2 and θ (T0 ), where VSC I
contributes partial first-order compensation and VSC II cancels
residual first-order and high-order TC of VBE (T). For example,
according to (15), the temperature nonlinearity of V B E (T )
can be directly cancelled out by selecting θ for a given T0
in equation (12). The required zero TC at T0 is realized by
setting proper ( A1 + A2 ) in equation (17) (i.e. current ratio λ2
can be fine-tuned to get an optimized value). The 2nd -order
TC in VBE (T ) is completely cancelled out by VSC II while
the 3rd -order quantities are also reduced as well as shown in
equation (15).
The temperature stability of the designed reference is
shown in Fig. 3(a), which is simulated from −5°C to 125°C
using a supply voltage of 3.6V. As can be seen, VREF1
a nonlinear positive TC. With a summation of these two
parameters, the peak-to-peak voltage variation for VREF2 is
0.5mV and TC of 3.6ppm/°C is easily obtained. According
to equation (15), because of using an advanced “VGS
steps” structure to compensate temperature nonlinearity in
V B E (T ), the proposed reference gains more stable temperature
characteristics compared to other resister-less BGR reported
previously [15]. Furthermore, Fig. 3(b) shows voltage stability
when the low temperature range is extended to −40°C. Since
VSC II will affect both first-order and high-order TCs by
different quantities, if we want to enhance the compensa-
tion strength at hot temperature, it will also increase TC
at cold temperature simultaneously. So the optimization is
a balance between high and low temperature range, which
mainly focuses on covering the range from 0°C to 110°C in
the design [21], [22].
Normally, the presence of component mismatches will affect
precision of the proposed BGR with successive VSC tech-
nique. According to equations (7)-(10), the circuit parameter
A1 is a weak function of aspect ratios for MOS transistors
and A2 is only related to size ratio of different devices.
So mismatch effect of the compensation architecture is mainly
determined by variation of threshold voltages for the transistor
MING et al.: HIGH-PRECISION RESISTOR-LESS CMOS COMPENSATED BGR 4089

Fig. 4. Monte Carlo simulation (500 samples) of VREF2 across temperature.

Fig. 3. Simulated output voltage VREF2 versus temperature (a) limited

temperature range (b) extended temperature range.

pairs M17 -M18 and M23 -M24 , where mismatch of the W/L
ratios and BJT are just neglected. This phenomenon will
introduce an additional offset voltage in equation (15), which
should be minimized, aiming at reducing dependence on the
detailed process.
Generally, since the mismatch variation with Gaussian
distribution for MOS transistors is inversely proportional to
√ Fig. 5.
WL [23], this error voltage can be reduced greatly by setting
the device area large. For example, the aspect ratio of M17 -M18
in saturation region are designed to be 3.5/6 and 7/6 respec-
tively, while the aspect ratio of M23 -M24 in subthreshold
region are set to be 420/0.5. Here, a 500-run Monte Carlo
simulation is just utilized in Fig. 4 to assess the circuit stability
due to mismatch and process variation. Moreover, as shown
in Fig. 5(a) for statistics analysis, it is observed that the
simulated mean value (μ) and standard deviation SD (σ )
of the BGR are about 1193.63mV and 43.65mV. The vari-
ation (σ /μ) of the final compensated reference VREF2 is only
3.66% across temperatures. The minimum and maximum TC
before trimming is 3.46ppm/°C and 54.7ppm/°C respectively
in Fig. 5(b). The sensitivity to process variation is thus low
compared to other reported circuits [17], which is suitable for
mass production purpose and reduces the difficulty and chip
area of trimming circuit design.
Statistics of untrimmed VREF2 from a 500-run Monte-Carlo
simulation (a) VREF2 @ 27 °C (b) TC in ppm/°C of VREF2 .
C. High PSR Analysis
Considering PSR performance of the complete circuit
in Fig. 1(b) at low frequency, since self-biased current source
IP and IN are all designed with a feedback loop ②, it can
be regarded as ideal bias currents and PSR at the reference
output is ideally equal to 0 within the feedback loop bandwidth
f GBW2 [17]. However, when the frequency increases beyond
f GBW2 , the noises at the drain of M1 and M14 turns to be
v dd,noise, where only CLM effects should be reconsidered for
PSR design up to a medium frequency range. Assuming the
small-signal output resistance of bias currents IP and IN are roP
and roN respectively, the complete small-signal model for PSR
analysis is obtained in Fig. 6, where the operating frequency
locates in the range that f GBW2 < f < fmedium . The idea

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4090 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 12, DECEMBER 2018

Fig. 6. Small-signal model for PSR analysis up to a medium frequency

range. Fig. 7. Simulated PSR versus frequency at 27°C.

for the PSR enhancement is to utilize multiple low impedance

paths, which bypass ac ripples at the internal nodes of the
BGR to ground before reaching VREF2 .
As can be seen, the supply voltage ripple v dd can leak
through two paths to the reference output VREF2 , where path I
is from VSC I for the first-order temperature compensation and
path II is from VSC II for high-order curvature compensation.
Assisted by the local feedback control in VSC I, which
is composed of M17 , M19 and M21 , the shunt resistance
RF ≈ 1/[gm17 gm21 (ro17 ||ro19)] is relatively small within the
feedback loop bandwidth f GBW1 , leading to a small ac ripple
v REF1 . There is also a small resistor RE to bypass supply noises Fig. 8. The proposed resistor-less BGR including noise sources.
in path II. Based on superposition principle, the final ripple
voltage at v REF2 is equal to v pathI + v pathII , and PSR at this
frequency range can then be calculated as Since M23 is designed with a large aspect ratio and gm17
K 1 K 2 (s) is much smaller than gm23 , path I will mainly determine the
PSR  high frequency PSR. The simulated PSR versus frequency
1 + gm17 gm21 (ro17  ro19 ) · ro P /λ1
K 2 (s) under the condition that VDD = 3.6V and T = 27°C is
+ , shown in Fig. 7. As can be seen, PSRvref2 at 100 Hz and
1 + gm23 · (ro P /λ2  roN )
f G B W 2( f eedback) ≤ f < f G B W 1( f eedback) (18) 1 MHz gains a performance of −86dB and −25dB, respec-
tively. PSRvref2 is better than PSRvref1 at low frequency based
where on the resistive subdivision (i.e. 1/gm24 and roN ) and gains
gm18ro20 similar performance at high frequency owing to the capacitive
K1 = (19)
1 + gm18ro20 coupling effect of Cpar . Moreover, if the BGR circuit works at
gm24roN 1 + s/ Cgm24 several MHz frequency range, supply ripples can couple to the
K 2 (s) = ·
par
(20) reference VREF2 through the parasitic capacitance of M30 -M31 .
1 + gm24roN 1 + s/ 1+gm24roN Output resistance roP and roN in Fig. 6 will lose effect for noise
roN C par

Here the parameter Cpar is equal to Cgs24 + Cdb24 and should
be considered because of a large transistor size of M24 used.
K 2 (s) thus has a zero-pole pair and becomes smaller than 1 at
low frequency. As shown by the blue parts in Fig. 6, based on
small shunt resistance from nodes E and F to ground, the ac
ripple v REF2 is really small, isolating the reference output from
the input supply ripple effectively.
On the other hand, when the frequency is above the GBW
of the feedback loop ① in VSC I, the resistance RF becomes a
little larger. The ripple voltage v REF1 will provide an important
quantity to the total PSR, which is given by
K 1 K 2 (s)
P S R 
1 + gm17ro P /2λ1
K 2 (s)
+ ,
1 + gm23 · (ro P /λ2  roN )
f G B W 1( f eedback) ≤ f < f medium
isolation. Based on this condition, a low-pass filter should be
connected at the output node VREF2 to restrict supply noises
without any extra power consumption. This RC filter will
contribute a high-frequency pole in the transfer function of
PSR and is a design tradeoff with chip area and system cost.
D. Noise Optimization
The noise analysis of the proposed BGR is shown in Fig. 8,
where the noise sources, labeled by different colors in VSC I
and VSC II, are uncorrelated from different devices and will
propagate to the gate of M24 at the reference output. Here,
M18 and M24 will produce no noise if CLM effects in M20 and
M32 are neglected [24], [25]. We just utilize the low frequency
output noise spectral density to assess noise performance.
(21) Since the voltage gain v ref2 /v F = v ref2 /v E ≈ 1, the total output

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MING et al.: HIGH-PRECISION RESISTOR-LESS CMOS COMPENSATED BGR 4091

stage of the starting procedure, transistor M27 will turn on and

there is a charging current flowing into MOS capacitor M25 .
Therefore, node voltage VY rises and the current reference
IP is increased gradually to the required stable state. Finally,
M27 will be shut down when VX reaches VDD and M26 stays
in linear region. The start-up circuit does not disturb normal
functions of the proposed BGR and consumes zero DC current.
The simulated start-up waveforms at different temperature and
corners are shown in Fig. 11 and relevant control voltages at
node X and S are also given to show working principle. As can
be seen, the supply voltage rises to 3.6V in 5μs edge time and
the start-up time in all cases is less than 7μs. A smooth and
fast start-up process is thus ensured. Moreover, in order to
Fig. 9. Simulated total output noise voltage at VREF2 @27°C. reduce device mismatching and CLM effect, all devices in the
current mirrors are implemented with long channel lengths
(i.e. L = 6μm), aiming at realizing perfect temperature
noise voltage can then be given by compensation and high PSR performance.
 
v n,vre
2 = v 2 + v 2  + v 2  As mentioned above, precision of the BGR is generally
f2 d,B E n,F  n,E  (22)
V SC I V SC I I degraded by device mismatches and nonlinear temperature
v d,B
2
E = 2 (kT ) /q I P
2
(23) dependence of the threshold voltage [18], where trimming
  is a useful methodology to eliminate the impacts resulting
v n,F
2  i n20
2 + i2
n29 R F + i n19 (gm21ro19 ) R F
2 2 2 2
from these non-idealities. A two-step trim is just involved to
2 R2 + v 2 realize the target reference value while minimizing the TC by
+ i n21 (24)
 F n17  adjusting bias currents. It is aimed at reducing the voltage vari-
v n,E
2 = i n23 + i n30 + i n31
2 2 2 + i2
n32 (1/gm23 )
2
(25) ation (σ /μ) to be less than 1%. For example, step I is to set the
reference VREF2 to the predetermined value at room temper-
where ature. PTAT term A1 will be adjusted by changing the ratios
4kT γ K 1 of M19 -M20 for first-order compensation, while (W/L)M30 is
v n17
2 = + · (26)
gm17 Cox (W L)21 f initially set to the median value. During step II, the reference
K 1 value is measured at both the minimum (VREF2,min @−5°C)
2
i n21 = 4kT γ gm21 + · · gm21
2
(27)
Cox (W L)21 f and maximum (VREF2,max @125°C) temperatures. If VREF2,min
K 1 is much larger than VREF2,max , it is an under-compensation
2
i n23 = 4kT γ gm23 + · · gm23
2
(28)
Cox (W L)23 f condition and (W/L)M30 is gradually increased by trimming
bits. On the contrary, if VREF2,min is much smaller than
Referring to the current mirror, the diode-connected device
VREF2,max , it is an over-compensation condition and (W/L)M30
will contribute significant flicker noise in the low frequency,
should be decreased. This successive approximation process
and the relevant noise currents can then be expressed as
  is over when VREF2,max ≈ VREF2,min . As shown in Fig. 12,
4kT γ K 1 considering trimming step and range as well as circuit
i ni =
2 + · (Mi + 1) gmi
2
gmi Cox (W L)i f complexity, M30 is laid out as a transistor array with seven
i = 19, 20, 29, 30, 31, 32 (29) binary-weighted devices [15]. The adjusting range for the
width of M30 ranges from 2.5 to 317.5μm, and an optimal
where Mi is the relevant current mirror ratio. value is 80μm. On the other hand, M19 is designed as a five-
According to the above analysis, based on the small device array, where the width can change from 2.5 to 77.5μm
impedance from nodes E and F to ground, the thermal, flicker with an optimal value of 40μm. The detailed information of
and shot noises from MOSFETs and BJTs can be greatly device sizes is shown in table I.
reduced without increasing the transconductance or device The minimum power supply VDD,min should guarantee that
area, relaxing the tradeoff design between noise, power and all the transistors from three function blocks of Fig. 10 works
chip area. Simulation result in Fig. 9 shows that the flat-band
√ in the proper region, including current references and BGR
noise spectral density is about 227nV/ Hz with a bias current core circuit. This is critical to ensure excellent TC and
of 38μA and the 1/f corner frequency is about 20Hz. PSR performance. For example, VDD,min1 of current reference
IP is limited by the path M1 , M2 and Q1 , which can be
III. C IRCUIT R EALIZATION given by
The detailed circuit of this proposed resistor-less BGR is
shown in Fig. 10. It consists of three function blocks, including V D D,min 1 ≥ VSG(M1) + V D S(M2) + V B E(Q 1) (30)
bandgap core circuit and current references with different TC, VDD,min2 of current reference IN is restricted by the path M14 ,
respectively. Since the current reference utilizes self-biasing M15 and M16 , which can be expressed as
technique, a startup circuit is needed to avoid zero biasing
state. For example, the node voltage VX is low at an early V D D,min 2 ≥ VSG(M14) + V D S(M15) + VG S(M16) (31)

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4092 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 12, DECEMBER 2018

Fig. 10. The proposed complete schematic of the high-order curvature compensated BGR.

TABLE I
M AIN D EVICE S IZES

Fig. 11. Simulated start-up waveforms of the proposed voltage reference.

VDD,min can be reduced greatly (i.e. much less than 2V) if

the BGR is fabricated in submicron processes with a smaller
threshold voltage VTHP .
Fig. 12. Trimming schematic for transistor M30 .

IV. E XPERIMENTAL R ESULTS AND D ISCUSSION

VDD,min3 resulting from BGR core circuit is due to the path
Q3 , M17 and M29 , which can be shown below
V D D,min 3 ≥ V B E(Q 3 ) + VSG(M17) + VS D(M29)
The designed VDD,min is the maximum value of these three
constraints. In the selected 0.5μm CMOS process, VTHN and
|VTHP | are about 0.8 and 0.77V at room temperature. The
overdrive voltage of MOS transistors in saturation region is
designed to be about 100-200mV. Therefore, the minimum
supply voltage is about 2.1V, which is mainly restricted by
VSG of PMOS transistors as shown in equations (30)-(32).
The resistor-less BGR in Fig. 10 has been fabricated
in standard 0.5μm CMOS process, where αVTn is about
(32) −1.77 mV/°C. Fig. 13 shows the chip micrograph, which
occupies an active area of 356 × 150μm2. Here, common-
centroid layout technique is adopted for both BJTs and MOS
transistors with the purpose of limiting process mismatch
effect. Moreover, additional dummy devices are utilized for the
critical transistors to achieve better matching, such as current
mirrors and input pair M17 -M18 .
Ten BGR circuits are measured to prove the stable perfor-
mance with process variation. Fig. 14 shows the tested

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MING et al.: HIGH-PRECISION RESISTOR-LESS CMOS COMPENSATED BGR
Fig. 13. Micrograph of the proposed bandgap voltage reference.
Fig. 14. Measured temperature dependence for different supply voltage.
temperature characteristics of a single trimmed device at
different supply voltages (i.e. VIN = 2.1, 3.6, and 5V). As can
be seen, referring to the typical application VDD = 3.6V, high-
order compensation takes effect when T > 70°C based on
optimized parameters (i.e. λ2 = 8 and λ3 = 5). Peak-to-peak
voltage variation is about 0.62mV and a stable voltage refer-
ence is achieved in the wide temperature range. A little larger
voltage variation, compared to the simulation, is observed in
measured result, because the VR is a sensitive block, which is
easily affected by random offset, mismatches from BJTs and
current mirrors. Ten random samples’ performance, every one
of which is trimmed to the same designed value, is shown
in Fig. 15. The maximum voltage variation, resulting from
any of these VRs, is less than 1.3mV. With the help of
advanced VSC technique for curvature compensation, a stable
temperature characteristic is achieved with the proposed
resistor-less BGR.
Table II just shows detailed data of the measured BGR at
room temperature and the relevant TCs for the ten untrimmed
and trimmed samples. Here, the voltage variation (σ /μ) is
utilized to evaluate the proposed BGR performance, where the
value of untrimmed circuits and trimmed ones is about 1.48%
and 0.62%, respectively. The TCs of the untrimmed BGRs is
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4093
Fig. 15. Measured temperature dependence of ten trimmed samples.
TABLE II
M EASURED V REF AND TC OF T EN S AMPLES
from 13.66 to 4.81 ppm/°C and the average value is about
9.72 ppm/°C. However, TCs of the trimmed ones range from
8.29 to 3.98 ppm/°C with an average value of 5.87 ppm/°C.
According to the measured results, the designed trim step and
adjusting range are well suited to ensure a good accuracy of
the BGR.
The power-supply dependence of the measured three
samples at room temperature is shown in Fig. 16. The
proposed BGR can operate normally when the supply voltage
is above 2.1 V and the line regulation is only about 0.19mV/V.
Fig. 17 shows power supply rejection ability versus frequency
without any output filter capacitor. During the PSR measure-
ment, the peak–peak voltage of supply ripple is approximately
100 mV during the entire frequency range and the ac ripple at
the reference output are monitored with the help of a low-noise
high-bandwidth post amplifier. By utilizing SNBT in the BGR
as shown in Fig. 6, the measured PSR is −84dB at 100Hz and
−37dB at 100 kHz.
Table III summarizes the performance of the proposed BGR
and makes a comparison with other reported ones recently.
The proposed high-precision voltage reference is stable with
respect to TC and PSR. Compared to the BGR with resis-
tors in [1] and [3], the curvature compensation architecture
4094 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 12, DECEMBER 2018

TABLE III
P ERFORMANCE S UMMARY AND C OMPARISON W ITH P REVIOUS W ORKS

although the offset voltage of error amplifier can be canceled,

the circuit is very complex to realize low TC and occupies
a larger chip area resulting from large transistor sizes and
switched capacitors adopted. Furthermore, the reported refer-
ences without resistors in [14] and [17] are all realized with
only simple temperature compensation, so the TCs achieved
are not as good as the proposed work. The advantages are even
more obvious if the circuit is designed with smaller technology
nodes, including the minimum supply voltage and chip area
consumption. On the other hand, compared to the reported
high-order compensated resistor-less BGR [15], the proposed
Fig. 16. Measured reference voltage versus supply voltage at 27°C. circuit is much simpler to realize a high-precision reference.
For example, by changing compensation methodology from
VBE linearization to VSC, the inverse-function technique to
achieve first-order BGR, and current subtractor as well as
translinear circuit to realize high-order compensation are no
longer used in order to save additional current mirrors and
op amps. Chip area, supply voltage, power consumption and
impacts of process variation are thus reduced greatly with a
better TC. PSR performance up to medium frequency is also
improved by feedback control and SNBT while the previous
one is only determined by CLM effect of current mirrors.

Fig. 17. Measured output supply rejection versus frequency at 27°C.
is much simpler to achieve similar TC and higher PSR
performance without using many op amps. This can simplify
circuit and layout design greatly. It also achieves a compet-
itive performance in a low-cost CMOS process compared
to [8], which should be implemented in BiCMOS technology,
limiting its applications especially for power management IC
design. Referring to the low-power switched-mode BGR in [5],
V. C ONCLUSION
This paper shows a high-precision, area-efficient curvature
compensated BGR without resistors. It utilizes VSC concept,
consisting of different resistor-less current references, PTAT
voltage generator and VGS steps for high-order temperature
compensation. Moreover, high PSR performance is achieved
by utilizing small shunt resistance to bypass supply ripple
to ground before reaching the reference output. Experimental
results demonstrate that an output voltage with a good temper-
ature stability (TC ≈ 3.98ppm/°C) and power supply rejection
ability (PSR ≈ −84dB at DC frequency) can be easily

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MING et al.: HIGH-PRECISION RESISTOR-LESS CMOS COMPENSATED BGR
achieved without consuming much chip area. Future research
work is to lower TC and power dissipation in a wider tempera-
ture range. That will greatly expand applications of the voltage
reference in power management IC design.
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Xin Ming received the M.Sc. and Ph.D. degrees
in microelectronics from the University of Elec-
tronic Science and Technology of China (UESTC),
Chengdu, China, in 2007 and 2012, respectively.
From 2013 to 2014, he was a Visiting Scholar
with the Center for Power Electronics Systems,
Virginia Polytechnic Institute and State Univer-
sity, Blacksburg, USA, where his research activity
was ripple-based control circuit design. He is
currently an Associate Professor with UESTC. His
current research interests include Class D amplifiers,
switching power supply, LDO, and GaN drivers.
Li Hu received the bachelor’s degree fromthe Infor-
mation Science and Technology College, Southwest
Jiaotong University, Chengdu, China, in 2016, where
she is currently pursuing the Ph.D. degree with the
State Key Laboratory of Electronic Thin Films and
Integrated Devices. Her current research interests
are dead-time control for dc–dc converters and GaN
driver.
Yang-Li Xin received the bachelor’s degree from
the Micro and Solid-Electronics College, University
of Electronic Science and Technology of China,
Chengdu, China, in 2016, where he is currently
pursuing the M.S. degree with the Power Integration
Technology Laboratory. His current research inter-
ests include circuit design of dc–dc converter, LDO,
and gate driver.
Xuan Zhang received the bachelor’s degree from
the Micro and Solid-Electronics College, University
of Electronic Science and Technology of China,
Chengdu, China, in 2016, where she is currently
pursuing the Ph.D. degree with the State Key
Laboratory of Electronic Thin Films and Integrated
Devices. Her current research interests include GaN
drivers and converters and low-dropout regulator.
4096 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 12, DECEMBER 2018

Di Gao received the bachelor’s degree from the Bo Zhang received the B.S. degree in electronic
Micro and Solid-Electronics College, University engineering from the Beijing Institute of Technology
of Electronics Science and Technology of China, in 1985 and the M.S. degree in electronic engi-
Chengdu, China, in 2015, where he is currently neering from the University of Electronic Science
pursuing the Ph.D. degree with the State Key and Technology of China (UESTC) in 1988. From
Laboratory of Electronic Thin Films and Integrated 1988 to 1996, he was involved in power semi-
Devices. His current research interests include issues conductor devices research and development at the
of loop stability in power systems including dc–dc UESTC. From 1996 to 1999, he was a Visiting
converter, LDO, and voltage reference. Professor with the Center for Power Electronics
Systems, Virginia Polytechnic Institute and State
University, Blacksburg, USA, where his research
activity was modern power semiconductor devices. In 1999, he returned to
UESTC, where he has been involved in power devices and smart power inte-
grated circuits. He is currently a Full Professor with UESTC and the Director
of Center for Integrated Circuits, UESTC. His research interest has been
focused on the power semiconductor technology since 1987, including power
discrete devices, power management ICs, and power integrated technology.
He holds over 100 China or U.S. patents. He has published and presented
over 400 technical papers in scientific journals and international conferences.
He was a member of the IEEE EDS Power Devices and ICs Committee
from 2014 to 2017 and the TPC member of the International Symposium on
Power Semiconductor Devices and ICs from 2010 to 2015. He has been an
IEEE Chengdu Section EXCOM Member and the Chair of the Technology
Committee since 2006. He is also the Editor of the IEEE T RANSACTIONS
ON E LECTRON D EVICES . His work has received over 4000 citations, with
h-index of 31 and i10 index of 134 (source: Google Scholar).

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